clock.c 11 KB

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  1. /*
  2. * TNETV107X: Clock management APIs
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm-generic/errno.h>
  8. #include <asm/io.h>
  9. #include <asm/processor.h>
  10. #include <asm/arch/clock.h>
  11. #define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
  12. #define PSC_BASE TNETV107X_PSC_BASE
  13. #define BIT(x) (1 << (x))
  14. #define MAX_PREDIV 64
  15. #define MAX_POSTDIV 8
  16. #define MAX_MULT 512
  17. #define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
  18. /* LPSC registers */
  19. #define PSC_PTCMD 0x120
  20. #define PSC_PTSTAT 0x128
  21. #define PSC_MDSTAT(n) (0x800 + (n) * 4)
  22. #define PSC_MDCTL(n) (0xA00 + (n) * 4)
  23. #define PSC_MDCTL_LRSTZ BIT(8)
  24. #define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
  25. #define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
  26. /* SSPLL registers */
  27. struct sspll_regs {
  28. u32 modes;
  29. u32 postdiv;
  30. u32 prediv;
  31. u32 mult_factor;
  32. u32 divider_range;
  33. u32 bw_divider;
  34. u32 spr_amount;
  35. u32 spr_rate_div;
  36. u32 diag;
  37. };
  38. /* SSPLL base addresses */
  39. static struct sspll_regs *sspll_regs[] = {
  40. (struct sspll_regs *)(CLOCK_BASE + 0x040),
  41. (struct sspll_regs *)(CLOCK_BASE + 0x080),
  42. (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
  43. };
  44. #define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
  45. #define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
  46. #define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
  47. /* PLL Control Registers */
  48. struct pllctl_regs {
  49. u32 ctl; /* 00 */
  50. u32 ocsel; /* 04 */
  51. u32 secctl; /* 08 */
  52. u32 __pad0;
  53. u32 mult; /* 10 */
  54. u32 prediv; /* 14 */
  55. u32 div1; /* 18 */
  56. u32 div2; /* 1c */
  57. u32 div3; /* 20 */
  58. u32 oscdiv1; /* 24 */
  59. u32 postdiv; /* 28 */
  60. u32 bpdiv; /* 2c */
  61. u32 wakeup; /* 30 */
  62. u32 __pad1;
  63. u32 cmd; /* 38 */
  64. u32 stat; /* 3c */
  65. u32 alnctl; /* 40 */
  66. u32 dchange; /* 44 */
  67. u32 cken; /* 48 */
  68. u32 ckstat; /* 4c */
  69. u32 systat; /* 50 */
  70. u32 ckctl; /* 54 */
  71. u32 __pad2[2];
  72. u32 div4; /* 60 */
  73. u32 div5; /* 64 */
  74. u32 div6; /* 68 */
  75. u32 div7; /* 6c */
  76. u32 div8; /* 70 */
  77. };
  78. struct lpsc_map {
  79. int pll, div;
  80. };
  81. static struct pllctl_regs *pllctl_regs[] = {
  82. (struct pllctl_regs *)(CLOCK_BASE + 0x700),
  83. (struct pllctl_regs *)(CLOCK_BASE + 0x300),
  84. (struct pllctl_regs *)(CLOCK_BASE + 0x500),
  85. };
  86. #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
  87. #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
  88. #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
  89. #define pllctl_reg_rmw(pll, reg, mask, val) \
  90. pllctl_reg_write(pll, reg, \
  91. (pllctl_reg_read(pll, reg) & ~(mask)) | val)
  92. #define pllctl_reg_setbits(pll, reg, mask) \
  93. pllctl_reg_rmw(pll, reg, 0, mask)
  94. #define pllctl_reg_clrbits(pll, reg, mask) \
  95. pllctl_reg_rmw(pll, reg, mask, 0)
  96. /* PLLCTL Bits */
  97. #define PLLCTL_CLKMODE BIT(8)
  98. #define PLLCTL_PLLSELB BIT(7)
  99. #define PLLCTL_PLLENSRC BIT(5)
  100. #define PLLCTL_PLLDIS BIT(4)
  101. #define PLLCTL_PLLRST BIT(3)
  102. #define PLLCTL_PLLPWRDN BIT(1)
  103. #define PLLCTL_PLLEN BIT(0)
  104. #define PLLDIV_ENABLE BIT(15)
  105. static int pll_div_offset[] = {
  106. #define div_offset(reg) offsetof(struct pllctl_regs, reg)
  107. div_offset(div1), div_offset(div2), div_offset(div3),
  108. div_offset(div4), div_offset(div5), div_offset(div6),
  109. div_offset(div7), div_offset(div8),
  110. };
  111. static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
  112. static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
  113. /* Mappings from PLL+DIV to subsystem clocks */
  114. #define sys_arm1176_clk {SYS_PLL, 0}
  115. #define sys_dsp_clk {SYS_PLL, 1}
  116. #define sys_ddr_clk {SYS_PLL, 2}
  117. #define sys_full_clk {SYS_PLL, 3}
  118. #define sys_lcd_clk {SYS_PLL, 4}
  119. #define sys_vlynq_ref_clk {SYS_PLL, 5}
  120. #define sys_tsc_clk {SYS_PLL, 6}
  121. #define sys_half_clk {SYS_PLL, 7}
  122. #define eth_clk_5 {ETH_PLL, 0}
  123. #define eth_clk_50 {ETH_PLL, 1}
  124. #define eth_clk_125 {ETH_PLL, 2}
  125. #define eth_clk_250 {ETH_PLL, 3}
  126. #define eth_clk_25 {ETH_PLL, 4}
  127. #define tdm_clk {TDM_PLL, 0}
  128. #define tdm_extra_clk {TDM_PLL, 1}
  129. #define tdm1_clk {TDM_PLL, 2}
  130. static const struct lpsc_map lpsc_clk_map[] = {
  131. [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
  132. [TNETV107X_LPSC_GEM] = sys_dsp_clk,
  133. [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
  134. [TNETV107X_LPSC_TPCC] = sys_full_clk,
  135. [TNETV107X_LPSC_TPTC0] = sys_full_clk,
  136. [TNETV107X_LPSC_TPTC1] = sys_full_clk,
  137. [TNETV107X_LPSC_RAM] = sys_full_clk,
  138. [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
  139. [TNETV107X_LPSC_LCD] = sys_lcd_clk,
  140. [TNETV107X_LPSC_ETHSS] = eth_clk_125,
  141. [TNETV107X_LPSC_AEMIF] = sys_full_clk,
  142. [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
  143. [TNETV107X_LPSC_TSC] = sys_tsc_clk,
  144. [TNETV107X_LPSC_ROM] = sys_half_clk,
  145. [TNETV107X_LPSC_UART2] = sys_half_clk,
  146. [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
  147. [TNETV107X_LPSC_SECCTL] = sys_half_clk,
  148. [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
  149. [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
  150. [TNETV107X_LPSC_GPIO] = sys_half_clk,
  151. [TNETV107X_LPSC_MDIO] = sys_half_clk,
  152. [TNETV107X_LPSC_SDIO0] = sys_half_clk,
  153. [TNETV107X_LPSC_UART0] = sys_half_clk,
  154. [TNETV107X_LPSC_UART1] = sys_half_clk,
  155. [TNETV107X_LPSC_TIMER0] = sys_half_clk,
  156. [TNETV107X_LPSC_TIMER1] = sys_half_clk,
  157. [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
  158. [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
  159. [TNETV107X_LPSC_SSP] = sys_half_clk,
  160. [TNETV107X_LPSC_TDM0] = tdm_clk,
  161. [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
  162. [TNETV107X_LPSC_MCDMA] = sys_half_clk,
  163. [TNETV107X_LPSC_USB0] = sys_half_clk,
  164. [TNETV107X_LPSC_TDM1] = tdm1_clk,
  165. [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
  166. [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
  167. [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
  168. [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
  169. [TNETV107X_LPSC_SPARE] = sys_half_clk,
  170. [TNETV107X_LPSC_SDIO1] = sys_half_clk,
  171. [TNETV107X_LPSC_USB1] = sys_half_clk,
  172. [TNETV107X_LPSC_USBSS] = sys_half_clk,
  173. [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
  174. [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
  175. };
  176. static const unsigned long pll_ext_freq[] = {
  177. [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
  178. [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
  179. [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
  180. };
  181. static unsigned long pll_freq_get(int pll)
  182. {
  183. unsigned long mult = 1, prediv = 1, postdiv = 1;
  184. unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
  185. unsigned long ret;
  186. u32 bypass;
  187. bypass = __raw_readl((u32 *)(CLOCK_BASE));
  188. if (!(bypass & pll_bypass_mask[pll])) {
  189. mult = sspll_reg_read(pll, mult_factor);
  190. prediv = sspll_reg_read(pll, prediv) + 1;
  191. postdiv = sspll_reg_read(pll, postdiv) + 1;
  192. }
  193. if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
  194. ref = pll_ext_freq[pll];
  195. if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
  196. return ref;
  197. ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
  198. ret /= (prediv * postdiv);
  199. return ret;
  200. }
  201. static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
  202. int div)
  203. {
  204. int divider = 1;
  205. unsigned long divreg;
  206. divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
  207. if (divreg & PLLDIV_ENABLE)
  208. divider = (divreg & pll_div_mask[pll]) + 1;
  209. return fpll / divider;
  210. }
  211. static unsigned long pll_div_freq_get(int pll, int div)
  212. {
  213. unsigned int fpll = pll_freq_get(pll);
  214. return __pll_div_freq_get(pll, fpll, div);
  215. }
  216. static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
  217. unsigned long hz)
  218. {
  219. int divider = (fpll / hz - 1);
  220. divider &= pll_div_mask[pll];
  221. divider |= PLLDIV_ENABLE;
  222. __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
  223. pllctl_reg_setbits(pll, alnctl, (1 << div));
  224. pllctl_reg_setbits(pll, dchange, (1 << div));
  225. }
  226. static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
  227. {
  228. unsigned int fpll = pll_freq_get(pll);
  229. __pll_div_freq_set(pll, fpll, div, hz);
  230. pllctl_reg_write(pll, cmd, 1);
  231. /* Wait until new divider takes effect */
  232. while (pllctl_reg_read(pll, stat) & 0x01);
  233. return __pll_div_freq_get(pll, fpll, div);
  234. }
  235. unsigned long clk_get_rate(unsigned int clk)
  236. {
  237. return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
  238. }
  239. unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
  240. {
  241. unsigned long fpll, divider, pll;
  242. pll = lpsc_clk_map[clk].pll;
  243. fpll = pll_freq_get(pll);
  244. divider = (fpll / hz - 1);
  245. divider &= pll_div_mask[pll];
  246. return fpll / (divider + 1);
  247. }
  248. int clk_set_rate(unsigned int clk, unsigned long _hz)
  249. {
  250. unsigned long hz;
  251. hz = clk_round_rate(clk, _hz);
  252. if (hz != _hz)
  253. return -EINVAL; /* Cannot set to target freq */
  254. pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
  255. return 0;
  256. }
  257. void lpsc_control(int mod, unsigned long state, int lrstz)
  258. {
  259. u32 mdctl;
  260. mdctl = psc_reg_read(PSC_MDCTL(mod));
  261. mdctl &= ~0x1f;
  262. mdctl |= state;
  263. if (lrstz == 0)
  264. mdctl &= ~PSC_MDCTL_LRSTZ;
  265. else if (lrstz == 1)
  266. mdctl |= PSC_MDCTL_LRSTZ;
  267. psc_reg_write(PSC_MDCTL(mod), mdctl);
  268. psc_reg_write(PSC_PTCMD, 1);
  269. /* wait for power domain transition to end */
  270. while (psc_reg_read(PSC_PTSTAT) & 1);
  271. /* Wait for module state change */
  272. while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
  273. }
  274. int lpsc_status(unsigned int id)
  275. {
  276. return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
  277. }
  278. static void init_pll(const struct pll_init_data *data)
  279. {
  280. unsigned long fpll;
  281. unsigned long best_pre = 0, best_post = 0, best_mult = 0;
  282. unsigned long div, prediv, postdiv, mult;
  283. unsigned long delta, actual;
  284. long best_delta = -1;
  285. int i;
  286. u32 tmp;
  287. if (data->pll == SYS_PLL)
  288. return; /* cannot reconfigure system pll on the fly */
  289. tmp = pllctl_reg_read(data->pll, ctl);
  290. if (data->internal_osc) {
  291. tmp &= ~PLLCTL_CLKMODE;
  292. fpll = CONFIG_SYS_INT_OSC_FREQ;
  293. } else {
  294. tmp |= PLLCTL_CLKMODE;
  295. fpll = pll_ext_freq[data->pll];
  296. }
  297. pllctl_reg_write(data->pll, ctl, tmp);
  298. mult = data->pll_freq / fpll;
  299. for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
  300. div = (fpll * mult) / data->pll_freq;
  301. if (div < 1 || div > MAX_DIV)
  302. continue;
  303. for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
  304. prediv = div / postdiv;
  305. if (prediv < 1 || prediv > MAX_PREDIV)
  306. continue;
  307. actual = (fpll / prediv) * (mult / postdiv);
  308. delta = (actual - data->pll_freq);
  309. if (delta < 0)
  310. delta = -delta;
  311. if ((delta < best_delta) || (best_delta == -1)) {
  312. best_delta = delta;
  313. best_mult = mult;
  314. best_pre = prediv;
  315. best_post = postdiv;
  316. if (delta == 0)
  317. goto done;
  318. }
  319. }
  320. }
  321. done:
  322. if (best_delta == -1) {
  323. printf("pll cannot derive %lu from %lu\n",
  324. data->pll_freq, fpll);
  325. return;
  326. }
  327. fpll = fpll * best_mult;
  328. fpll /= best_pre * best_post;
  329. pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
  330. pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
  331. pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
  332. pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
  333. pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
  334. sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
  335. sspll_reg_write(data->pll, prediv, best_pre - 1);
  336. sspll_reg_write(data->pll, postdiv, best_post - 1);
  337. for (i = 0; i < 10; i++)
  338. if (data->div_freq[i])
  339. __pll_div_freq_set(data->pll, fpll, i,
  340. data->div_freq[i]);
  341. pllctl_reg_write(data->pll, cmd, 1);
  342. /* Wait until pll "go" operation completes */
  343. while (pllctl_reg_read(data->pll, stat) & 0x01);
  344. pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
  345. pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
  346. }
  347. void init_plls(int num_pll, struct pll_init_data *config)
  348. {
  349. int i;
  350. for (i = 0; i < num_pll; i++)
  351. init_pll(&config[i]);
  352. }