start.S 7.1 KB

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  1. /*
  2. * armboot - Startup Code for ARM1176 CPU-core
  3. *
  4. * Copyright (c) 2007 Samsung Electronics
  5. *
  6. * Copyright (C) 2008
  7. * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. *
  11. * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
  12. * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
  13. * jsgood (jsgood.yang@samsung.com)
  14. * Base codes by scsuh (sc.suh)
  15. */
  16. #include <asm-offsets.h>
  17. #include <config.h>
  18. #include <version.h>
  19. #ifndef CONFIG_SYS_PHY_UBOOT_BASE
  20. #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
  21. #endif
  22. /*
  23. *************************************************************************
  24. *
  25. * Jump vector table as in table 3.1 in [1]
  26. *
  27. *************************************************************************
  28. */
  29. .globl _start
  30. _start: b reset
  31. #ifndef CONFIG_SPL_BUILD
  32. ldr pc, _undefined_instruction
  33. ldr pc, _software_interrupt
  34. ldr pc, _prefetch_abort
  35. ldr pc, _data_abort
  36. ldr pc, _not_used
  37. ldr pc, _irq
  38. ldr pc, _fiq
  39. _undefined_instruction:
  40. .word undefined_instruction
  41. _software_interrupt:
  42. .word software_interrupt
  43. _prefetch_abort:
  44. .word prefetch_abort
  45. _data_abort:
  46. .word data_abort
  47. _not_used:
  48. .word not_used
  49. _irq:
  50. .word irq
  51. _fiq:
  52. .word fiq
  53. _pad:
  54. .word 0x12345678 /* now 16*4=64 */
  55. #else
  56. . = _start + 64
  57. #endif
  58. .global _end_vect
  59. _end_vect:
  60. .balignl 16,0xdeadbeef
  61. /*
  62. *************************************************************************
  63. *
  64. * Startup Code (reset vector)
  65. *
  66. * do important init only if we don't start from memory!
  67. * setup Memory and board specific bits prior to relocation.
  68. * relocate armboot to ram
  69. * setup stack
  70. *
  71. *************************************************************************
  72. */
  73. .globl _TEXT_BASE
  74. _TEXT_BASE:
  75. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  76. .word CONFIG_SPL_TEXT_BASE
  77. #else
  78. .word CONFIG_SYS_TEXT_BASE
  79. #endif
  80. /*
  81. * These are defined in the board-specific linker script.
  82. * Subtracting _start from them lets the linker put their
  83. * relative position in the executable instead of leaving
  84. * them null.
  85. */
  86. .globl _bss_start_ofs
  87. _bss_start_ofs:
  88. .word __bss_start - _start
  89. .globl _bss_end_ofs
  90. _bss_end_ofs:
  91. .word __bss_end - _start
  92. .globl _end_ofs
  93. _end_ofs:
  94. .word _end - _start
  95. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  96. .globl IRQ_STACK_START_IN
  97. IRQ_STACK_START_IN:
  98. .word 0x0badc0de
  99. /*
  100. * the actual reset code
  101. */
  102. reset:
  103. /*
  104. * set the cpu to SVC32 mode
  105. */
  106. mrs r0, cpsr
  107. bic r0, r0, #0x3f
  108. orr r0, r0, #0xd3
  109. msr cpsr, r0
  110. /*
  111. *************************************************************************
  112. *
  113. * CPU_init_critical registers
  114. *
  115. * setup important registers
  116. * setup memory timing
  117. *
  118. *************************************************************************
  119. */
  120. /*
  121. * we do sys-critical inits only at reboot,
  122. * not when booting from ram!
  123. */
  124. cpu_init_crit:
  125. /*
  126. * When booting from NAND - it has definitely been a reset, so, no need
  127. * to flush caches and disable the MMU
  128. */
  129. #ifndef CONFIG_SPL_BUILD
  130. /*
  131. * flush v4 I/D caches
  132. */
  133. mov r0, #0
  134. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  135. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  136. /*
  137. * disable MMU stuff and caches
  138. */
  139. mrc p15, 0, r0, c1, c0, 0
  140. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  141. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  142. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  143. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  144. /* Prepare to disable the MMU */
  145. adr r2, mmu_disable_phys
  146. sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
  147. b mmu_disable
  148. .align 5
  149. /* Run in a single cache-line */
  150. mmu_disable:
  151. mcr p15, 0, r0, c1, c0, 0
  152. nop
  153. nop
  154. mov pc, r2
  155. mmu_disable_phys:
  156. #ifdef CONFIG_DISABLE_TCM
  157. /*
  158. * Disable the TCMs
  159. */
  160. mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
  161. cmp r0, #0
  162. beq skip_tcmdisable
  163. mov r1, #0
  164. mov r2, #1
  165. tst r0, r2
  166. mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
  167. tst r0, r2, LSL #16
  168. mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
  169. skip_tcmdisable:
  170. #endif
  171. #endif
  172. #ifdef CONFIG_PERIPORT_REMAP
  173. /* Peri port setup */
  174. ldr r0, =CONFIG_PERIPORT_BASE
  175. orr r0, r0, #CONFIG_PERIPORT_SIZE
  176. mcr p15,0,r0,c15,c2,4
  177. #endif
  178. /*
  179. * Go setup Memory and board specific bits prior to relocation.
  180. */
  181. bl lowlevel_init /* go setup pll,mux,memory */
  182. bl _main
  183. /*------------------------------------------------------------------------------*/
  184. .globl c_runtime_cpu_setup
  185. c_runtime_cpu_setup:
  186. mov pc, lr
  187. #ifndef CONFIG_SPL_BUILD
  188. /*
  189. *************************************************************************
  190. *
  191. * Interrupt handling
  192. *
  193. *************************************************************************
  194. */
  195. @
  196. @ IRQ stack frame.
  197. @
  198. #define S_FRAME_SIZE 72
  199. #define S_OLD_R0 68
  200. #define S_PSR 64
  201. #define S_PC 60
  202. #define S_LR 56
  203. #define S_SP 52
  204. #define S_IP 48
  205. #define S_FP 44
  206. #define S_R10 40
  207. #define S_R9 36
  208. #define S_R8 32
  209. #define S_R7 28
  210. #define S_R6 24
  211. #define S_R5 20
  212. #define S_R4 16
  213. #define S_R3 12
  214. #define S_R2 8
  215. #define S_R1 4
  216. #define S_R0 0
  217. #define MODE_SVC 0x13
  218. #define I_BIT 0x80
  219. /*
  220. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  221. */
  222. .macro bad_save_user_regs
  223. /* carve out a frame on current user stack */
  224. sub sp, sp, #S_FRAME_SIZE
  225. /* Save user registers (now in svc mode) r0-r12 */
  226. stmia sp, {r0 - r12}
  227. ldr r2, IRQ_STACK_START_IN
  228. /* get values for "aborted" pc and cpsr (into parm regs) */
  229. ldmia r2, {r2 - r3}
  230. /* grab pointer to old stack */
  231. add r0, sp, #S_FRAME_SIZE
  232. add r5, sp, #S_SP
  233. mov r1, lr
  234. /* save sp_SVC, lr_SVC, pc, cpsr */
  235. stmia r5, {r0 - r3}
  236. /* save current stack into r0 (param register) */
  237. mov r0, sp
  238. .endm
  239. .macro get_bad_stack
  240. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  241. /* save caller lr in position 0 of saved stack */
  242. str lr, [r13]
  243. /* get the spsr */
  244. mrs lr, spsr
  245. /* save spsr in position 1 of saved stack */
  246. str lr, [r13, #4]
  247. /* prepare SVC-Mode */
  248. mov r13, #MODE_SVC
  249. @ msr spsr_c, r13
  250. /* switch modes, make sure moves will execute */
  251. msr spsr, r13
  252. /* capture return pc */
  253. mov lr, pc
  254. /* jump to next instruction & switch modes. */
  255. movs pc, lr
  256. .endm
  257. .macro get_bad_stack_swi
  258. /* space on current stack for scratch reg. */
  259. sub r13, r13, #4
  260. /* save R0's value. */
  261. str r0, [r13]
  262. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  263. /* save caller lr in position 0 of saved stack */
  264. str lr, [r0]
  265. /* get the spsr */
  266. mrs lr, spsr
  267. /* save spsr in position 1 of saved stack */
  268. str lr, [r0, #4]
  269. /* restore lr */
  270. ldr lr, [r0]
  271. /* restore r0 */
  272. ldr r0, [r13]
  273. /* pop stack entry */
  274. add r13, r13, #4
  275. .endm
  276. /*
  277. * exception handlers
  278. */
  279. .align 5
  280. undefined_instruction:
  281. get_bad_stack
  282. bad_save_user_regs
  283. bl do_undefined_instruction
  284. .align 5
  285. software_interrupt:
  286. get_bad_stack_swi
  287. bad_save_user_regs
  288. bl do_software_interrupt
  289. .align 5
  290. prefetch_abort:
  291. get_bad_stack
  292. bad_save_user_regs
  293. bl do_prefetch_abort
  294. .align 5
  295. data_abort:
  296. get_bad_stack
  297. bad_save_user_regs
  298. bl do_data_abort
  299. .align 5
  300. not_used:
  301. get_bad_stack
  302. bad_save_user_regs
  303. bl do_not_used
  304. .align 5
  305. irq:
  306. get_bad_stack
  307. bad_save_user_regs
  308. bl do_irq
  309. .align 5
  310. fiq:
  311. get_bad_stack
  312. bad_save_user_regs
  313. bl do_fiq
  314. #endif /* CONFIG_SPL_BUILD */