start.S 8.2 KB

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  1. /*
  2. * armboot - Startup Code for OMP2420/ARM1136 CPU-core
  3. *
  4. * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
  5. *
  6. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  7. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  8. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  9. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  10. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <asm-offsets.h>
  15. #include <config.h>
  16. #include <version.h>
  17. .globl _start
  18. _start: b reset
  19. #ifdef CONFIG_SPL_BUILD
  20. ldr pc, _hang
  21. ldr pc, _hang
  22. ldr pc, _hang
  23. ldr pc, _hang
  24. ldr pc, _hang
  25. ldr pc, _hang
  26. ldr pc, _hang
  27. _hang:
  28. .word do_hang
  29. .word 0x12345678
  30. .word 0x12345678
  31. .word 0x12345678
  32. .word 0x12345678
  33. .word 0x12345678
  34. .word 0x12345678
  35. .word 0x12345678 /* now 16*4=64 */
  36. #else
  37. ldr pc, _undefined_instruction
  38. ldr pc, _software_interrupt
  39. ldr pc, _prefetch_abort
  40. ldr pc, _data_abort
  41. ldr pc, _not_used
  42. ldr pc, _irq
  43. ldr pc, _fiq
  44. _undefined_instruction: .word undefined_instruction
  45. _software_interrupt: .word software_interrupt
  46. _prefetch_abort: .word prefetch_abort
  47. _data_abort: .word data_abort
  48. _not_used: .word not_used
  49. _irq: .word irq
  50. _fiq: .word fiq
  51. _pad: .word 0x12345678 /* now 16*4=64 */
  52. #endif /* CONFIG_SPL_BUILD */
  53. .global _end_vect
  54. _end_vect:
  55. .balignl 16,0xdeadbeef
  56. /*
  57. *************************************************************************
  58. *
  59. * Startup Code (reset vector)
  60. *
  61. * do important init only if we don't start from memory!
  62. * setup Memory and board specific bits prior to relocation.
  63. * relocate armboot to ram
  64. * setup stack
  65. *
  66. *************************************************************************
  67. */
  68. .globl _TEXT_BASE
  69. _TEXT_BASE:
  70. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  71. .word CONFIG_SPL_TEXT_BASE
  72. #else
  73. .word CONFIG_SYS_TEXT_BASE
  74. #endif
  75. /*
  76. * These are defined in the board-specific linker script.
  77. * Subtracting _start from them lets the linker put their
  78. * relative position in the executable instead of leaving
  79. * them null.
  80. */
  81. .globl _bss_start_ofs
  82. _bss_start_ofs:
  83. .word __bss_start - _start
  84. .globl _bss_end_ofs
  85. _bss_end_ofs:
  86. .word __bss_end - _start
  87. .globl _end_ofs
  88. _end_ofs:
  89. .word _end - _start
  90. #ifdef CONFIG_USE_IRQ
  91. /* IRQ stack memory (calculated at run-time) */
  92. .globl IRQ_STACK_START
  93. IRQ_STACK_START:
  94. .word 0x0badc0de
  95. /* IRQ stack memory (calculated at run-time) */
  96. .globl FIQ_STACK_START
  97. FIQ_STACK_START:
  98. .word 0x0badc0de
  99. #endif
  100. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  101. .globl IRQ_STACK_START_IN
  102. IRQ_STACK_START_IN:
  103. .word 0x0badc0de
  104. /*
  105. * the actual reset code
  106. */
  107. reset:
  108. /*
  109. * set the cpu to SVC32 mode
  110. */
  111. mrs r0,cpsr
  112. bic r0,r0,#0x1f
  113. orr r0,r0,#0xd3
  114. msr cpsr,r0
  115. /* the mask ROM code should have PLL and others stable */
  116. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  117. bl cpu_init_crit
  118. #endif
  119. bl _main
  120. /*------------------------------------------------------------------------------*/
  121. .globl c_runtime_cpu_setup
  122. c_runtime_cpu_setup:
  123. bx lr
  124. /*
  125. *************************************************************************
  126. *
  127. * CPU_init_critical registers
  128. *
  129. * setup important registers
  130. * setup memory timing
  131. *
  132. *************************************************************************
  133. */
  134. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  135. cpu_init_crit:
  136. /*
  137. * flush v4 I/D caches
  138. */
  139. mov r0, #0
  140. mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
  141. mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
  142. /*
  143. * disable MMU stuff and caches
  144. */
  145. mrc p15, 0, r0, c1, c0, 0
  146. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  147. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  148. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  149. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  150. mcr p15, 0, r0, c1, c0, 0
  151. /*
  152. * Jump to board specific initialization... The Mask ROM will have already initialized
  153. * basic memory. Go here to bump up clock rate and handle wake up conditions.
  154. */
  155. mov ip, lr /* persevere link reg across call */
  156. bl lowlevel_init /* go setup pll,mux,memory */
  157. mov lr, ip /* restore link */
  158. mov pc, lr /* back to my caller */
  159. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  160. #ifndef CONFIG_SPL_BUILD
  161. /*
  162. *************************************************************************
  163. *
  164. * Interrupt handling
  165. *
  166. *************************************************************************
  167. */
  168. @
  169. @ IRQ stack frame.
  170. @
  171. #define S_FRAME_SIZE 72
  172. #define S_OLD_R0 68
  173. #define S_PSR 64
  174. #define S_PC 60
  175. #define S_LR 56
  176. #define S_SP 52
  177. #define S_IP 48
  178. #define S_FP 44
  179. #define S_R10 40
  180. #define S_R9 36
  181. #define S_R8 32
  182. #define S_R7 28
  183. #define S_R6 24
  184. #define S_R5 20
  185. #define S_R4 16
  186. #define S_R3 12
  187. #define S_R2 8
  188. #define S_R1 4
  189. #define S_R0 0
  190. #define MODE_SVC 0x13
  191. #define I_BIT 0x80
  192. /*
  193. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  194. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  195. */
  196. .macro bad_save_user_regs
  197. sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
  198. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  199. ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
  200. ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
  201. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  202. add r5, sp, #S_SP
  203. mov r1, lr
  204. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  205. mov r0, sp @ save current stack into r0 (param register)
  206. .endm
  207. .macro irq_save_user_regs
  208. sub sp, sp, #S_FRAME_SIZE
  209. stmia sp, {r0 - r12} @ Calling r0-r12
  210. add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  211. stmdb r8, {sp, lr}^ @ Calling SP, LR
  212. str lr, [r8, #0] @ Save calling PC
  213. mrs r6, spsr
  214. str r6, [r8, #4] @ Save CPSR
  215. str r0, [r8, #8] @ Save OLD_R0
  216. mov r0, sp
  217. .endm
  218. .macro irq_restore_user_regs
  219. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  220. mov r0, r0
  221. ldr lr, [sp, #S_PC] @ Get PC
  222. add sp, sp, #S_FRAME_SIZE
  223. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  224. .endm
  225. .macro get_bad_stack
  226. ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
  227. str lr, [r13] @ save caller lr in position 0 of saved stack
  228. mrs lr, spsr @ get the spsr
  229. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  230. mov r13, #MODE_SVC @ prepare SVC-Mode
  231. @ msr spsr_c, r13
  232. msr spsr, r13 @ switch modes, make sure moves will execute
  233. mov lr, pc @ capture return pc
  234. movs pc, lr @ jump to next instruction & switch modes.
  235. .endm
  236. .macro get_bad_stack_swi
  237. sub r13, r13, #4 @ space on current stack for scratch reg.
  238. str r0, [r13] @ save R0's value.
  239. ldr r0, IRQ_STACK_START_IN @ get data regions start
  240. str lr, [r0] @ save caller lr in position 0 of saved stack
  241. mrs lr, spsr @ get the spsr
  242. str lr, [r0, #4] @ save spsr in position 1 of saved stack
  243. ldr lr, [r0] @ restore lr
  244. ldr r0, [r13] @ restore r0
  245. add r13, r13, #4 @ pop stack entry
  246. .endm
  247. .macro get_irq_stack @ setup IRQ stack
  248. ldr sp, IRQ_STACK_START
  249. .endm
  250. .macro get_fiq_stack @ setup FIQ stack
  251. ldr sp, FIQ_STACK_START
  252. .endm
  253. #endif /* CONFIG_SPL_BUILD */
  254. /*
  255. * exception handlers
  256. */
  257. #ifdef CONFIG_SPL_BUILD
  258. .align 5
  259. do_hang:
  260. ldr sp, _TEXT_BASE /* use 32 words about stack */
  261. bl hang /* hang and never return */
  262. #else /* !CONFIG_SPL_BUILD */
  263. .align 5
  264. undefined_instruction:
  265. get_bad_stack
  266. bad_save_user_regs
  267. bl do_undefined_instruction
  268. .align 5
  269. software_interrupt:
  270. get_bad_stack_swi
  271. bad_save_user_regs
  272. bl do_software_interrupt
  273. .align 5
  274. prefetch_abort:
  275. get_bad_stack
  276. bad_save_user_regs
  277. bl do_prefetch_abort
  278. .align 5
  279. data_abort:
  280. get_bad_stack
  281. bad_save_user_regs
  282. bl do_data_abort
  283. .align 5
  284. not_used:
  285. get_bad_stack
  286. bad_save_user_regs
  287. bl do_not_used
  288. #ifdef CONFIG_USE_IRQ
  289. .align 5
  290. irq:
  291. get_irq_stack
  292. irq_save_user_regs
  293. bl do_irq
  294. irq_restore_user_regs
  295. .align 5
  296. fiq:
  297. get_fiq_stack
  298. /* someone ought to write a more effiction fiq_save_user_regs */
  299. irq_save_user_regs
  300. bl do_fiq
  301. irq_restore_user_regs
  302. #else
  303. .align 5
  304. irq:
  305. get_bad_stack
  306. bad_save_user_regs
  307. bl do_irq
  308. .align 5
  309. fiq:
  310. get_bad_stack
  311. bad_save_user_regs
  312. bl do_fiq
  313. #endif
  314. .align 5
  315. .global arm1136_cache_flush
  316. arm1136_cache_flush:
  317. #if !defined(CONFIG_SYS_ICACHE_OFF)
  318. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  319. #endif
  320. #if !defined(CONFIG_SYS_DCACHE_OFF)
  321. mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
  322. #endif
  323. mov pc, lr @ back to caller
  324. #endif /* CONFIG_SPL_BUILD */