mx35_sdram.c 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121
  1. /*
  2. * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <asm/io.h>
  7. #include <asm/errno.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <linux/types.h>
  10. #include <asm/arch/sys_proto.h>
  11. #define ESDCTL_DDR2_EMR2 0x04000000
  12. #define ESDCTL_DDR2_EMR3 0x06000000
  13. #define ESDCTL_PRECHARGE 0x00000400
  14. #define ESDCTL_DDR2_EN_DLL 0x02000400
  15. #define ESDCTL_DDR2_RESET_DLL 0x00000333
  16. #define ESDCTL_DDR2_MR 0x00000233
  17. #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
  18. enum {
  19. SMODE_NORMAL = 0,
  20. SMODE_PRECHARGE,
  21. SMODE_AUTO_REFRESH,
  22. SMODE_LOAD_REG,
  23. SMODE_MANUAL_REFRESH
  24. };
  25. #define set_mode(x, en, m) (x | (en << 31) | (m << 28))
  26. static inline void dram_wait(unsigned int count)
  27. {
  28. volatile unsigned int wait = count;
  29. while (wait--)
  30. ;
  31. }
  32. void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
  33. u32 row, u32 col, u32 dsize, u32 refresh)
  34. {
  35. struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  36. u32 *cfg_reg, *ctl_reg;
  37. u32 val;
  38. u32 ctlval;
  39. switch (start_address) {
  40. case CSD0_BASE_ADDR:
  41. cfg_reg = &esdc->esdcfg0;
  42. ctl_reg = &esdc->esdctl0;
  43. break;
  44. case CSD1_BASE_ADDR:
  45. cfg_reg = &esdc->esdcfg1;
  46. ctl_reg = &esdc->esdctl1;
  47. break;
  48. default:
  49. return;
  50. }
  51. /* The MX35 supports 11 up to 14 rows */
  52. if (row < 11 || row > 14 || col < 8 || col > 10)
  53. return;
  54. ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
  55. /* Initialize MISC register for DDR2 */
  56. val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
  57. ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
  58. writel(val, &esdc->esdmisc);
  59. val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
  60. writel(val, &esdc->esdmisc);
  61. /*
  62. * according to DDR2 specs, wait a while before
  63. * the PRECHARGE_ALL command
  64. */
  65. dram_wait(0x20000);
  66. /* Load DDR2 config and timing */
  67. writel(ddr2_config, cfg_reg);
  68. /* Precharge ALL */
  69. writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
  70. ctl_reg);
  71. writel(0xda, start_address + ESDCTL_PRECHARGE);
  72. /* Load mode */
  73. writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
  74. ctl_reg);
  75. writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
  76. writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
  77. writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
  78. writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
  79. /* Precharge ALL */
  80. writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
  81. ctl_reg);
  82. writel(0xda, start_address + ESDCTL_PRECHARGE);
  83. /* Set mode auto refresh : at least two refresh are required */
  84. writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
  85. ctl_reg);
  86. writel(0xda, start_address);
  87. writel(0xda, start_address);
  88. writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
  89. ctl_reg);
  90. writeb(0xda, start_address + ESDCTL_DDR2_MR);
  91. writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
  92. /* OCD mode exit */
  93. writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
  94. /* Set normal mode */
  95. writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
  96. ctl_reg);
  97. dram_wait(0x20000);
  98. /* Do not set delay lines, only for MDDR */
  99. }