cpu.c 3.1 KB

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  1. /*
  2. * (C) Copyright 2004 Texas Insturments
  3. *
  4. * (C) Copyright 2002
  5. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  6. * Marius Groeger <mgroeger@sysgo.de>
  7. *
  8. * (C) Copyright 2002
  9. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. /*
  14. * CPU specific code
  15. */
  16. #include <common.h>
  17. #include <command.h>
  18. #include <asm/system.h>
  19. static void cache_flush(void);
  20. int cleanup_before_linux (void)
  21. {
  22. /*
  23. * this function is called just before we call linux
  24. * it prepares the processor for linux
  25. *
  26. * we turn off caches etc ...
  27. */
  28. disable_interrupts ();
  29. #ifdef CONFIG_LCD
  30. {
  31. extern void lcd_disable(void);
  32. extern void lcd_panel_disable(void);
  33. lcd_disable(); /* proper disable of lcd & panel */
  34. lcd_panel_disable();
  35. }
  36. #endif
  37. /* turn off I/D-cache */
  38. icache_disable();
  39. dcache_disable();
  40. /* flush I/D-cache */
  41. cache_flush();
  42. return 0;
  43. }
  44. static void cache_flush(void)
  45. {
  46. unsigned long i = 0;
  47. /* clean entire data cache */
  48. asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
  49. /* invalidate both caches and flush btb */
  50. asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
  51. /* mem barrier to sync things */
  52. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
  53. }
  54. #ifndef CONFIG_SYS_DCACHE_OFF
  55. #ifndef CONFIG_SYS_CACHELINE_SIZE
  56. #define CONFIG_SYS_CACHELINE_SIZE 32
  57. #endif
  58. void invalidate_dcache_all(void)
  59. {
  60. asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
  61. }
  62. void flush_dcache_all(void)
  63. {
  64. asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
  65. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  66. }
  67. static int check_cache_range(unsigned long start, unsigned long stop)
  68. {
  69. int ok = 1;
  70. if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
  71. ok = 0;
  72. if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
  73. ok = 0;
  74. if (!ok)
  75. debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
  76. start, stop);
  77. return ok;
  78. }
  79. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  80. {
  81. if (!check_cache_range(start, stop))
  82. return;
  83. while (start < stop) {
  84. asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
  85. start += CONFIG_SYS_CACHELINE_SIZE;
  86. }
  87. }
  88. void flush_dcache_range(unsigned long start, unsigned long stop)
  89. {
  90. if (!check_cache_range(start, stop))
  91. return;
  92. while (start < stop) {
  93. asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
  94. start += CONFIG_SYS_CACHELINE_SIZE;
  95. }
  96. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  97. }
  98. void flush_cache(unsigned long start, unsigned long size)
  99. {
  100. flush_dcache_range(start, start + size);
  101. }
  102. #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
  103. void invalidate_dcache_all(void)
  104. {
  105. }
  106. void flush_dcache_all(void)
  107. {
  108. }
  109. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  110. {
  111. }
  112. void flush_dcache_range(unsigned long start, unsigned long stop)
  113. {
  114. }
  115. void flush_cache(unsigned long start, unsigned long size)
  116. {
  117. }
  118. #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  119. #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
  120. void enable_caches(void)
  121. {
  122. #ifndef CONFIG_SYS_ICACHE_OFF
  123. icache_enable();
  124. #endif
  125. #ifndef CONFIG_SYS_DCACHE_OFF
  126. dcache_enable();
  127. #endif
  128. }
  129. #endif