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- /*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /*
- * CPU specific code
- */
- #include <common.h>
- #include <command.h>
- #include <asm/system.h>
- static void cache_flush(void);
- int cleanup_before_linux (void)
- {
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- */
- disable_interrupts ();
- #ifdef CONFIG_LCD
- {
- extern void lcd_disable(void);
- extern void lcd_panel_disable(void);
- lcd_disable(); /* proper disable of lcd & panel */
- lcd_panel_disable();
- }
- #endif
- /* turn off I/D-cache */
- icache_disable();
- dcache_disable();
- /* flush I/D-cache */
- cache_flush();
- return 0;
- }
- static void cache_flush(void)
- {
- unsigned long i = 0;
- /* clean entire data cache */
- asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
- /* invalidate both caches and flush btb */
- asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
- /* mem barrier to sync things */
- asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
- }
- #ifndef CONFIG_SYS_DCACHE_OFF
- #ifndef CONFIG_SYS_CACHELINE_SIZE
- #define CONFIG_SYS_CACHELINE_SIZE 32
- #endif
- void invalidate_dcache_all(void)
- {
- asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
- }
- void flush_dcache_all(void)
- {
- asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
- asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
- }
- static int check_cache_range(unsigned long start, unsigned long stop)
- {
- int ok = 1;
- if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
- ok = 0;
- if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
- ok = 0;
- if (!ok)
- debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
- start, stop);
- return ok;
- }
- void invalidate_dcache_range(unsigned long start, unsigned long stop)
- {
- if (!check_cache_range(start, stop))
- return;
- while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
- start += CONFIG_SYS_CACHELINE_SIZE;
- }
- }
- void flush_dcache_range(unsigned long start, unsigned long stop)
- {
- if (!check_cache_range(start, stop))
- return;
- while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
- start += CONFIG_SYS_CACHELINE_SIZE;
- }
- asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
- }
- void flush_cache(unsigned long start, unsigned long size)
- {
- flush_dcache_range(start, start + size);
- }
- #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
- void invalidate_dcache_all(void)
- {
- }
- void flush_dcache_all(void)
- {
- }
- void invalidate_dcache_range(unsigned long start, unsigned long stop)
- {
- }
- void flush_dcache_range(unsigned long start, unsigned long stop)
- {
- }
- void flush_cache(unsigned long start, unsigned long size)
- {
- }
- #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
- #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
- void enable_caches(void)
- {
- #ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
- #endif
- #ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
- #endif
- }
- #endif
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