mpc83xx_cpu.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <bitfield.h>
  8. #include <clk.h>
  9. #include <cpu.h>
  10. #include <dm.h>
  11. #include "mpc83xx_cpu.h"
  12. /**
  13. * struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs
  14. * @e300_type: The e300 core type of the MPC83xx CPU
  15. * @family: The MPC83xx family the CPU belongs to
  16. * @type: The MPC83xx type of the CPU
  17. * @is_e_processor: Flag indicating whether the CPU is a E processor or not
  18. * @is_a_variant: Flag indicating whtther the CPU is a A variant or not
  19. * @revid: The revision ID of the CPU
  20. * @revid.major: The major part of the CPU's revision ID
  21. * @revid.minor: The minor part of the CPU's revision ID
  22. */
  23. struct mpc83xx_cpu_priv {
  24. enum e300_type e300_type;
  25. enum mpc83xx_cpu_family family;
  26. enum mpc83xx_cpu_type type;
  27. bool is_e_processor;
  28. bool is_a_variant;
  29. struct {
  30. uint major;
  31. uint minor;
  32. } revid;
  33. };
  34. int checkcpu(void)
  35. {
  36. /* Activate all CPUs from board_f.c */
  37. return cpu_probe_all();
  38. }
  39. /**
  40. * get_spridr() - Read SPRIDR (System Part and Revision ID Register) of CPU
  41. *
  42. * Return: The SPRIDR value
  43. */
  44. static inline u32 get_spridr(void)
  45. {
  46. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  47. return in_be32(&immr->sysconf.spridr);
  48. }
  49. /**
  50. * determine_type() - Determine CPU family of MPC83xx device
  51. * @dev: CPU device from which to read CPU family from
  52. */
  53. static inline void determine_family(struct udevice *dev)
  54. {
  55. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  56. /* Upper 12 bits of PARTID field (bits 0-23 in SPRIDR) */
  57. const u32 PARTID_FAMILY_MASK = 0xFFF00000;
  58. switch (bitfield_extract_by_mask(get_spridr(), PARTID_FAMILY_MASK)) {
  59. case 0x810:
  60. case 0x811:
  61. priv->family = FAMILY_830X;
  62. break;
  63. case 0x80B:
  64. priv->family = FAMILY_831X;
  65. break;
  66. case 0x806:
  67. priv->family = FAMILY_832X;
  68. break;
  69. case 0x803:
  70. priv->family = FAMILY_834X;
  71. break;
  72. case 0x804:
  73. priv->family = FAMILY_836X;
  74. break;
  75. case 0x80C:
  76. priv->family = FAMILY_837X;
  77. break;
  78. default:
  79. priv->family = FAMILY_UNKNOWN;
  80. }
  81. }
  82. /**
  83. * determine_type() - Determine CPU type of MPC83xx device
  84. * @dev: CPU device from which to read CPU type from
  85. */
  86. static inline void determine_type(struct udevice *dev)
  87. {
  88. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  89. /* Upper 16 bits of PVR (Processor Version Register) */
  90. const u32 PCR_UPPER_MASK = 0xFFFF0000;
  91. u32 val;
  92. val = bitfield_extract_by_mask(get_spridr(), PCR_UPPER_MASK);
  93. /* Mask out E-variant bit */
  94. switch (val & 0xFFFE) {
  95. case 0x8100:
  96. priv->type = TYPE_8308;
  97. break;
  98. case 0x8110:
  99. priv->type = TYPE_8309;
  100. break;
  101. case 0x80B2:
  102. priv->type = TYPE_8311;
  103. break;
  104. case 0x80B0:
  105. priv->type = TYPE_8313;
  106. break;
  107. case 0x80B6:
  108. priv->type = TYPE_8314;
  109. break;
  110. case 0x80B4:
  111. priv->type = TYPE_8315;
  112. break;
  113. case 0x8066:
  114. priv->type = TYPE_8321;
  115. break;
  116. case 0x8062:
  117. priv->type = TYPE_8323;
  118. break;
  119. case 0x8036:
  120. priv->type = TYPE_8343;
  121. break;
  122. case 0x8032:
  123. priv->type = TYPE_8347_TBGA;
  124. break;
  125. case 0x8034:
  126. priv->type = TYPE_8347_PBGA;
  127. break;
  128. case 0x8030:
  129. priv->type = TYPE_8349;
  130. break;
  131. case 0x804A:
  132. priv->type = TYPE_8358_TBGA;
  133. break;
  134. case 0x804E:
  135. priv->type = TYPE_8358_PBGA;
  136. break;
  137. case 0x8048:
  138. priv->type = TYPE_8360;
  139. break;
  140. case 0x80C6:
  141. priv->type = TYPE_8377;
  142. break;
  143. case 0x80C4:
  144. priv->type = TYPE_8378;
  145. break;
  146. case 0x80C2:
  147. priv->type = TYPE_8379;
  148. break;
  149. default:
  150. priv->type = TYPE_UNKNOWN;
  151. }
  152. }
  153. /**
  154. * determine_e300_type() - Determine e300 core type of MPC83xx device
  155. * @dev: CPU device from which to read e300 core type from
  156. */
  157. static inline void determine_e300_type(struct udevice *dev)
  158. {
  159. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  160. /* Upper 16 bits of PVR (Processor Version Register) */
  161. const u32 PCR_UPPER_MASK = 0xFFFF0000;
  162. u32 pvr = get_pvr();
  163. switch ((pvr & PCR_UPPER_MASK) >> 16) {
  164. case 0x8083:
  165. priv->e300_type = E300C1;
  166. break;
  167. case 0x8084:
  168. priv->e300_type = E300C2;
  169. break;
  170. case 0x8085:
  171. priv->e300_type = E300C3;
  172. break;
  173. case 0x8086:
  174. priv->e300_type = E300C4;
  175. break;
  176. default:
  177. priv->e300_type = E300_UNKNOWN;
  178. }
  179. }
  180. /**
  181. * determine_revid() - Determine revision ID of CPU device
  182. * @dev: CPU device from which to read revision ID
  183. */
  184. static inline void determine_revid(struct udevice *dev)
  185. {
  186. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  187. u32 REVID_MAJOR_MASK;
  188. u32 REVID_MINOR_MASK;
  189. u32 spridr = get_spridr();
  190. if (priv->family == FAMILY_834X) {
  191. REVID_MAJOR_MASK = 0x0000FF00;
  192. REVID_MINOR_MASK = 0x000000FF;
  193. } else {
  194. REVID_MAJOR_MASK = 0x000000F0;
  195. REVID_MINOR_MASK = 0x0000000F;
  196. }
  197. priv->revid.major = bitfield_extract_by_mask(spridr, REVID_MAJOR_MASK);
  198. priv->revid.minor = bitfield_extract_by_mask(spridr, REVID_MINOR_MASK);
  199. }
  200. /**
  201. * determine_cpu_data() - Determine CPU information from hardware
  202. * @dev: CPU device from which to read information
  203. */
  204. static void determine_cpu_data(struct udevice *dev)
  205. {
  206. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  207. const u32 E_FLAG_MASK = 0x00010000;
  208. u32 spridr = get_spridr();
  209. determine_family(dev);
  210. determine_type(dev);
  211. determine_e300_type(dev);
  212. determine_revid(dev);
  213. if ((priv->family == FAMILY_834X ||
  214. priv->family == FAMILY_836X) && priv->revid.major >= 2)
  215. priv->is_a_variant = true;
  216. priv->is_e_processor = !bitfield_extract_by_mask(spridr, E_FLAG_MASK);
  217. }
  218. static int mpc83xx_cpu_get_desc(struct udevice *dev, char *buf, int size)
  219. {
  220. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  221. struct clk core_clk;
  222. struct clk csb_clk;
  223. char core_freq[32];
  224. char csb_freq[32];
  225. int ret;
  226. ret = clk_get_by_index(dev, 0, &core_clk);
  227. if (ret) {
  228. debug("%s: Failed to get core clock (err = %d)\n",
  229. dev->name, ret);
  230. return ret;
  231. }
  232. ret = clk_get_by_index(dev, 1, &csb_clk);
  233. if (ret) {
  234. debug("%s: Failed to get CSB clock (err = %d)\n",
  235. dev->name, ret);
  236. return ret;
  237. }
  238. determine_cpu_data(dev);
  239. snprintf(buf, size,
  240. "CPU: %s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz\n",
  241. e300_names[priv->e300_type],
  242. cpu_type_names[priv->type],
  243. priv->is_e_processor ? "E" : "",
  244. priv->is_a_variant ? "A" : "",
  245. priv->revid.major,
  246. priv->revid.minor,
  247. strmhz(core_freq, clk_get_rate(&core_clk)),
  248. strmhz(csb_freq, clk_get_rate(&csb_clk)));
  249. return 0;
  250. }
  251. static int mpc83xx_cpu_get_info(struct udevice *dev, struct cpu_info *info)
  252. {
  253. struct clk clock;
  254. int ret;
  255. ulong freq;
  256. ret = clk_get_by_index(dev, 0, &clock);
  257. if (ret) {
  258. debug("%s: Failed to get core clock (err = %d)\n",
  259. dev->name, ret);
  260. return ret;
  261. }
  262. freq = clk_get_rate(&clock);
  263. if (!freq) {
  264. debug("%s: Core clock speed is zero\n", dev->name);
  265. return -EINVAL;
  266. }
  267. info->cpu_freq = freq;
  268. info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
  269. return 0;
  270. }
  271. static int mpc83xx_cpu_get_count(struct udevice *dev)
  272. {
  273. /* We have one e300cX core */
  274. return 1;
  275. }
  276. static int mpc83xx_cpu_get_vendor(struct udevice *dev, char *buf, int size)
  277. {
  278. snprintf(buf, size, "NXP");
  279. return 0;
  280. }
  281. static const struct cpu_ops mpc83xx_cpu_ops = {
  282. .get_desc = mpc83xx_cpu_get_desc,
  283. .get_info = mpc83xx_cpu_get_info,
  284. .get_count = mpc83xx_cpu_get_count,
  285. .get_vendor = mpc83xx_cpu_get_vendor,
  286. };
  287. static int mpc83xx_cpu_probe(struct udevice *dev)
  288. {
  289. return 0;
  290. }
  291. static const struct udevice_id mpc83xx_cpu_ids[] = {
  292. { .compatible = "fsl,mpc83xx", },
  293. { .compatible = "fsl,mpc8308", },
  294. { .compatible = "fsl,mpc8309", },
  295. { .compatible = "fsl,mpc8313", },
  296. { .compatible = "fsl,mpc8315", },
  297. { .compatible = "fsl,mpc832x", },
  298. { .compatible = "fsl,mpc8349", },
  299. { .compatible = "fsl,mpc8360", },
  300. { .compatible = "fsl,mpc8379", },
  301. { /* sentinel */ }
  302. };
  303. U_BOOT_DRIVER(mpc83xx_cpu) = {
  304. .name = "mpc83xx_cpu",
  305. .id = UCLASS_CPU,
  306. .of_match = mpc83xx_cpu_ids,
  307. .probe = mpc83xx_cpu_probe,
  308. .priv_auto_alloc_size = sizeof(struct mpc83xx_cpu_priv),
  309. .ops = &mpc83xx_cpu_ops,
  310. .flags = DM_FLAG_PRE_RELOC,
  311. };