cpu.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * CPU specific code for the MPC83xx family.
  7. *
  8. * Derived from the MPC8260 and MPC85xx.
  9. */
  10. #include <common.h>
  11. #include <watchdog.h>
  12. #include <command.h>
  13. #include <mpc83xx.h>
  14. #include <asm/processor.h>
  15. #include <linux/libfdt.h>
  16. #include <tsec.h>
  17. #include <netdev.h>
  18. #include <fsl_esdhc.h>
  19. #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
  20. #include <linux/immap_qe.h>
  21. #include <asm/io.h>
  22. #endif
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #ifndef CONFIG_CPU_MPC83XX
  25. int checkcpu(void)
  26. {
  27. volatile immap_t *immr;
  28. ulong clock = gd->cpu_clk;
  29. u32 pvr = get_pvr();
  30. u32 spridr;
  31. char buf[32];
  32. int ret;
  33. int i;
  34. const struct cpu_type {
  35. char name[15];
  36. u32 partid;
  37. } cpu_type_list [] = {
  38. CPU_TYPE_ENTRY(8308),
  39. CPU_TYPE_ENTRY(8309),
  40. CPU_TYPE_ENTRY(8311),
  41. CPU_TYPE_ENTRY(8313),
  42. CPU_TYPE_ENTRY(8314),
  43. CPU_TYPE_ENTRY(8315),
  44. CPU_TYPE_ENTRY(8321),
  45. CPU_TYPE_ENTRY(8323),
  46. CPU_TYPE_ENTRY(8343),
  47. CPU_TYPE_ENTRY(8347_TBGA_),
  48. CPU_TYPE_ENTRY(8347_PBGA_),
  49. CPU_TYPE_ENTRY(8349),
  50. CPU_TYPE_ENTRY(8358_TBGA_),
  51. CPU_TYPE_ENTRY(8358_PBGA_),
  52. CPU_TYPE_ENTRY(8360),
  53. CPU_TYPE_ENTRY(8377),
  54. CPU_TYPE_ENTRY(8378),
  55. CPU_TYPE_ENTRY(8379),
  56. };
  57. immr = (immap_t *)CONFIG_SYS_IMMR;
  58. ret = prt_83xx_rsr();
  59. if (ret)
  60. return ret;
  61. puts("CPU: ");
  62. switch (pvr & 0xffff0000) {
  63. case PVR_E300C1:
  64. printf("e300c1, ");
  65. break;
  66. case PVR_E300C2:
  67. printf("e300c2, ");
  68. break;
  69. case PVR_E300C3:
  70. printf("e300c3, ");
  71. break;
  72. case PVR_E300C4:
  73. printf("e300c4, ");
  74. break;
  75. default:
  76. printf("Unknown core, ");
  77. }
  78. spridr = immr->sysconf.spridr;
  79. for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  80. if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
  81. puts("MPC");
  82. puts(cpu_type_list[i].name);
  83. if (IS_E_PROCESSOR(spridr))
  84. puts("E");
  85. if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
  86. SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
  87. REVID_MAJOR(spridr) >= 2)
  88. puts("A");
  89. printf(", Rev: %d.%d", REVID_MAJOR(spridr),
  90. REVID_MINOR(spridr));
  91. break;
  92. }
  93. if (i == ARRAY_SIZE(cpu_type_list))
  94. printf("(SPRIDR %08x unknown), ", spridr);
  95. printf(" at %s MHz, ", strmhz(buf, clock));
  96. printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
  97. return 0;
  98. }
  99. #endif
  100. #ifndef CONFIG_SYSRESET
  101. int
  102. do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  103. {
  104. ulong msr;
  105. #ifndef MPC83xx_RESET
  106. ulong addr;
  107. #endif
  108. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  109. puts("Resetting the board.\n");
  110. #ifdef MPC83xx_RESET
  111. /* Interrupts and MMU off */
  112. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  113. msr &= ~( MSR_EE | MSR_IR | MSR_DR);
  114. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  115. /* enable Reset Control Reg */
  116. immap->reset.rpr = 0x52535445;
  117. __asm__ __volatile__ ("sync");
  118. __asm__ __volatile__ ("isync");
  119. /* confirm Reset Control Reg is enabled */
  120. while(!((immap->reset.rcer) & RCER_CRE));
  121. udelay(200);
  122. /* perform reset, only one bit */
  123. immap->reset.rcr = RCR_SWHR;
  124. #else /* ! MPC83xx_RESET */
  125. immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
  126. /* Interrupts and MMU off */
  127. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  128. msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
  129. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  130. /*
  131. * Trying to execute the next instruction at a non-existing address
  132. * should cause a machine check, resulting in reset
  133. */
  134. addr = CONFIG_SYS_RESET_ADDRESS;
  135. ((void (*)(void)) addr) ();
  136. #endif /* MPC83xx_RESET */
  137. return 1;
  138. }
  139. #endif
  140. /*
  141. * Get timebase clock frequency (like cpu_clk in Hz)
  142. */
  143. #ifndef CONFIG_TIMER
  144. unsigned long get_tbclk(void)
  145. {
  146. return (gd->bus_clk + 3L) / 4L;
  147. }
  148. #endif
  149. #if defined(CONFIG_WATCHDOG)
  150. void watchdog_reset (void)
  151. {
  152. int re_enable = disable_interrupts();
  153. /* Reset the 83xx watchdog */
  154. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  155. immr->wdt.swsrr = 0x556c;
  156. immr->wdt.swsrr = 0xaa39;
  157. if (re_enable)
  158. enable_interrupts ();
  159. }
  160. #endif
  161. /*
  162. * Initializes on-chip ethernet controllers.
  163. * to override, implement board_eth_init()
  164. */
  165. int cpu_eth_init(bd_t *bis)
  166. {
  167. #if defined(CONFIG_UEC_ETH)
  168. uec_standard_init(bis);
  169. #endif
  170. #if defined(CONFIG_TSEC_ENET)
  171. tsec_standard_init(bis);
  172. #endif
  173. return 0;
  174. }
  175. /*
  176. * Initializes on-chip MMC controllers.
  177. * to override, implement board_mmc_init()
  178. */
  179. int cpu_mmc_init(bd_t *bis)
  180. {
  181. #ifdef CONFIG_FSL_ESDHC
  182. return fsl_esdhc_mmc_init(bis);
  183. #else
  184. return 0;
  185. #endif
  186. }