pci-uclass.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. #include <dm/device-internal.h>
  12. #include <dm/lists.h>
  13. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  14. #include <asm/fsp/fsp_support.h>
  15. #endif
  16. #include "pci_internal.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int pci_get_bus(int busnum, struct udevice **busp)
  19. {
  20. int ret;
  21. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  22. /* Since buses may not be numbered yet try a little harder with bus 0 */
  23. if (ret == -ENODEV) {
  24. ret = uclass_first_device_err(UCLASS_PCI, busp);
  25. if (ret)
  26. return ret;
  27. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  28. }
  29. return ret;
  30. }
  31. struct udevice *pci_get_controller(struct udevice *dev)
  32. {
  33. while (device_is_on_pci_bus(dev))
  34. dev = dev->parent;
  35. return dev;
  36. }
  37. pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
  38. {
  39. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  40. struct udevice *bus = dev->parent;
  41. /*
  42. * This error indicates that @dev is a device on an unprobed PCI bus.
  43. * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
  44. * will produce a bad BDF>
  45. *
  46. * A common cause of this problem is that this function is called in the
  47. * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
  48. * method is not allowed, since it has not yet been probed. To fix this,
  49. * move that access to the probe() method of @dev instead.
  50. */
  51. if (!device_active(bus))
  52. log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
  53. bus->name);
  54. return PCI_ADD_BUS(bus->seq, pplat->devfn);
  55. }
  56. /**
  57. * pci_get_bus_max() - returns the bus number of the last active bus
  58. *
  59. * @return last bus number, or -1 if no active buses
  60. */
  61. static int pci_get_bus_max(void)
  62. {
  63. struct udevice *bus;
  64. struct uclass *uc;
  65. int ret = -1;
  66. ret = uclass_get(UCLASS_PCI, &uc);
  67. uclass_foreach_dev(bus, uc) {
  68. if (bus->seq > ret)
  69. ret = bus->seq;
  70. }
  71. debug("%s: ret=%d\n", __func__, ret);
  72. return ret;
  73. }
  74. int pci_last_busno(void)
  75. {
  76. return pci_get_bus_max();
  77. }
  78. int pci_get_ff(enum pci_size_t size)
  79. {
  80. switch (size) {
  81. case PCI_SIZE_8:
  82. return 0xff;
  83. case PCI_SIZE_16:
  84. return 0xffff;
  85. default:
  86. return 0xffffffff;
  87. }
  88. }
  89. static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
  90. ofnode *rnode)
  91. {
  92. struct fdt_pci_addr addr;
  93. ofnode node;
  94. int ret;
  95. dev_for_each_subnode(node, bus) {
  96. ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
  97. &addr);
  98. if (ret)
  99. continue;
  100. if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
  101. continue;
  102. *rnode = node;
  103. break;
  104. }
  105. };
  106. int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
  107. struct udevice **devp)
  108. {
  109. struct udevice *dev;
  110. for (device_find_first_child(bus, &dev);
  111. dev;
  112. device_find_next_child(&dev)) {
  113. struct pci_child_platdata *pplat;
  114. pplat = dev_get_parent_platdata(dev);
  115. if (pplat && pplat->devfn == find_devfn) {
  116. *devp = dev;
  117. return 0;
  118. }
  119. }
  120. return -ENODEV;
  121. }
  122. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  123. {
  124. struct udevice *bus;
  125. int ret;
  126. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  127. if (ret)
  128. return ret;
  129. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  130. }
  131. static int pci_device_matches_ids(struct udevice *dev,
  132. struct pci_device_id *ids)
  133. {
  134. struct pci_child_platdata *pplat;
  135. int i;
  136. pplat = dev_get_parent_platdata(dev);
  137. if (!pplat)
  138. return -EINVAL;
  139. for (i = 0; ids[i].vendor != 0; i++) {
  140. if (pplat->vendor == ids[i].vendor &&
  141. pplat->device == ids[i].device)
  142. return i;
  143. }
  144. return -EINVAL;
  145. }
  146. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  147. int *indexp, struct udevice **devp)
  148. {
  149. struct udevice *dev;
  150. /* Scan all devices on this bus */
  151. for (device_find_first_child(bus, &dev);
  152. dev;
  153. device_find_next_child(&dev)) {
  154. if (pci_device_matches_ids(dev, ids) >= 0) {
  155. if ((*indexp)-- <= 0) {
  156. *devp = dev;
  157. return 0;
  158. }
  159. }
  160. }
  161. return -ENODEV;
  162. }
  163. int pci_find_device_id(struct pci_device_id *ids, int index,
  164. struct udevice **devp)
  165. {
  166. struct udevice *bus;
  167. /* Scan all known buses */
  168. for (uclass_first_device(UCLASS_PCI, &bus);
  169. bus;
  170. uclass_next_device(&bus)) {
  171. if (!pci_bus_find_devices(bus, ids, &index, devp))
  172. return 0;
  173. }
  174. *devp = NULL;
  175. return -ENODEV;
  176. }
  177. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  178. unsigned int device, int *indexp,
  179. struct udevice **devp)
  180. {
  181. struct pci_child_platdata *pplat;
  182. struct udevice *dev;
  183. for (device_find_first_child(bus, &dev);
  184. dev;
  185. device_find_next_child(&dev)) {
  186. pplat = dev_get_parent_platdata(dev);
  187. if (pplat->vendor == vendor && pplat->device == device) {
  188. if (!(*indexp)--) {
  189. *devp = dev;
  190. return 0;
  191. }
  192. }
  193. }
  194. return -ENODEV;
  195. }
  196. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  197. struct udevice **devp)
  198. {
  199. struct udevice *bus;
  200. /* Scan all known buses */
  201. for (uclass_first_device(UCLASS_PCI, &bus);
  202. bus;
  203. uclass_next_device(&bus)) {
  204. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  205. return device_probe(*devp);
  206. }
  207. *devp = NULL;
  208. return -ENODEV;
  209. }
  210. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  211. {
  212. struct udevice *dev;
  213. /* Scan all known buses */
  214. for (pci_find_first_device(&dev);
  215. dev;
  216. pci_find_next_device(&dev)) {
  217. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  218. if (pplat->class == find_class && !index--) {
  219. *devp = dev;
  220. return device_probe(*devp);
  221. }
  222. }
  223. *devp = NULL;
  224. return -ENODEV;
  225. }
  226. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  227. unsigned long value, enum pci_size_t size)
  228. {
  229. struct dm_pci_ops *ops;
  230. ops = pci_get_ops(bus);
  231. if (!ops->write_config)
  232. return -ENOSYS;
  233. return ops->write_config(bus, bdf, offset, value, size);
  234. }
  235. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  236. u32 clr, u32 set)
  237. {
  238. ulong val;
  239. int ret;
  240. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  241. if (ret)
  242. return ret;
  243. val &= ~clr;
  244. val |= set;
  245. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  246. }
  247. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  248. enum pci_size_t size)
  249. {
  250. struct udevice *bus;
  251. int ret;
  252. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  253. if (ret)
  254. return ret;
  255. return pci_bus_write_config(bus, bdf, offset, value, size);
  256. }
  257. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  258. enum pci_size_t size)
  259. {
  260. struct udevice *bus;
  261. for (bus = dev; device_is_on_pci_bus(bus);)
  262. bus = bus->parent;
  263. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  264. size);
  265. }
  266. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  267. {
  268. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  269. }
  270. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  271. {
  272. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  273. }
  274. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  275. {
  276. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  277. }
  278. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  279. {
  280. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  281. }
  282. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  283. {
  284. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  285. }
  286. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  287. {
  288. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  289. }
  290. int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
  291. unsigned long *valuep, enum pci_size_t size)
  292. {
  293. struct dm_pci_ops *ops;
  294. ops = pci_get_ops(bus);
  295. if (!ops->read_config)
  296. return -ENOSYS;
  297. return ops->read_config(bus, bdf, offset, valuep, size);
  298. }
  299. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  300. enum pci_size_t size)
  301. {
  302. struct udevice *bus;
  303. int ret;
  304. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  305. if (ret)
  306. return ret;
  307. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  308. }
  309. int dm_pci_read_config(const struct udevice *dev, int offset,
  310. unsigned long *valuep, enum pci_size_t size)
  311. {
  312. const struct udevice *bus;
  313. for (bus = dev; device_is_on_pci_bus(bus);)
  314. bus = bus->parent;
  315. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  316. size);
  317. }
  318. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  319. {
  320. unsigned long value;
  321. int ret;
  322. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  323. if (ret)
  324. return ret;
  325. *valuep = value;
  326. return 0;
  327. }
  328. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  329. {
  330. unsigned long value;
  331. int ret;
  332. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  333. if (ret)
  334. return ret;
  335. *valuep = value;
  336. return 0;
  337. }
  338. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  339. {
  340. unsigned long value;
  341. int ret;
  342. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  343. if (ret)
  344. return ret;
  345. *valuep = value;
  346. return 0;
  347. }
  348. int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
  349. {
  350. unsigned long value;
  351. int ret;
  352. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  353. if (ret)
  354. return ret;
  355. *valuep = value;
  356. return 0;
  357. }
  358. int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
  359. {
  360. unsigned long value;
  361. int ret;
  362. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  363. if (ret)
  364. return ret;
  365. *valuep = value;
  366. return 0;
  367. }
  368. int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
  369. {
  370. unsigned long value;
  371. int ret;
  372. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  373. if (ret)
  374. return ret;
  375. *valuep = value;
  376. return 0;
  377. }
  378. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  379. {
  380. u8 val;
  381. int ret;
  382. ret = dm_pci_read_config8(dev, offset, &val);
  383. if (ret)
  384. return ret;
  385. val &= ~clr;
  386. val |= set;
  387. return dm_pci_write_config8(dev, offset, val);
  388. }
  389. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  390. {
  391. u16 val;
  392. int ret;
  393. ret = dm_pci_read_config16(dev, offset, &val);
  394. if (ret)
  395. return ret;
  396. val &= ~clr;
  397. val |= set;
  398. return dm_pci_write_config16(dev, offset, val);
  399. }
  400. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  401. {
  402. u32 val;
  403. int ret;
  404. ret = dm_pci_read_config32(dev, offset, &val);
  405. if (ret)
  406. return ret;
  407. val &= ~clr;
  408. val |= set;
  409. return dm_pci_write_config32(dev, offset, val);
  410. }
  411. static void set_vga_bridge_bits(struct udevice *dev)
  412. {
  413. struct udevice *parent = dev->parent;
  414. u16 bc;
  415. while (parent->seq != 0) {
  416. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  417. bc |= PCI_BRIDGE_CTL_VGA;
  418. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  419. parent = parent->parent;
  420. }
  421. }
  422. int pci_auto_config_devices(struct udevice *bus)
  423. {
  424. struct pci_controller *hose = bus->uclass_priv;
  425. struct pci_child_platdata *pplat;
  426. unsigned int sub_bus;
  427. struct udevice *dev;
  428. int ret;
  429. sub_bus = bus->seq;
  430. debug("%s: start\n", __func__);
  431. pciauto_config_init(hose);
  432. for (ret = device_find_first_child(bus, &dev);
  433. !ret && dev;
  434. ret = device_find_next_child(&dev)) {
  435. unsigned int max_bus;
  436. int ret;
  437. debug("%s: device %s\n", __func__, dev->name);
  438. ret = dm_pciauto_config_device(dev);
  439. if (ret < 0)
  440. return ret;
  441. max_bus = ret;
  442. sub_bus = max(sub_bus, max_bus);
  443. pplat = dev_get_parent_platdata(dev);
  444. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  445. set_vga_bridge_bits(dev);
  446. }
  447. debug("%s: done\n", __func__);
  448. return sub_bus;
  449. }
  450. int pci_generic_mmap_write_config(
  451. const struct udevice *bus,
  452. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  453. void **addrp),
  454. pci_dev_t bdf,
  455. uint offset,
  456. ulong value,
  457. enum pci_size_t size)
  458. {
  459. void *address;
  460. if (addr_f(bus, bdf, offset, &address) < 0)
  461. return 0;
  462. switch (size) {
  463. case PCI_SIZE_8:
  464. writeb(value, address);
  465. return 0;
  466. case PCI_SIZE_16:
  467. writew(value, address);
  468. return 0;
  469. case PCI_SIZE_32:
  470. writel(value, address);
  471. return 0;
  472. default:
  473. return -EINVAL;
  474. }
  475. }
  476. int pci_generic_mmap_read_config(
  477. const struct udevice *bus,
  478. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  479. void **addrp),
  480. pci_dev_t bdf,
  481. uint offset,
  482. ulong *valuep,
  483. enum pci_size_t size)
  484. {
  485. void *address;
  486. if (addr_f(bus, bdf, offset, &address) < 0) {
  487. *valuep = pci_get_ff(size);
  488. return 0;
  489. }
  490. switch (size) {
  491. case PCI_SIZE_8:
  492. *valuep = readb(address);
  493. return 0;
  494. case PCI_SIZE_16:
  495. *valuep = readw(address);
  496. return 0;
  497. case PCI_SIZE_32:
  498. *valuep = readl(address);
  499. return 0;
  500. default:
  501. return -EINVAL;
  502. }
  503. }
  504. int dm_pci_hose_probe_bus(struct udevice *bus)
  505. {
  506. int sub_bus;
  507. int ret;
  508. debug("%s\n", __func__);
  509. sub_bus = pci_get_bus_max() + 1;
  510. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  511. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  512. ret = device_probe(bus);
  513. if (ret) {
  514. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  515. ret);
  516. return ret;
  517. }
  518. if (sub_bus != bus->seq) {
  519. printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
  520. __func__, bus->name, bus->seq, sub_bus);
  521. return -EPIPE;
  522. }
  523. sub_bus = pci_get_bus_max();
  524. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  525. return sub_bus;
  526. }
  527. /**
  528. * pci_match_one_device - Tell if a PCI device structure has a matching
  529. * PCI device id structure
  530. * @id: single PCI device id structure to match
  531. * @find: the PCI device id structure to match against
  532. *
  533. * Returns true if the finding pci_device_id structure matched or false if
  534. * there is no match.
  535. */
  536. static bool pci_match_one_id(const struct pci_device_id *id,
  537. const struct pci_device_id *find)
  538. {
  539. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  540. (id->device == PCI_ANY_ID || id->device == find->device) &&
  541. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  542. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  543. !((id->class ^ find->class) & id->class_mask))
  544. return true;
  545. return false;
  546. }
  547. /**
  548. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  549. *
  550. * This only looks at certain fields in the descriptor.
  551. *
  552. * @parent: Parent bus
  553. * @find_id: Specification of the driver to find
  554. * @bdf: Bus/device/function addreess - see PCI_BDF()
  555. * @devp: Returns a pointer to the device created
  556. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  557. * therefore was not created, other -ve value on error
  558. */
  559. static int pci_find_and_bind_driver(struct udevice *parent,
  560. struct pci_device_id *find_id,
  561. pci_dev_t bdf, struct udevice **devp)
  562. {
  563. struct pci_driver_entry *start, *entry;
  564. ofnode node = ofnode_null();
  565. const char *drv;
  566. int n_ents;
  567. int ret;
  568. char name[30], *str;
  569. bool bridge;
  570. *devp = NULL;
  571. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  572. find_id->vendor, find_id->device);
  573. /* Determine optional OF node */
  574. pci_dev_find_ofnode(parent, bdf, &node);
  575. if (ofnode_valid(node) && !ofnode_is_available(node)) {
  576. debug("%s: Ignoring disabled device\n", __func__);
  577. return -EPERM;
  578. }
  579. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  580. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  581. for (entry = start; entry != start + n_ents; entry++) {
  582. const struct pci_device_id *id;
  583. struct udevice *dev;
  584. const struct driver *drv;
  585. for (id = entry->match;
  586. id->vendor || id->subvendor || id->class_mask;
  587. id++) {
  588. if (!pci_match_one_id(id, find_id))
  589. continue;
  590. drv = entry->driver;
  591. /*
  592. * In the pre-relocation phase, we only bind devices
  593. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  594. * precious memory space as on some platforms as that
  595. * space is pretty limited (ie: using Cache As RAM).
  596. */
  597. if (!(gd->flags & GD_FLG_RELOC) &&
  598. !(drv->flags & DM_FLAG_PRE_RELOC))
  599. return -EPERM;
  600. /*
  601. * We could pass the descriptor to the driver as
  602. * platdata (instead of NULL) and allow its bind()
  603. * method to return -ENOENT if it doesn't support this
  604. * device. That way we could continue the search to
  605. * find another driver. For now this doesn't seem
  606. * necesssary, so just bind the first match.
  607. */
  608. ret = device_bind_ofnode(parent, drv, drv->name, NULL,
  609. node, &dev);
  610. if (ret)
  611. goto error;
  612. debug("%s: Match found: %s\n", __func__, drv->name);
  613. dev->driver_data = id->driver_data;
  614. *devp = dev;
  615. return 0;
  616. }
  617. }
  618. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  619. /*
  620. * In the pre-relocation phase, we only bind bridge devices to save
  621. * precious memory space as on some platforms as that space is pretty
  622. * limited (ie: using Cache As RAM).
  623. */
  624. if (!(gd->flags & GD_FLG_RELOC) && !bridge)
  625. return -EPERM;
  626. /* Bind a generic driver so that the device can be used */
  627. sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
  628. PCI_FUNC(bdf));
  629. str = strdup(name);
  630. if (!str)
  631. return -ENOMEM;
  632. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  633. ret = device_bind_driver_to_node(parent, drv, str, node, devp);
  634. if (ret) {
  635. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  636. free(str);
  637. return ret;
  638. }
  639. debug("%s: No match found: bound generic driver instead\n", __func__);
  640. return 0;
  641. error:
  642. debug("%s: No match found: error %d\n", __func__, ret);
  643. return ret;
  644. }
  645. int pci_bind_bus_devices(struct udevice *bus)
  646. {
  647. ulong vendor, device;
  648. ulong header_type;
  649. pci_dev_t bdf, end;
  650. bool found_multi;
  651. int ret;
  652. found_multi = false;
  653. end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
  654. PCI_MAX_PCI_FUNCTIONS - 1);
  655. for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
  656. bdf += PCI_BDF(0, 0, 1)) {
  657. struct pci_child_platdata *pplat;
  658. struct udevice *dev;
  659. ulong class;
  660. if (!PCI_FUNC(bdf))
  661. found_multi = false;
  662. if (PCI_FUNC(bdf) && !found_multi)
  663. continue;
  664. /* Check only the first access, we don't expect problems */
  665. ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  666. PCI_SIZE_16);
  667. if (ret)
  668. goto error;
  669. if (vendor == 0xffff || vendor == 0x0000)
  670. continue;
  671. pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  672. &header_type, PCI_SIZE_8);
  673. if (!PCI_FUNC(bdf))
  674. found_multi = header_type & 0x80;
  675. debug("%s: bus %d/%s: found device %x, function %d", __func__,
  676. bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  677. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  678. PCI_SIZE_16);
  679. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  680. PCI_SIZE_32);
  681. class >>= 8;
  682. /* Find this device in the device tree */
  683. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  684. debug(": find ret=%d\n", ret);
  685. /* If nothing in the device tree, bind a device */
  686. if (ret == -ENODEV) {
  687. struct pci_device_id find_id;
  688. ulong val;
  689. memset(&find_id, '\0', sizeof(find_id));
  690. find_id.vendor = vendor;
  691. find_id.device = device;
  692. find_id.class = class;
  693. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  694. pci_bus_read_config(bus, bdf,
  695. PCI_SUBSYSTEM_VENDOR_ID,
  696. &val, PCI_SIZE_32);
  697. find_id.subvendor = val & 0xffff;
  698. find_id.subdevice = val >> 16;
  699. }
  700. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  701. &dev);
  702. }
  703. if (ret == -EPERM)
  704. continue;
  705. else if (ret)
  706. return ret;
  707. /* Update the platform data */
  708. pplat = dev_get_parent_platdata(dev);
  709. pplat->devfn = PCI_MASK_BUS(bdf);
  710. pplat->vendor = vendor;
  711. pplat->device = device;
  712. pplat->class = class;
  713. }
  714. return 0;
  715. error:
  716. printf("Cannot read bus configuration: %d\n", ret);
  717. return ret;
  718. }
  719. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  720. ofnode node)
  721. {
  722. int pci_addr_cells, addr_cells, size_cells;
  723. int cells_per_record;
  724. const u32 *prop;
  725. int len;
  726. int i;
  727. prop = ofnode_get_property(node, "ranges", &len);
  728. if (!prop) {
  729. debug("%s: Cannot decode regions\n", __func__);
  730. return;
  731. }
  732. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  733. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  734. size_cells = ofnode_read_simple_size_cells(node);
  735. /* PCI addresses are always 3-cells */
  736. len /= sizeof(u32);
  737. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  738. hose->region_count = 0;
  739. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  740. cells_per_record);
  741. for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
  742. u64 pci_addr, addr, size;
  743. int space_code;
  744. u32 flags;
  745. int type;
  746. int pos;
  747. if (len < cells_per_record)
  748. break;
  749. flags = fdt32_to_cpu(prop[0]);
  750. space_code = (flags >> 24) & 3;
  751. pci_addr = fdtdec_get_number(prop + 1, 2);
  752. prop += pci_addr_cells;
  753. addr = fdtdec_get_number(prop, addr_cells);
  754. prop += addr_cells;
  755. size = fdtdec_get_number(prop, size_cells);
  756. prop += size_cells;
  757. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  758. __func__, hose->region_count, pci_addr, addr, size, space_code);
  759. if (space_code & 2) {
  760. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  761. PCI_REGION_MEM;
  762. } else if (space_code & 1) {
  763. type = PCI_REGION_IO;
  764. } else {
  765. continue;
  766. }
  767. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  768. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  769. debug(" - beyond the 32-bit boundary, ignoring\n");
  770. continue;
  771. }
  772. pos = -1;
  773. for (i = 0; i < hose->region_count; i++) {
  774. if (hose->regions[i].flags == type)
  775. pos = i;
  776. }
  777. if (pos == -1)
  778. pos = hose->region_count++;
  779. debug(" - type=%d, pos=%d\n", type, pos);
  780. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  781. }
  782. /* Add a region for our local memory */
  783. #ifdef CONFIG_NR_DRAM_BANKS
  784. bd_t *bd = gd->bd;
  785. if (!bd)
  786. return;
  787. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  788. if (hose->region_count == MAX_PCI_REGIONS) {
  789. pr_err("maximum number of regions parsed, aborting\n");
  790. break;
  791. }
  792. if (bd->bi_dram[i].size) {
  793. pci_set_region(hose->regions + hose->region_count++,
  794. bd->bi_dram[i].start,
  795. bd->bi_dram[i].start,
  796. bd->bi_dram[i].size,
  797. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  798. }
  799. }
  800. #else
  801. phys_addr_t base = 0, size;
  802. size = gd->ram_size;
  803. #ifdef CONFIG_SYS_SDRAM_BASE
  804. base = CONFIG_SYS_SDRAM_BASE;
  805. #endif
  806. if (gd->pci_ram_top && gd->pci_ram_top < base + size)
  807. size = gd->pci_ram_top - base;
  808. if (size)
  809. pci_set_region(hose->regions + hose->region_count++, base,
  810. base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  811. #endif
  812. return;
  813. }
  814. static int pci_uclass_pre_probe(struct udevice *bus)
  815. {
  816. struct pci_controller *hose;
  817. debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
  818. bus->parent->name);
  819. hose = bus->uclass_priv;
  820. /* For bridges, use the top-level PCI controller */
  821. if (!device_is_on_pci_bus(bus)) {
  822. hose->ctlr = bus;
  823. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  824. } else {
  825. struct pci_controller *parent_hose;
  826. parent_hose = dev_get_uclass_priv(bus->parent);
  827. hose->ctlr = parent_hose->bus;
  828. }
  829. hose->bus = bus;
  830. hose->first_busno = bus->seq;
  831. hose->last_busno = bus->seq;
  832. hose->skip_auto_config_until_reloc =
  833. dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
  834. return 0;
  835. }
  836. static int pci_uclass_post_probe(struct udevice *bus)
  837. {
  838. struct pci_controller *hose = dev_get_uclass_priv(bus);
  839. int ret;
  840. debug("%s: probing bus %d\n", __func__, bus->seq);
  841. ret = pci_bind_bus_devices(bus);
  842. if (ret)
  843. return ret;
  844. if (CONFIG_IS_ENABLED(PCI_PNP) &&
  845. (!hose->skip_auto_config_until_reloc ||
  846. (gd->flags & GD_FLG_RELOC))) {
  847. ret = pci_auto_config_devices(bus);
  848. if (ret < 0)
  849. return log_msg_ret("pci auto-config", ret);
  850. }
  851. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  852. /*
  853. * Per Intel FSP specification, we should call FSP notify API to
  854. * inform FSP that PCI enumeration has been done so that FSP will
  855. * do any necessary initialization as required by the chipset's
  856. * BIOS Writer's Guide (BWG).
  857. *
  858. * Unfortunately we have to put this call here as with driver model,
  859. * the enumeration is all done on a lazy basis as needed, so until
  860. * something is touched on PCI it won't happen.
  861. *
  862. * Note we only call this 1) after U-Boot is relocated, and 2)
  863. * root bus has finished probing.
  864. */
  865. if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
  866. ret = fsp_init_phase_pci();
  867. if (ret)
  868. return ret;
  869. }
  870. #endif
  871. return 0;
  872. }
  873. static int pci_uclass_child_post_bind(struct udevice *dev)
  874. {
  875. struct pci_child_platdata *pplat;
  876. if (!dev_of_valid(dev))
  877. return 0;
  878. pplat = dev_get_parent_platdata(dev);
  879. /* Extract vendor id and device id if available */
  880. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  881. /* Extract the devfn from fdt_pci_addr */
  882. pplat->devfn = pci_get_devfn(dev);
  883. return 0;
  884. }
  885. static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
  886. uint offset, ulong *valuep,
  887. enum pci_size_t size)
  888. {
  889. struct pci_controller *hose = bus->uclass_priv;
  890. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  891. }
  892. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  893. uint offset, ulong value,
  894. enum pci_size_t size)
  895. {
  896. struct pci_controller *hose = bus->uclass_priv;
  897. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  898. }
  899. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  900. {
  901. struct udevice *dev;
  902. int ret = 0;
  903. /*
  904. * Scan through all the PCI controllers. On x86 there will only be one
  905. * but that is not necessarily true on other hardware.
  906. */
  907. do {
  908. device_find_first_child(bus, &dev);
  909. if (dev) {
  910. *devp = dev;
  911. return 0;
  912. }
  913. ret = uclass_next_device(&bus);
  914. if (ret)
  915. return ret;
  916. } while (bus);
  917. return 0;
  918. }
  919. int pci_find_next_device(struct udevice **devp)
  920. {
  921. struct udevice *child = *devp;
  922. struct udevice *bus = child->parent;
  923. int ret;
  924. /* First try all the siblings */
  925. *devp = NULL;
  926. while (child) {
  927. device_find_next_child(&child);
  928. if (child) {
  929. *devp = child;
  930. return 0;
  931. }
  932. }
  933. /* We ran out of siblings. Try the next bus */
  934. ret = uclass_next_device(&bus);
  935. if (ret)
  936. return ret;
  937. return bus ? skip_to_next_device(bus, devp) : 0;
  938. }
  939. int pci_find_first_device(struct udevice **devp)
  940. {
  941. struct udevice *bus;
  942. int ret;
  943. *devp = NULL;
  944. ret = uclass_first_device(UCLASS_PCI, &bus);
  945. if (ret)
  946. return ret;
  947. return skip_to_next_device(bus, devp);
  948. }
  949. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  950. {
  951. switch (size) {
  952. case PCI_SIZE_8:
  953. return (value >> ((offset & 3) * 8)) & 0xff;
  954. case PCI_SIZE_16:
  955. return (value >> ((offset & 2) * 8)) & 0xffff;
  956. default:
  957. return value;
  958. }
  959. }
  960. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  961. enum pci_size_t size)
  962. {
  963. uint off_mask;
  964. uint val_mask, shift;
  965. ulong ldata, mask;
  966. switch (size) {
  967. case PCI_SIZE_8:
  968. off_mask = 3;
  969. val_mask = 0xff;
  970. break;
  971. case PCI_SIZE_16:
  972. off_mask = 2;
  973. val_mask = 0xffff;
  974. break;
  975. default:
  976. return value;
  977. }
  978. shift = (offset & off_mask) * 8;
  979. ldata = (value & val_mask) << shift;
  980. mask = val_mask << shift;
  981. value = (old & ~mask) | ldata;
  982. return value;
  983. }
  984. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  985. struct pci_region **memp, struct pci_region **prefp)
  986. {
  987. struct udevice *bus = pci_get_controller(dev);
  988. struct pci_controller *hose = dev_get_uclass_priv(bus);
  989. int i;
  990. *iop = NULL;
  991. *memp = NULL;
  992. *prefp = NULL;
  993. for (i = 0; i < hose->region_count; i++) {
  994. switch (hose->regions[i].flags) {
  995. case PCI_REGION_IO:
  996. if (!*iop || (*iop)->size < hose->regions[i].size)
  997. *iop = hose->regions + i;
  998. break;
  999. case PCI_REGION_MEM:
  1000. if (!*memp || (*memp)->size < hose->regions[i].size)
  1001. *memp = hose->regions + i;
  1002. break;
  1003. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  1004. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  1005. *prefp = hose->regions + i;
  1006. break;
  1007. }
  1008. }
  1009. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  1010. }
  1011. u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
  1012. {
  1013. u32 addr;
  1014. int bar;
  1015. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1016. dm_pci_read_config32(dev, bar, &addr);
  1017. if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  1018. return addr & PCI_BASE_ADDRESS_IO_MASK;
  1019. else
  1020. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  1021. }
  1022. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  1023. {
  1024. int bar;
  1025. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1026. dm_pci_write_config32(dev, bar, addr);
  1027. }
  1028. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  1029. pci_addr_t bus_addr, unsigned long flags,
  1030. unsigned long skip_mask, phys_addr_t *pa)
  1031. {
  1032. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  1033. struct pci_region *res;
  1034. int i;
  1035. if (hose->region_count == 0) {
  1036. *pa = bus_addr;
  1037. return 0;
  1038. }
  1039. for (i = 0; i < hose->region_count; i++) {
  1040. res = &hose->regions[i];
  1041. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1042. continue;
  1043. if (res->flags & skip_mask)
  1044. continue;
  1045. if (bus_addr >= res->bus_start &&
  1046. (bus_addr - res->bus_start) < res->size) {
  1047. *pa = (bus_addr - res->bus_start + res->phys_start);
  1048. return 0;
  1049. }
  1050. }
  1051. return 1;
  1052. }
  1053. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1054. unsigned long flags)
  1055. {
  1056. phys_addr_t phys_addr = 0;
  1057. struct udevice *ctlr;
  1058. int ret;
  1059. /* The root controller has the region information */
  1060. ctlr = pci_get_controller(dev);
  1061. /*
  1062. * if PCI_REGION_MEM is set we do a two pass search with preference
  1063. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1064. */
  1065. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1066. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1067. flags, PCI_REGION_SYS_MEMORY,
  1068. &phys_addr);
  1069. if (!ret)
  1070. return phys_addr;
  1071. }
  1072. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1073. if (ret)
  1074. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1075. return phys_addr;
  1076. }
  1077. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1078. unsigned long flags, unsigned long skip_mask,
  1079. pci_addr_t *ba)
  1080. {
  1081. struct pci_region *res;
  1082. struct udevice *ctlr;
  1083. pci_addr_t bus_addr;
  1084. int i;
  1085. struct pci_controller *hose;
  1086. /* The root controller has the region information */
  1087. ctlr = pci_get_controller(dev);
  1088. hose = dev_get_uclass_priv(ctlr);
  1089. if (hose->region_count == 0) {
  1090. *ba = phys_addr;
  1091. return 0;
  1092. }
  1093. for (i = 0; i < hose->region_count; i++) {
  1094. res = &hose->regions[i];
  1095. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1096. continue;
  1097. if (res->flags & skip_mask)
  1098. continue;
  1099. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1100. if (bus_addr >= res->bus_start &&
  1101. (bus_addr - res->bus_start) < res->size) {
  1102. *ba = bus_addr;
  1103. return 0;
  1104. }
  1105. }
  1106. return 1;
  1107. }
  1108. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1109. unsigned long flags)
  1110. {
  1111. pci_addr_t bus_addr = 0;
  1112. int ret;
  1113. /*
  1114. * if PCI_REGION_MEM is set we do a two pass search with preference
  1115. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1116. */
  1117. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1118. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1119. PCI_REGION_SYS_MEMORY, &bus_addr);
  1120. if (!ret)
  1121. return bus_addr;
  1122. }
  1123. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1124. if (ret)
  1125. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1126. return bus_addr;
  1127. }
  1128. static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
  1129. int ea_off)
  1130. {
  1131. int ea_cnt, i, entry_size;
  1132. int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
  1133. u32 ea_entry;
  1134. phys_addr_t addr;
  1135. /* EA capability structure header */
  1136. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1137. ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
  1138. ea_off += PCI_EA_FIRST_ENT;
  1139. for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
  1140. /* Entry header */
  1141. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1142. entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
  1143. if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
  1144. continue;
  1145. /* Base address, 1st DW */
  1146. dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
  1147. addr = ea_entry & PCI_EA_FIELD_MASK;
  1148. if (ea_entry & PCI_EA_IS_64) {
  1149. /* Base address, 2nd DW, skip over 4B MaxOffset */
  1150. dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
  1151. addr |= ((u64)ea_entry) << 32;
  1152. }
  1153. /* size ignored for now */
  1154. return map_physmem(addr, flags, 0);
  1155. }
  1156. return 0;
  1157. }
  1158. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1159. {
  1160. pci_addr_t pci_bus_addr;
  1161. u32 bar_response;
  1162. int ea_off;
  1163. /*
  1164. * if the function supports Enhanced Allocation use that instead of
  1165. * BARs
  1166. */
  1167. ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
  1168. if (ea_off)
  1169. return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
  1170. /* read BAR address */
  1171. dm_pci_read_config32(dev, bar, &bar_response);
  1172. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1173. /*
  1174. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1175. * isn't actualy used on any platform because u-boot assumes a static
  1176. * linear mapping. In the future, this could read the BAR size
  1177. * and pass that as the size if needed.
  1178. */
  1179. return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1180. }
  1181. static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
  1182. {
  1183. int ttl = PCI_FIND_CAP_TTL;
  1184. u8 id;
  1185. u16 ent;
  1186. dm_pci_read_config8(dev, pos, &pos);
  1187. while (ttl--) {
  1188. if (pos < PCI_STD_HEADER_SIZEOF)
  1189. break;
  1190. pos &= ~3;
  1191. dm_pci_read_config16(dev, pos, &ent);
  1192. id = ent & 0xff;
  1193. if (id == 0xff)
  1194. break;
  1195. if (id == cap)
  1196. return pos;
  1197. pos = (ent >> 8);
  1198. }
  1199. return 0;
  1200. }
  1201. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
  1202. {
  1203. return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
  1204. cap);
  1205. }
  1206. int dm_pci_find_capability(struct udevice *dev, int cap)
  1207. {
  1208. u16 status;
  1209. u8 header_type;
  1210. u8 pos;
  1211. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1212. if (!(status & PCI_STATUS_CAP_LIST))
  1213. return 0;
  1214. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1215. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1216. pos = PCI_CB_CAPABILITY_LIST;
  1217. else
  1218. pos = PCI_CAPABILITY_LIST;
  1219. return _dm_pci_find_next_capability(dev, pos, cap);
  1220. }
  1221. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
  1222. {
  1223. u32 header;
  1224. int ttl;
  1225. int pos = PCI_CFG_SPACE_SIZE;
  1226. /* minimum 8 bytes per capability */
  1227. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1228. if (start)
  1229. pos = start;
  1230. dm_pci_read_config32(dev, pos, &header);
  1231. /*
  1232. * If we have no capabilities, this is indicated by cap ID,
  1233. * cap version and next pointer all being 0.
  1234. */
  1235. if (header == 0)
  1236. return 0;
  1237. while (ttl--) {
  1238. if (PCI_EXT_CAP_ID(header) == cap)
  1239. return pos;
  1240. pos = PCI_EXT_CAP_NEXT(header);
  1241. if (pos < PCI_CFG_SPACE_SIZE)
  1242. break;
  1243. dm_pci_read_config32(dev, pos, &header);
  1244. }
  1245. return 0;
  1246. }
  1247. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1248. {
  1249. return dm_pci_find_next_ext_capability(dev, 0, cap);
  1250. }
  1251. int dm_pci_flr(struct udevice *dev)
  1252. {
  1253. int pcie_off;
  1254. u32 cap;
  1255. /* look for PCI Express Capability */
  1256. pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
  1257. if (!pcie_off)
  1258. return -ENOENT;
  1259. /* check FLR capability */
  1260. dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
  1261. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1262. return -ENOENT;
  1263. dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
  1264. PCI_EXP_DEVCTL_BCR_FLR);
  1265. /* wait 100ms, per PCI spec */
  1266. mdelay(100);
  1267. return 0;
  1268. }
  1269. UCLASS_DRIVER(pci) = {
  1270. .id = UCLASS_PCI,
  1271. .name = "pci",
  1272. .flags = DM_UC_FLAG_SEQ_ALIAS,
  1273. .post_bind = dm_scan_fdt_dev,
  1274. .pre_probe = pci_uclass_pre_probe,
  1275. .post_probe = pci_uclass_post_probe,
  1276. .child_post_bind = pci_uclass_child_post_bind,
  1277. .per_device_auto_alloc_size = sizeof(struct pci_controller),
  1278. .per_child_platdata_auto_alloc_size =
  1279. sizeof(struct pci_child_platdata),
  1280. };
  1281. static const struct dm_pci_ops pci_bridge_ops = {
  1282. .read_config = pci_bridge_read_config,
  1283. .write_config = pci_bridge_write_config,
  1284. };
  1285. static const struct udevice_id pci_bridge_ids[] = {
  1286. { .compatible = "pci-bridge" },
  1287. { }
  1288. };
  1289. U_BOOT_DRIVER(pci_bridge_drv) = {
  1290. .name = "pci_bridge_drv",
  1291. .id = UCLASS_PCI,
  1292. .of_match = pci_bridge_ids,
  1293. .ops = &pci_bridge_ops,
  1294. };
  1295. UCLASS_DRIVER(pci_generic) = {
  1296. .id = UCLASS_PCI_GENERIC,
  1297. .name = "pci_generic",
  1298. };
  1299. static const struct udevice_id pci_generic_ids[] = {
  1300. { .compatible = "pci-generic" },
  1301. { }
  1302. };
  1303. U_BOOT_DRIVER(pci_generic_drv) = {
  1304. .name = "pci_generic_drv",
  1305. .id = UCLASS_PCI_GENERIC,
  1306. .of_match = pci_generic_ids,
  1307. };
  1308. void pci_init(void)
  1309. {
  1310. struct udevice *bus;
  1311. /*
  1312. * Enumerate all known controller devices. Enumeration has the side-
  1313. * effect of probing them, so PCIe devices will be enumerated too.
  1314. */
  1315. for (uclass_first_device_check(UCLASS_PCI, &bus);
  1316. bus;
  1317. uclass_next_device_check(&bus)) {
  1318. ;
  1319. }
  1320. }