tsec.c 18 KB

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  1. /*
  2. * Freescale Three Speed Ethernet Controller driver
  3. *
  4. * This software may be used and distributed according to the
  5. * terms of the GNU Public License, Version 2, incorporated
  6. * herein by reference.
  7. *
  8. * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
  9. * (C) Copyright 2003, Motorola, Inc.
  10. * author Andy Fleming
  11. *
  12. */
  13. #include <config.h>
  14. #include <common.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <command.h>
  18. #include <tsec.h>
  19. #include <fsl_mdio.h>
  20. #include <asm/errno.h>
  21. #include <asm/processor.h>
  22. #include <asm/io.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define TX_BUF_CNT 2
  25. static uint rx_idx; /* index of the current RX buffer */
  26. static uint tx_idx; /* index of the current TX buffer */
  27. #ifdef __GNUC__
  28. static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
  29. static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
  30. #else
  31. #error "rtx must be 64-bit aligned"
  32. #endif
  33. static int tsec_send(struct eth_device *dev, void *packet, int length);
  34. /* Default initializations for TSEC controllers. */
  35. static struct tsec_info_struct tsec_info[] = {
  36. #ifdef CONFIG_TSEC1
  37. STD_TSEC_INFO(1), /* TSEC1 */
  38. #endif
  39. #ifdef CONFIG_TSEC2
  40. STD_TSEC_INFO(2), /* TSEC2 */
  41. #endif
  42. #ifdef CONFIG_MPC85XX_FEC
  43. {
  44. .regs = TSEC_GET_REGS(2, 0x2000),
  45. .devname = CONFIG_MPC85XX_FEC_NAME,
  46. .phyaddr = FEC_PHY_ADDR,
  47. .flags = FEC_FLAGS,
  48. .mii_devname = DEFAULT_MII_NAME
  49. }, /* FEC */
  50. #endif
  51. #ifdef CONFIG_TSEC3
  52. STD_TSEC_INFO(3), /* TSEC3 */
  53. #endif
  54. #ifdef CONFIG_TSEC4
  55. STD_TSEC_INFO(4), /* TSEC4 */
  56. #endif
  57. };
  58. #define TBIANA_SETTINGS ( \
  59. TBIANA_ASYMMETRIC_PAUSE \
  60. | TBIANA_SYMMETRIC_PAUSE \
  61. | TBIANA_FULL_DUPLEX \
  62. )
  63. /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  64. #ifndef CONFIG_TSEC_TBICR_SETTINGS
  65. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  66. TBICR_PHY_RESET \
  67. | TBICR_ANEG_ENABLE \
  68. | TBICR_FULL_DUPLEX \
  69. | TBICR_SPEED1_SET \
  70. )
  71. #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  72. /* Configure the TBI for SGMII operation */
  73. static void tsec_configure_serdes(struct tsec_private *priv)
  74. {
  75. /* Access TBI PHY registers at given TSEC register offset as opposed
  76. * to the register offset used for external PHY accesses */
  77. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  78. 0, TBI_ANA, TBIANA_SETTINGS);
  79. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  80. 0, TBI_TBICON, TBICON_CLK_SELECT);
  81. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  82. 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  83. }
  84. #ifdef CONFIG_MCAST_TFTP
  85. /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  86. /* Set the appropriate hash bit for the given addr */
  87. /* The algorithm works like so:
  88. * 1) Take the Destination Address (ie the multicast address), and
  89. * do a CRC on it (little endian), and reverse the bits of the
  90. * result.
  91. * 2) Use the 8 most significant bits as a hash into a 256-entry
  92. * table. The table is controlled through 8 32-bit registers:
  93. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
  94. * 255. This means that the 3 most significant bits in the
  95. * hash index which gaddr register to use, and the 5 other bits
  96. * indicate which bit (assuming an IBM numbering scheme, which
  97. * for PowerPC (tm) is usually the case) in the register holds
  98. * the entry. */
  99. static int
  100. tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
  101. {
  102. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  103. struct tsec __iomem *regs = priv->regs;
  104. u32 result, value;
  105. u8 whichbit, whichreg;
  106. result = ether_crc(MAC_ADDR_LEN, mcast_mac);
  107. whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
  108. whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
  109. value = 1 << (31-whichbit);
  110. if (set)
  111. setbits_be32(&regs->hash.gaddr0 + whichreg, value);
  112. else
  113. clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
  114. return 0;
  115. }
  116. #endif /* Multicast TFTP ? */
  117. /* Initialized required registers to appropriate values, zeroing
  118. * those we don't care about (unless zero is bad, in which case,
  119. * choose a more appropriate value)
  120. */
  121. static void init_registers(struct tsec __iomem *regs)
  122. {
  123. /* Clear IEVENT */
  124. out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  125. out_be32(&regs->imask, IMASK_INIT_CLEAR);
  126. out_be32(&regs->hash.iaddr0, 0);
  127. out_be32(&regs->hash.iaddr1, 0);
  128. out_be32(&regs->hash.iaddr2, 0);
  129. out_be32(&regs->hash.iaddr3, 0);
  130. out_be32(&regs->hash.iaddr4, 0);
  131. out_be32(&regs->hash.iaddr5, 0);
  132. out_be32(&regs->hash.iaddr6, 0);
  133. out_be32(&regs->hash.iaddr7, 0);
  134. out_be32(&regs->hash.gaddr0, 0);
  135. out_be32(&regs->hash.gaddr1, 0);
  136. out_be32(&regs->hash.gaddr2, 0);
  137. out_be32(&regs->hash.gaddr3, 0);
  138. out_be32(&regs->hash.gaddr4, 0);
  139. out_be32(&regs->hash.gaddr5, 0);
  140. out_be32(&regs->hash.gaddr6, 0);
  141. out_be32(&regs->hash.gaddr7, 0);
  142. out_be32(&regs->rctrl, 0x00000000);
  143. /* Init RMON mib registers */
  144. memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
  145. out_be32(&regs->rmon.cam1, 0xffffffff);
  146. out_be32(&regs->rmon.cam2, 0xffffffff);
  147. out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  148. out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  149. out_be32(&regs->attr, ATTR_INIT_SETTINGS);
  150. out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  151. }
  152. /* Configure maccfg2 based on negotiated speed and duplex
  153. * reported by PHY handling code
  154. */
  155. static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  156. {
  157. struct tsec __iomem *regs = priv->regs;
  158. u32 ecntrl, maccfg2;
  159. if (!phydev->link) {
  160. printf("%s: No link.\n", phydev->dev->name);
  161. return;
  162. }
  163. /* clear all bits relative with interface mode */
  164. ecntrl = in_be32(&regs->ecntrl);
  165. ecntrl &= ~ECNTRL_R100;
  166. maccfg2 = in_be32(&regs->maccfg2);
  167. maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  168. if (phydev->duplex)
  169. maccfg2 |= MACCFG2_FULL_DUPLEX;
  170. switch (phydev->speed) {
  171. case 1000:
  172. maccfg2 |= MACCFG2_GMII;
  173. break;
  174. case 100:
  175. case 10:
  176. maccfg2 |= MACCFG2_MII;
  177. /* Set R100 bit in all modes although
  178. * it is only used in RGMII mode
  179. */
  180. if (phydev->speed == 100)
  181. ecntrl |= ECNTRL_R100;
  182. break;
  183. default:
  184. printf("%s: Speed was bad\n", phydev->dev->name);
  185. break;
  186. }
  187. out_be32(&regs->ecntrl, ecntrl);
  188. out_be32(&regs->maccfg2, maccfg2);
  189. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  190. (phydev->duplex) ? "full" : "half",
  191. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  192. }
  193. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  194. /*
  195. * When MACCFG1[Rx_EN] is enabled during system boot as part
  196. * of the eTSEC port initialization sequence,
  197. * the eTSEC Rx logic may not be properly initialized.
  198. */
  199. void redundant_init(struct eth_device *dev)
  200. {
  201. struct tsec_private *priv = dev->priv;
  202. struct tsec __iomem *regs = priv->regs;
  203. uint t, count = 0;
  204. int fail = 1;
  205. static const u8 pkt[] = {
  206. 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
  207. 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
  208. 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
  209. 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
  210. 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
  211. 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
  212. 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
  213. 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
  214. 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  215. 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  216. 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
  217. 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
  218. 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
  219. 0x71, 0x72};
  220. /* Enable promiscuous mode */
  221. setbits_be32(&regs->rctrl, 0x8);
  222. /* Enable loopback mode */
  223. setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  224. /* Enable transmit and receive */
  225. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  226. /* Tell the DMA it is clear to go */
  227. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  228. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  229. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  230. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  231. do {
  232. uint16_t status;
  233. tsec_send(dev, (void *)pkt, sizeof(pkt));
  234. /* Wait for buffer to be received */
  235. for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
  236. if (t >= 10 * TOUT_LOOP) {
  237. printf("%s: tsec: rx error\n", dev->name);
  238. break;
  239. }
  240. }
  241. if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt)))
  242. fail = 0;
  243. out_be16(&rxbd[rx_idx].length, 0);
  244. status = RXBD_EMPTY;
  245. if ((rx_idx + 1) == PKTBUFSRX)
  246. status |= RXBD_WRAP;
  247. out_be16(&rxbd[rx_idx].status, status);
  248. rx_idx = (rx_idx + 1) % PKTBUFSRX;
  249. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  250. out_be32(&regs->ievent, IEVENT_BSY);
  251. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  252. }
  253. if (fail) {
  254. printf("loopback recv packet error!\n");
  255. clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  256. udelay(1000);
  257. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  258. }
  259. } while ((count++ < 4) && (fail == 1));
  260. if (fail)
  261. panic("eTSEC init fail!\n");
  262. /* Disable promiscuous mode */
  263. clrbits_be32(&regs->rctrl, 0x8);
  264. /* Disable loopback mode */
  265. clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  266. }
  267. #endif
  268. /* Set up the buffers and their descriptors, and bring up the
  269. * interface
  270. */
  271. static void startup_tsec(struct eth_device *dev)
  272. {
  273. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  274. struct tsec __iomem *regs = priv->regs;
  275. uint16_t status;
  276. int i;
  277. /* reset the indices to zero */
  278. rx_idx = 0;
  279. tx_idx = 0;
  280. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  281. uint svr;
  282. #endif
  283. /* Point to the buffer descriptors */
  284. out_be32(&regs->tbase, (u32)&txbd[0]);
  285. out_be32(&regs->rbase, (u32)&rxbd[0]);
  286. /* Initialize the Rx Buffer descriptors */
  287. for (i = 0; i < PKTBUFSRX; i++) {
  288. out_be16(&rxbd[i].status, RXBD_EMPTY);
  289. out_be16(&rxbd[i].length, 0);
  290. out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]);
  291. }
  292. status = in_be16(&rxbd[PKTBUFSRX - 1].status);
  293. out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
  294. /* Initialize the TX Buffer Descriptors */
  295. for (i = 0; i < TX_BUF_CNT; i++) {
  296. out_be16(&txbd[i].status, 0);
  297. out_be16(&txbd[i].length, 0);
  298. out_be32(&txbd[i].bufptr, 0);
  299. }
  300. status = in_be16(&txbd[TX_BUF_CNT - 1].status);
  301. out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
  302. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  303. svr = get_svr();
  304. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
  305. redundant_init(dev);
  306. #endif
  307. /* Enable Transmit and Receive */
  308. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  309. /* Tell the DMA it is clear to go */
  310. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  311. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  312. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  313. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  314. }
  315. /* This returns the status bits of the device. The return value
  316. * is never checked, and this is what the 8260 driver did, so we
  317. * do the same. Presumably, this would be zero if there were no
  318. * errors
  319. */
  320. static int tsec_send(struct eth_device *dev, void *packet, int length)
  321. {
  322. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  323. struct tsec __iomem *regs = priv->regs;
  324. uint16_t status;
  325. int result = 0;
  326. int i;
  327. /* Find an empty buffer descriptor */
  328. for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
  329. if (i >= TOUT_LOOP) {
  330. debug("%s: tsec: tx buffers full\n", dev->name);
  331. return result;
  332. }
  333. }
  334. out_be32(&txbd[tx_idx].bufptr, (u32)packet);
  335. out_be16(&txbd[tx_idx].length, length);
  336. status = in_be16(&txbd[tx_idx].status);
  337. out_be16(&txbd[tx_idx].status, status |
  338. (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
  339. /* Tell the DMA to go */
  340. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  341. /* Wait for buffer to be transmitted */
  342. for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
  343. if (i >= TOUT_LOOP) {
  344. debug("%s: tsec: tx error\n", dev->name);
  345. return result;
  346. }
  347. }
  348. tx_idx = (tx_idx + 1) % TX_BUF_CNT;
  349. result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
  350. return result;
  351. }
  352. static int tsec_recv(struct eth_device *dev)
  353. {
  354. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  355. struct tsec __iomem *regs = priv->regs;
  356. while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
  357. int length = in_be16(&rxbd[rx_idx].length);
  358. uint16_t status = in_be16(&rxbd[rx_idx].status);
  359. /* Send the packet up if there were no errors */
  360. if (!(status & RXBD_STATS))
  361. net_process_received_packet(net_rx_packets[rx_idx],
  362. length - 4);
  363. else
  364. printf("Got error %x\n", (status & RXBD_STATS));
  365. out_be16(&rxbd[rx_idx].length, 0);
  366. status = RXBD_EMPTY;
  367. /* Set the wrap bit if this is the last element in the list */
  368. if ((rx_idx + 1) == PKTBUFSRX)
  369. status |= RXBD_WRAP;
  370. out_be16(&rxbd[rx_idx].status, status);
  371. rx_idx = (rx_idx + 1) % PKTBUFSRX;
  372. }
  373. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  374. out_be32(&regs->ievent, IEVENT_BSY);
  375. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  376. }
  377. return -1;
  378. }
  379. /* Stop the interface */
  380. static void tsec_halt(struct eth_device *dev)
  381. {
  382. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  383. struct tsec __iomem *regs = priv->regs;
  384. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  385. setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  386. while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
  387. != (IEVENT_GRSC | IEVENT_GTSC))
  388. ;
  389. clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  390. /* Shut down the PHY, as needed */
  391. phy_shutdown(priv->phydev);
  392. }
  393. /* Initializes data structures and registers for the controller,
  394. * and brings the interface up. Returns the link status, meaning
  395. * that it returns success if the link is up, failure otherwise.
  396. * This allows u-boot to find the first active controller.
  397. */
  398. static int tsec_init(struct eth_device *dev, bd_t * bd)
  399. {
  400. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  401. struct tsec __iomem *regs = priv->regs;
  402. u32 tempval;
  403. int ret;
  404. /* Make sure the controller is stopped */
  405. tsec_halt(dev);
  406. /* Init MACCFG2. Defaults to GMII */
  407. out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  408. /* Init ECNTRL */
  409. out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  410. /* Copy the station address into the address registers.
  411. * For a station address of 0x12345678ABCD in transmission
  412. * order (BE), MACnADDR1 is set to 0xCDAB7856 and
  413. * MACnADDR2 is set to 0x34120000.
  414. */
  415. tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
  416. (dev->enetaddr[3] << 8) | dev->enetaddr[2];
  417. out_be32(&regs->macstnaddr1, tempval);
  418. tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
  419. out_be32(&regs->macstnaddr2, tempval);
  420. /* Clear out (for the most part) the other registers */
  421. init_registers(regs);
  422. /* Ready the device for tx/rx */
  423. startup_tsec(dev);
  424. /* Start up the PHY */
  425. ret = phy_startup(priv->phydev);
  426. if (ret) {
  427. printf("Could not initialize PHY %s\n",
  428. priv->phydev->dev->name);
  429. return ret;
  430. }
  431. adjust_link(priv, priv->phydev);
  432. /* If there's no link, fail */
  433. return priv->phydev->link ? 0 : -1;
  434. }
  435. static phy_interface_t tsec_get_interface(struct tsec_private *priv)
  436. {
  437. struct tsec __iomem *regs = priv->regs;
  438. u32 ecntrl;
  439. ecntrl = in_be32(&regs->ecntrl);
  440. if (ecntrl & ECNTRL_SGMII_MODE)
  441. return PHY_INTERFACE_MODE_SGMII;
  442. if (ecntrl & ECNTRL_TBI_MODE) {
  443. if (ecntrl & ECNTRL_REDUCED_MODE)
  444. return PHY_INTERFACE_MODE_RTBI;
  445. else
  446. return PHY_INTERFACE_MODE_TBI;
  447. }
  448. if (ecntrl & ECNTRL_REDUCED_MODE) {
  449. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  450. return PHY_INTERFACE_MODE_RMII;
  451. else {
  452. phy_interface_t interface = priv->interface;
  453. /*
  454. * This isn't autodetected, so it must
  455. * be set by the platform code.
  456. */
  457. if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  458. (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
  459. (interface == PHY_INTERFACE_MODE_RGMII_RXID))
  460. return interface;
  461. return PHY_INTERFACE_MODE_RGMII;
  462. }
  463. }
  464. if (priv->flags & TSEC_GIGABIT)
  465. return PHY_INTERFACE_MODE_GMII;
  466. return PHY_INTERFACE_MODE_MII;
  467. }
  468. /* Discover which PHY is attached to the device, and configure it
  469. * properly. If the PHY is not recognized, then return 0
  470. * (failure). Otherwise, return 1
  471. */
  472. static int init_phy(struct eth_device *dev)
  473. {
  474. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  475. struct phy_device *phydev;
  476. struct tsec __iomem *regs = priv->regs;
  477. u32 supported = (SUPPORTED_10baseT_Half |
  478. SUPPORTED_10baseT_Full |
  479. SUPPORTED_100baseT_Half |
  480. SUPPORTED_100baseT_Full);
  481. if (priv->flags & TSEC_GIGABIT)
  482. supported |= SUPPORTED_1000baseT_Full;
  483. /* Assign a Physical address to the TBI */
  484. out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  485. priv->interface = tsec_get_interface(priv);
  486. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  487. tsec_configure_serdes(priv);
  488. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  489. if (!phydev)
  490. return 0;
  491. phydev->supported &= supported;
  492. phydev->advertising = phydev->supported;
  493. priv->phydev = phydev;
  494. phy_config(phydev);
  495. return 1;
  496. }
  497. /* Initialize device structure. Returns success if PHY
  498. * initialization succeeded (i.e. if it recognizes the PHY)
  499. */
  500. static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
  501. {
  502. struct eth_device *dev;
  503. int i;
  504. struct tsec_private *priv;
  505. dev = (struct eth_device *)malloc(sizeof *dev);
  506. if (NULL == dev)
  507. return 0;
  508. memset(dev, 0, sizeof *dev);
  509. priv = (struct tsec_private *)malloc(sizeof(*priv));
  510. if (NULL == priv)
  511. return 0;
  512. priv->regs = tsec_info->regs;
  513. priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
  514. priv->phyaddr = tsec_info->phyaddr;
  515. priv->flags = tsec_info->flags;
  516. strcpy(dev->name, tsec_info->devname);
  517. priv->interface = tsec_info->interface;
  518. priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
  519. dev->iobase = 0;
  520. dev->priv = priv;
  521. dev->init = tsec_init;
  522. dev->halt = tsec_halt;
  523. dev->send = tsec_send;
  524. dev->recv = tsec_recv;
  525. #ifdef CONFIG_MCAST_TFTP
  526. dev->mcast = tsec_mcast_addr;
  527. #endif
  528. /* Tell u-boot to get the addr from the env */
  529. for (i = 0; i < 6; i++)
  530. dev->enetaddr[i] = 0;
  531. eth_register(dev);
  532. /* Reset the MAC */
  533. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  534. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  535. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  536. /* Try to initialize PHY here, and return */
  537. return init_phy(dev);
  538. }
  539. /*
  540. * Initialize all the TSEC devices
  541. *
  542. * Returns the number of TSEC devices that were initialized
  543. */
  544. int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
  545. {
  546. int i;
  547. int ret, count = 0;
  548. for (i = 0; i < num; i++) {
  549. ret = tsec_initialize(bis, &tsecs[i]);
  550. if (ret > 0)
  551. count += ret;
  552. }
  553. return count;
  554. }
  555. int tsec_standard_init(bd_t *bis)
  556. {
  557. struct fsl_pq_mdio_info info;
  558. info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  559. info.name = DEFAULT_MII_NAME;
  560. fsl_pq_mdio_init(bis, &info);
  561. return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
  562. }