pch_gbe.c 12 KB

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  1. /*
  2. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  3. *
  4. * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <asm/io.h>
  12. #include <pci.h>
  13. #include <miiphy.h>
  14. #include "pch_gbe.h"
  15. #if !defined(CONFIG_PHYLIB)
  16. # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
  17. #endif
  18. static struct pci_device_id supported[] = {
  19. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
  20. { }
  21. };
  22. static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
  23. {
  24. u32 macid_hi, macid_lo;
  25. macid_hi = readl(&mac_regs->mac_adr[0].high);
  26. macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
  27. debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
  28. addr[0] = (u8)(macid_hi & 0xff);
  29. addr[1] = (u8)((macid_hi >> 8) & 0xff);
  30. addr[2] = (u8)((macid_hi >> 16) & 0xff);
  31. addr[3] = (u8)((macid_hi >> 24) & 0xff);
  32. addr[4] = (u8)(macid_lo & 0xff);
  33. addr[5] = (u8)((macid_lo >> 8) & 0xff);
  34. }
  35. static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
  36. {
  37. u32 macid_hi, macid_lo;
  38. ulong start;
  39. macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
  40. macid_lo = addr[4] + (addr[5] << 8);
  41. writel(macid_hi, &mac_regs->mac_adr[0].high);
  42. writel(macid_lo, &mac_regs->mac_adr[0].low);
  43. writel(0xfffe, &mac_regs->addr_mask);
  44. start = get_timer(0);
  45. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  46. if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
  47. return 0;
  48. udelay(10);
  49. }
  50. return -ETIME;
  51. }
  52. static int pch_gbe_reset(struct udevice *dev)
  53. {
  54. struct pch_gbe_priv *priv = dev_get_priv(dev);
  55. struct eth_pdata *plat = dev_get_platdata(dev);
  56. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  57. ulong start;
  58. priv->rx_idx = 0;
  59. priv->tx_idx = 0;
  60. writel(PCH_GBE_ALL_RST, &mac_regs->reset);
  61. /*
  62. * Configure the MAC to RGMII mode after reset
  63. *
  64. * For some unknown reason, we must do the configuration here right
  65. * after resetting the whole MAC, otherwise the reset bit in the RESET
  66. * register will never be cleared by the hardware. And there is another
  67. * way of having the same magic, that is to configure the MODE register
  68. * to have the MAC work in MII/GMII mode, which is how current Linux
  69. * pch_gbe driver does. Since anyway we need program the MAC to RGMII
  70. * mode in the driver, we just do it here.
  71. *
  72. * Note: this behavior is not documented in the hardware manual.
  73. */
  74. writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
  75. &mac_regs->rgmii_ctrl);
  76. start = get_timer(0);
  77. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  78. if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
  79. /*
  80. * Soft reset clears hardware MAC address registers,
  81. * so we have to reload MAC address here in order to
  82. * make linux pch_gbe driver happy.
  83. */
  84. return pch_gbe_mac_write(mac_regs, plat->enetaddr);
  85. }
  86. udelay(10);
  87. }
  88. debug("pch_gbe: reset timeout\n");
  89. return -ETIME;
  90. }
  91. static void pch_gbe_rx_descs_init(struct udevice *dev)
  92. {
  93. struct pch_gbe_priv *priv = dev_get_priv(dev);
  94. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  95. struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
  96. int i;
  97. memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
  98. for (i = 0; i < PCH_GBE_DESC_NUM; i++)
  99. rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf,
  100. (u32)(priv->rx_buff[i]));
  101. writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc),
  102. &mac_regs->rx_dsc_base);
  103. writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
  104. &mac_regs->rx_dsc_size);
  105. writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)),
  106. &mac_regs->rx_dsc_sw_p);
  107. }
  108. static void pch_gbe_tx_descs_init(struct udevice *dev)
  109. {
  110. struct pch_gbe_priv *priv = dev_get_priv(dev);
  111. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  112. struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
  113. memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
  114. writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc),
  115. &mac_regs->tx_dsc_base);
  116. writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
  117. &mac_regs->tx_dsc_size);
  118. writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)),
  119. &mac_regs->tx_dsc_sw_p);
  120. }
  121. static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
  122. struct phy_device *phydev)
  123. {
  124. if (!phydev->link) {
  125. printf("%s: No link.\n", phydev->dev->name);
  126. return;
  127. }
  128. clrbits_le32(&mac_regs->rgmii_ctrl,
  129. PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
  130. clrbits_le32(&mac_regs->mode,
  131. PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
  132. switch (phydev->speed) {
  133. case 1000:
  134. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
  135. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
  136. break;
  137. case 100:
  138. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
  139. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
  140. break;
  141. case 10:
  142. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
  143. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
  144. break;
  145. }
  146. if (phydev->duplex) {
  147. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
  148. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
  149. }
  150. printf("Speed: %d, %s duplex\n", phydev->speed,
  151. (phydev->duplex) ? "full" : "half");
  152. return;
  153. }
  154. static int pch_gbe_start(struct udevice *dev)
  155. {
  156. struct pch_gbe_priv *priv = dev_get_priv(dev);
  157. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  158. if (pch_gbe_reset(dev))
  159. return -1;
  160. pch_gbe_rx_descs_init(dev);
  161. pch_gbe_tx_descs_init(dev);
  162. /* Enable frame bursting */
  163. writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
  164. /* Disable TCP/IP accelerator */
  165. writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
  166. /* Disable RX flow control */
  167. writel(0, &mac_regs->rx_fctrl);
  168. /* Configure RX/TX mode */
  169. writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
  170. PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
  171. writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
  172. PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
  173. PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
  174. /* Start up the PHY */
  175. if (phy_startup(priv->phydev)) {
  176. printf("Could not initialize PHY %s\n",
  177. priv->phydev->dev->name);
  178. return -1;
  179. }
  180. pch_gbe_adjust_link(mac_regs, priv->phydev);
  181. if (!priv->phydev->link)
  182. return -1;
  183. /* Enable TX & RX */
  184. writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
  185. writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
  186. return 0;
  187. }
  188. static void pch_gbe_stop(struct udevice *dev)
  189. {
  190. struct pch_gbe_priv *priv = dev_get_priv(dev);
  191. pch_gbe_reset(dev);
  192. phy_shutdown(priv->phydev);
  193. }
  194. static int pch_gbe_send(struct udevice *dev, void *packet, int length)
  195. {
  196. struct pch_gbe_priv *priv = dev_get_priv(dev);
  197. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  198. struct pch_gbe_tx_desc *tx_head, *tx_desc;
  199. u16 frame_ctrl = 0;
  200. u32 int_st;
  201. ulong start;
  202. tx_head = &priv->tx_desc[0];
  203. tx_desc = &priv->tx_desc[priv->tx_idx];
  204. if (length < 64)
  205. frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
  206. tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet);
  207. tx_desc->length = length;
  208. tx_desc->tx_words_eob = length + 3;
  209. tx_desc->tx_frame_ctrl = frame_ctrl;
  210. tx_desc->dma_status = 0;
  211. tx_desc->gbec_status = 0;
  212. /* Test the wrap-around condition */
  213. if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
  214. priv->tx_idx = 0;
  215. writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)),
  216. &mac_regs->tx_dsc_sw_p);
  217. start = get_timer(0);
  218. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  219. int_st = readl(&mac_regs->int_st);
  220. if (int_st & PCH_GBE_INT_TX_CMPLT)
  221. return 0;
  222. udelay(10);
  223. }
  224. debug("pch_gbe: sent failed\n");
  225. return -ETIME;
  226. }
  227. static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
  228. {
  229. struct pch_gbe_priv *priv = dev_get_priv(dev);
  230. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  231. struct pch_gbe_rx_desc *rx_desc;
  232. u32 hw_desc, buffer_addr, length;
  233. rx_desc = &priv->rx_desc[priv->rx_idx];
  234. readl(&mac_regs->int_st);
  235. hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
  236. /* Just return if not receiving any packet */
  237. if ((u32)rx_desc == hw_desc)
  238. return -EAGAIN;
  239. buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr);
  240. *packetp = (uchar *)buffer_addr;
  241. length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
  242. return length;
  243. }
  244. static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
  245. {
  246. struct pch_gbe_priv *priv = dev_get_priv(dev);
  247. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  248. struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
  249. int rx_swp;
  250. /* Test the wrap-around condition */
  251. if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
  252. priv->rx_idx = 0;
  253. rx_swp = priv->rx_idx;
  254. if (++rx_swp >= PCH_GBE_DESC_NUM)
  255. rx_swp = 0;
  256. writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)),
  257. &mac_regs->rx_dsc_sw_p);
  258. return 0;
  259. }
  260. static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
  261. {
  262. ulong start = get_timer(0);
  263. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  264. if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
  265. return 0;
  266. udelay(10);
  267. }
  268. return -ETIME;
  269. }
  270. static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  271. {
  272. struct pch_gbe_regs *mac_regs = bus->priv;
  273. u32 miim;
  274. if (pch_gbe_mdio_ready(mac_regs))
  275. return -ETIME;
  276. miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
  277. (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
  278. PCH_GBE_MIIM_OPER_READ;
  279. writel(miim, &mac_regs->miim);
  280. if (pch_gbe_mdio_ready(mac_regs))
  281. return -ETIME;
  282. return readl(&mac_regs->miim) & 0xffff;
  283. }
  284. static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
  285. int reg, u16 val)
  286. {
  287. struct pch_gbe_regs *mac_regs = bus->priv;
  288. u32 miim;
  289. if (pch_gbe_mdio_ready(mac_regs))
  290. return -ETIME;
  291. miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
  292. (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
  293. PCH_GBE_MIIM_OPER_WRITE | val;
  294. writel(miim, &mac_regs->miim);
  295. if (pch_gbe_mdio_ready(mac_regs))
  296. return -ETIME;
  297. else
  298. return 0;
  299. }
  300. static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
  301. {
  302. struct mii_dev *bus;
  303. bus = mdio_alloc();
  304. if (!bus) {
  305. debug("pch_gbe: failed to allocate MDIO bus\n");
  306. return -ENOMEM;
  307. }
  308. bus->read = pch_gbe_mdio_read;
  309. bus->write = pch_gbe_mdio_write;
  310. strcpy(bus->name, name);
  311. bus->priv = (void *)mac_regs;
  312. return mdio_register(bus);
  313. }
  314. static int pch_gbe_phy_init(struct udevice *dev)
  315. {
  316. struct pch_gbe_priv *priv = dev_get_priv(dev);
  317. struct eth_pdata *plat = dev_get_platdata(dev);
  318. struct phy_device *phydev;
  319. int mask = 0xffffffff;
  320. phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
  321. if (!phydev) {
  322. printf("pch_gbe: cannot find the phy\n");
  323. return -1;
  324. }
  325. phy_connect_dev(phydev, dev);
  326. phydev->supported &= PHY_GBIT_FEATURES;
  327. phydev->advertising = phydev->supported;
  328. priv->phydev = phydev;
  329. phy_config(phydev);
  330. return 0;
  331. }
  332. int pch_gbe_probe(struct udevice *dev)
  333. {
  334. struct pch_gbe_priv *priv;
  335. struct eth_pdata *plat = dev_get_platdata(dev);
  336. pci_dev_t devno;
  337. u32 iobase;
  338. devno = dm_pci_get_bdf(dev);
  339. /*
  340. * The priv structure contains the descriptors and frame buffers which
  341. * need a strict buswidth alignment (64 bytes). This is guaranteed by
  342. * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
  343. */
  344. priv = dev_get_priv(dev);
  345. priv->bdf = devno;
  346. pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
  347. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  348. iobase = pci_mem_to_phys(devno, iobase);
  349. plat->iobase = iobase;
  350. priv->mac_regs = (struct pch_gbe_regs *)iobase;
  351. /* Read MAC address from SROM and initialize dev->enetaddr with it */
  352. pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
  353. plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
  354. pch_gbe_mdio_init(dev->name, priv->mac_regs);
  355. priv->bus = miiphy_get_dev_by_name(dev->name);
  356. return pch_gbe_phy_init(dev);
  357. }
  358. int pch_gbe_remove(struct udevice *dev)
  359. {
  360. struct pch_gbe_priv *priv = dev_get_priv(dev);
  361. free(priv->phydev);
  362. mdio_unregister(priv->bus);
  363. mdio_free(priv->bus);
  364. return 0;
  365. }
  366. static const struct eth_ops pch_gbe_ops = {
  367. .start = pch_gbe_start,
  368. .send = pch_gbe_send,
  369. .recv = pch_gbe_recv,
  370. .free_pkt = pch_gbe_free_pkt,
  371. .stop = pch_gbe_stop,
  372. };
  373. static const struct udevice_id pch_gbe_ids[] = {
  374. { .compatible = "intel,pch-gbe" },
  375. { }
  376. };
  377. U_BOOT_DRIVER(eth_pch_gbe) = {
  378. .name = "pch_gbe",
  379. .id = UCLASS_ETH,
  380. .of_match = pch_gbe_ids,
  381. .probe = pch_gbe_probe,
  382. .remove = pch_gbe_remove,
  383. .ops = &pch_gbe_ops,
  384. .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
  385. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  386. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  387. };
  388. U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);