mpc512x_fec.c 17 KB

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  1. /*
  2. * (C) Copyright 2003-2010
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Derived from the MPC8xx FEC driver.
  6. * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <miiphy.h>
  13. #include <asm/io.h>
  14. #include "mpc512x_fec.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define DEBUG 0
  17. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  18. #error "CONFIG_MII has to be defined!"
  19. #endif
  20. int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
  21. int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data);
  22. int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
  23. static uchar rx_buff[FEC_BUFFER_SIZE];
  24. static int rx_buff_idx = 0;
  25. /********************************************************************/
  26. #if (DEBUG & 0x2)
  27. static void mpc512x_fec_phydump (char *devname)
  28. {
  29. u16 phyStatus, i;
  30. u8 phyAddr = CONFIG_PHY_ADDR;
  31. u8 reg_mask[] = {
  32. /* regs to print: 0...8, 21,27,31 */
  33. 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
  34. 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
  35. };
  36. for (i = 0; i < 32; i++) {
  37. if (reg_mask[i]) {
  38. miiphy_read (devname, phyAddr, i, &phyStatus);
  39. printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
  40. }
  41. }
  42. }
  43. #endif
  44. /********************************************************************/
  45. static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
  46. {
  47. int ix;
  48. /*
  49. * Receive BDs init
  50. */
  51. for (ix = 0; ix < FEC_RBD_NUM; ix++) {
  52. fec->bdBase->rbd[ix].dataPointer =
  53. (u32)&fec->bdBase->recv_frames[ix];
  54. fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
  55. fec->bdBase->rbd[ix].dataLength = 0;
  56. }
  57. /*
  58. * have the last RBD to close the ring
  59. */
  60. fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
  61. fec->rbdIndex = 0;
  62. /*
  63. * Trasmit BDs init
  64. */
  65. for (ix = 0; ix < FEC_TBD_NUM; ix++) {
  66. fec->bdBase->tbd[ix].status = 0;
  67. }
  68. /*
  69. * Have the last TBD to close the ring
  70. */
  71. fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
  72. /*
  73. * Initialize some indices
  74. */
  75. fec->tbdIndex = 0;
  76. fec->usedTbdIndex = 0;
  77. fec->cleanTbdNum = FEC_TBD_NUM;
  78. return 0;
  79. }
  80. /********************************************************************/
  81. static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
  82. {
  83. /*
  84. * Reset buffer descriptor as empty
  85. */
  86. if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
  87. pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
  88. else
  89. pRbd->status = FEC_RBD_EMPTY;
  90. pRbd->dataLength = 0;
  91. /*
  92. * Increment BD count
  93. */
  94. fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
  95. /*
  96. * Now, we have an empty RxBD, notify FEC
  97. * Set Descriptor polling active
  98. */
  99. out_be32(&fec->eth->r_des_active, 0x01000000);
  100. }
  101. /********************************************************************/
  102. static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
  103. {
  104. volatile FEC_TBD *pUsedTbd;
  105. #if (DEBUG & 0x1)
  106. printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
  107. fec->cleanTbdNum, fec->usedTbdIndex);
  108. #endif
  109. /*
  110. * process all the consumed TBDs
  111. */
  112. while (fec->cleanTbdNum < FEC_TBD_NUM) {
  113. pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
  114. if (pUsedTbd->status & FEC_TBD_READY) {
  115. #if (DEBUG & 0x20)
  116. printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
  117. #endif
  118. return;
  119. }
  120. /*
  121. * clean this buffer descriptor
  122. */
  123. if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
  124. pUsedTbd->status = FEC_TBD_WRAP;
  125. else
  126. pUsedTbd->status = 0;
  127. /*
  128. * update some indeces for a correct handling of the TBD ring
  129. */
  130. fec->cleanTbdNum++;
  131. fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
  132. }
  133. }
  134. /********************************************************************/
  135. static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
  136. {
  137. u8 currByte; /* byte for which to compute the CRC */
  138. int byte; /* loop - counter */
  139. int bit; /* loop - counter */
  140. u32 crc = 0xffffffff; /* initial value */
  141. /*
  142. * The algorithm used is the following:
  143. * we loop on each of the six bytes of the provided address,
  144. * and we compute the CRC by left-shifting the previous
  145. * value by one position, so that each bit in the current
  146. * byte of the address may contribute the calculation. If
  147. * the latter and the MSB in the CRC are different, then
  148. * the CRC value so computed is also ex-ored with the
  149. * "polynomium generator". The current byte of the address
  150. * is also shifted right by one bit at each iteration.
  151. * This is because the CRC generatore in hardware is implemented
  152. * as a shift-register with as many ex-ores as the radixes
  153. * in the polynomium. This suggests that we represent the
  154. * polynomiumm itself as a 32-bit constant.
  155. */
  156. for (byte = 0; byte < 6; byte++) {
  157. currByte = mac[byte];
  158. for (bit = 0; bit < 8; bit++) {
  159. if ((currByte & 0x01) ^ (crc & 0x01)) {
  160. crc >>= 1;
  161. crc = crc ^ 0xedb88320;
  162. } else {
  163. crc >>= 1;
  164. }
  165. currByte >>= 1;
  166. }
  167. }
  168. crc = crc >> 26;
  169. /*
  170. * Set individual hash table register
  171. */
  172. if (crc >= 32) {
  173. out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
  174. out_be32(&fec->eth->iaddr2, 0);
  175. } else {
  176. out_be32(&fec->eth->iaddr1, 0);
  177. out_be32(&fec->eth->iaddr2, (1 << crc));
  178. }
  179. /*
  180. * Set physical address
  181. */
  182. out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
  183. (mac[2] << 8) + mac[3]);
  184. out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
  185. 0x8808);
  186. }
  187. /********************************************************************/
  188. static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
  189. {
  190. mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
  191. #if (DEBUG & 0x1)
  192. printf ("mpc512x_fec_init... Begin\n");
  193. #endif
  194. mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
  195. out_be32(&fec->eth->gaddr1, 0x00000000);
  196. out_be32(&fec->eth->gaddr2, 0x00000000);
  197. mpc512x_fec_init_phy (dev, bis);
  198. /* Set interrupt mask register */
  199. out_be32(&fec->eth->imask, 0x00000000);
  200. /* Clear FEC-Lite interrupt event register(IEVENT) */
  201. out_be32(&fec->eth->ievent, 0xffffffff);
  202. /* Set transmit fifo watermark register(X_WMRK), default = 64 */
  203. out_be32(&fec->eth->x_wmrk, 0x0);
  204. /* Set Opcode/Pause Duration Register */
  205. out_be32(&fec->eth->op_pause, 0x00010020);
  206. /* Frame length=1522; MII mode */
  207. out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
  208. /* Half-duplex, heartbeat disabled */
  209. out_be32(&fec->eth->x_cntrl, 0x00000000);
  210. /* Enable MIB counters */
  211. out_be32(&fec->eth->mib_control, 0x0);
  212. /* Setup recv fifo start and buff size */
  213. out_be32(&fec->eth->r_fstart, 0x500);
  214. out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
  215. /* Setup BD base addresses */
  216. out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
  217. out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
  218. /* DMA Control */
  219. out_be32(&fec->eth->dma_control, 0xc0000000);
  220. /* Enable FEC */
  221. setbits_be32(&fec->eth->ecntrl, 0x00000006);
  222. /* Initilize addresses and status words of BDs */
  223. mpc512x_fec_bd_init (fec);
  224. /* Descriptor polling active */
  225. out_be32(&fec->eth->r_des_active, 0x01000000);
  226. #if (DEBUG & 0x1)
  227. printf("mpc512x_fec_init... Done \n");
  228. #endif
  229. return 1;
  230. }
  231. /********************************************************************/
  232. int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
  233. {
  234. mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
  235. const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
  236. int timeout = 1;
  237. u16 phyStatus;
  238. #if (DEBUG & 0x1)
  239. printf ("mpc512x_fec_init_phy... Begin\n");
  240. #endif
  241. /*
  242. * Clear FEC-Lite interrupt event register(IEVENT)
  243. */
  244. out_be32(&fec->eth->ievent, 0xffffffff);
  245. /*
  246. * Set interrupt mask register
  247. */
  248. out_be32(&fec->eth->imask, 0x00000000);
  249. if (fec->xcv_type != SEVENWIRE) {
  250. /*
  251. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  252. * and do not drop the Preamble.
  253. */
  254. out_be32(&fec->eth->mii_speed,
  255. (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
  256. /*
  257. * Reset PHY, then delay 300ns
  258. */
  259. miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
  260. udelay (1000);
  261. if (fec->xcv_type == MII10) {
  262. /*
  263. * Force 10Base-T, FDX operation
  264. */
  265. #if (DEBUG & 0x2)
  266. printf ("Forcing 10 Mbps ethernet link... ");
  267. #endif
  268. miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
  269. miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
  270. timeout = 20;
  271. do { /* wait for link status to go down */
  272. udelay (10000);
  273. if ((timeout--) == 0) {
  274. #if (DEBUG & 0x2)
  275. printf ("hmmm, should not have waited...");
  276. #endif
  277. break;
  278. }
  279. miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
  280. #if (DEBUG & 0x2)
  281. printf ("=");
  282. #endif
  283. } while ((phyStatus & 0x0004)); /* !link up */
  284. timeout = 1000;
  285. do { /* wait for link status to come back up */
  286. udelay (10000);
  287. if ((timeout--) == 0) {
  288. printf ("failed. Link is down.\n");
  289. break;
  290. }
  291. miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
  292. #if (DEBUG & 0x2)
  293. printf ("+");
  294. #endif
  295. } while (!(phyStatus & 0x0004)); /* !link up */
  296. #if (DEBUG & 0x2)
  297. printf ("done.\n");
  298. #endif
  299. } else { /* MII100 */
  300. /*
  301. * Set the auto-negotiation advertisement register bits
  302. */
  303. miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
  304. /*
  305. * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
  306. */
  307. miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
  308. /*
  309. * Wait for AN completion
  310. */
  311. timeout = 2500;
  312. do {
  313. udelay (1000);
  314. if ((timeout--) == 0) {
  315. #if (DEBUG & 0x2)
  316. printf ("PHY auto neg 0 failed...\n");
  317. #endif
  318. return -1;
  319. }
  320. if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
  321. #if (DEBUG & 0x2)
  322. printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
  323. #endif
  324. return -1;
  325. }
  326. } while (!(phyStatus & 0x0004));
  327. #if (DEBUG & 0x2)
  328. printf ("PHY auto neg complete! \n");
  329. #endif
  330. }
  331. }
  332. #if (DEBUG & 0x2)
  333. if (fec->xcv_type != SEVENWIRE)
  334. mpc512x_fec_phydump (dev->name);
  335. #endif
  336. #if (DEBUG & 0x1)
  337. printf ("mpc512x_fec_init_phy... Done \n");
  338. #endif
  339. return 1;
  340. }
  341. /********************************************************************/
  342. static void mpc512x_fec_halt (struct eth_device *dev)
  343. {
  344. mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
  345. int counter = 0xffff;
  346. #if (DEBUG & 0x2)
  347. if (fec->xcv_type != SEVENWIRE)
  348. mpc512x_fec_phydump (dev->name);
  349. #endif
  350. /*
  351. * mask FEC chip interrupts
  352. */
  353. out_be32(&fec->eth->imask, 0);
  354. /*
  355. * issue graceful stop command to the FEC transmitter if necessary
  356. */
  357. setbits_be32(&fec->eth->x_cntrl, 0x00000001);
  358. /*
  359. * wait for graceful stop to register
  360. */
  361. while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
  362. ;
  363. /*
  364. * Disable the Ethernet Controller
  365. */
  366. clrbits_be32(&fec->eth->ecntrl, 0x00000002);
  367. /*
  368. * Issue a reset command to the FEC chip
  369. */
  370. setbits_be32(&fec->eth->ecntrl, 0x1);
  371. /*
  372. * wait at least 16 clock cycles
  373. */
  374. udelay (10);
  375. #if (DEBUG & 0x3)
  376. printf ("Ethernet task stopped\n");
  377. #endif
  378. }
  379. /********************************************************************/
  380. static int mpc512x_fec_send(struct eth_device *dev, void *eth_data,
  381. int data_length)
  382. {
  383. /*
  384. * This routine transmits one frame. This routine only accepts
  385. * 6-byte Ethernet addresses.
  386. */
  387. mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
  388. volatile FEC_TBD *pTbd;
  389. #if (DEBUG & 0x20)
  390. printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
  391. #endif
  392. /*
  393. * Clear Tx BD ring at first
  394. */
  395. mpc512x_fec_tbd_scrub (fec);
  396. /*
  397. * Check for valid length of data.
  398. */
  399. if ((data_length > 1500) || (data_length <= 0)) {
  400. return -1;
  401. }
  402. /*
  403. * Check the number of vacant TxBDs.
  404. */
  405. if (fec->cleanTbdNum < 1) {
  406. #if (DEBUG & 0x20)
  407. printf ("No available TxBDs ...\n");
  408. #endif
  409. return -1;
  410. }
  411. /*
  412. * Get the first TxBD to send the mac header
  413. */
  414. pTbd = &fec->bdBase->tbd[fec->tbdIndex];
  415. pTbd->dataLength = data_length;
  416. pTbd->dataPointer = (u32)eth_data;
  417. pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  418. fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
  419. /* Activate transmit Buffer Descriptor polling */
  420. out_be32(&fec->eth->x_des_active, 0x01000000);
  421. #if (DEBUG & 0x8)
  422. printf ( "+" );
  423. #endif
  424. fec->cleanTbdNum -= 1;
  425. /*
  426. * wait until frame is sent .
  427. */
  428. while (pTbd->status & FEC_TBD_READY) {
  429. udelay (10);
  430. #if (DEBUG & 0x8)
  431. printf ("TDB status = %04x\n", pTbd->status);
  432. #endif
  433. }
  434. return 0;
  435. }
  436. /********************************************************************/
  437. static int mpc512x_fec_recv (struct eth_device *dev)
  438. {
  439. /*
  440. * This command pulls one frame from the card
  441. */
  442. mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
  443. volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
  444. unsigned long ievent;
  445. int frame_length = 0;
  446. #if (DEBUG & 0x1)
  447. printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
  448. #endif
  449. #if (DEBUG & 0x8)
  450. printf( "-" );
  451. #endif
  452. /*
  453. * Check if any critical events have happened
  454. */
  455. ievent = in_be32(&fec->eth->ievent);
  456. out_be32(&fec->eth->ievent, ievent);
  457. if (ievent & 0x20060000) {
  458. /* BABT, Rx/Tx FIFO errors */
  459. mpc512x_fec_halt (dev);
  460. mpc512x_fec_init (dev, NULL);
  461. return 0;
  462. }
  463. if (ievent & 0x80000000) {
  464. /* Heartbeat error */
  465. setbits_be32(&fec->eth->x_cntrl, 0x00000001);
  466. }
  467. if (ievent & 0x10000000) {
  468. /* Graceful stop complete */
  469. if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
  470. mpc512x_fec_halt (dev);
  471. clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
  472. mpc512x_fec_init (dev, NULL);
  473. }
  474. }
  475. if (!(pRbd->status & FEC_RBD_EMPTY)) {
  476. if (!(pRbd->status & FEC_RBD_ERR) &&
  477. ((pRbd->dataLength - 4) > 14)) {
  478. /*
  479. * Get buffer size
  480. */
  481. if (pRbd->status & FEC_RBD_LAST)
  482. frame_length = pRbd->dataLength - 4;
  483. else
  484. frame_length = pRbd->dataLength;
  485. #if (DEBUG & 0x20)
  486. {
  487. int i;
  488. printf ("recv data length 0x%08x data hdr: ",
  489. pRbd->dataLength);
  490. for (i = 0; i < 14; i++)
  491. printf ("%x ", *((u8*)pRbd->dataPointer + i));
  492. printf("\n");
  493. }
  494. #endif
  495. /*
  496. * Fill the buffer and pass it to upper layers
  497. */
  498. memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
  499. frame_length - rx_buff_idx);
  500. rx_buff_idx = frame_length;
  501. if (pRbd->status & FEC_RBD_LAST) {
  502. net_process_received_packet((uchar *)rx_buff,
  503. frame_length);
  504. rx_buff_idx = 0;
  505. }
  506. }
  507. /*
  508. * Reset buffer descriptor as empty
  509. */
  510. mpc512x_fec_rbd_clean (fec, pRbd);
  511. }
  512. /* Try to fill Buffer Descriptors */
  513. out_be32(&fec->eth->r_des_active, 0x01000000);
  514. return frame_length;
  515. }
  516. /********************************************************************/
  517. int mpc512x_fec_initialize (bd_t * bis)
  518. {
  519. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  520. mpc512x_fec_priv *fec;
  521. struct eth_device *dev;
  522. void * bd;
  523. fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
  524. dev = (struct eth_device *) malloc (sizeof(*dev));
  525. memset (dev, 0, sizeof *dev);
  526. fec->eth = &im->fec;
  527. # ifndef CONFIG_FEC_10MBIT
  528. fec->xcv_type = MII100;
  529. # else
  530. fec->xcv_type = MII10;
  531. # endif
  532. dev->priv = (void *)fec;
  533. dev->iobase = (int)&im->fec;
  534. dev->init = mpc512x_fec_init;
  535. dev->halt = mpc512x_fec_halt;
  536. dev->send = mpc512x_fec_send;
  537. dev->recv = mpc512x_fec_recv;
  538. strcpy(dev->name, "FEC");
  539. eth_register (dev);
  540. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  541. miiphy_register (dev->name,
  542. fec512x_miiphy_read, fec512x_miiphy_write);
  543. #endif
  544. /* Clean up space FEC's MIB and FIFO RAM ...*/
  545. memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
  546. memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
  547. /*
  548. * Malloc space for BDs (must be quad word-aligned)
  549. * this pointer is lost, so cannot be freed
  550. */
  551. bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
  552. fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
  553. memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
  554. /*
  555. * Set interrupt mask register
  556. */
  557. out_be32(&fec->eth->imask, 0x00000000);
  558. /*
  559. * Clear FEC-Lite interrupt event register(IEVENT)
  560. */
  561. out_be32(&fec->eth->ievent, 0xffffffff);
  562. return 1;
  563. }
  564. /* MII-interface related functions */
  565. /********************************************************************/
  566. int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal)
  567. {
  568. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  569. volatile fec512x_t *eth = &im->fec;
  570. u32 reg; /* convenient holder for the PHY register */
  571. u32 phy; /* convenient holder for the PHY */
  572. int timeout = 0xffff;
  573. /*
  574. * reading from any PHY's register is done by properly
  575. * programming the FEC's MII data register.
  576. */
  577. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  578. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  579. out_be32(&eth->mii_data, FEC_MII_DATA_ST |
  580. FEC_MII_DATA_OP_RD |
  581. FEC_MII_DATA_TA |
  582. phy | reg);
  583. /*
  584. * wait for the related interrupt
  585. */
  586. while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
  587. ;
  588. if (timeout == 0) {
  589. #if (DEBUG & 0x2)
  590. printf ("Read MDIO failed...\n");
  591. #endif
  592. return -1;
  593. }
  594. /*
  595. * clear mii interrupt bit
  596. */
  597. out_be32(&eth->ievent, 0x00800000);
  598. /*
  599. * it's now safe to read the PHY's register
  600. */
  601. *retVal = (u16) in_be32(&eth->mii_data);
  602. return 0;
  603. }
  604. /********************************************************************/
  605. int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data)
  606. {
  607. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  608. volatile fec512x_t *eth = &im->fec;
  609. u32 reg; /* convenient holder for the PHY register */
  610. u32 phy; /* convenient holder for the PHY */
  611. int timeout = 0xffff;
  612. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  613. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  614. out_be32(&eth->mii_data, FEC_MII_DATA_ST |
  615. FEC_MII_DATA_OP_WR |
  616. FEC_MII_DATA_TA |
  617. phy | reg | data);
  618. /*
  619. * wait for the MII interrupt
  620. */
  621. while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
  622. ;
  623. if (timeout == 0) {
  624. #if (DEBUG & 0x2)
  625. printf ("Write MDIO failed...\n");
  626. #endif
  627. return -1;
  628. }
  629. /*
  630. * clear MII interrupt bit
  631. */
  632. out_be32(&eth->ievent, 0x00800000);
  633. return 0;
  634. }