lpc32xx_eth.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652
  1. /*
  2. * LPC32xx Ethernet MAC interface driver
  3. *
  4. * (C) Copyright 2014 DENX Software Engineering GmbH
  5. * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <net.h>
  11. #include <malloc.h>
  12. #include <miiphy.h>
  13. #include <asm/io.h>
  14. #include <asm/errno.h>
  15. #include <asm/types.h>
  16. #include <asm/system.h>
  17. #include <asm/byteorder.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/config.h>
  20. /*
  21. * Notes:
  22. *
  23. * 1. Unless specified otherwise, all references to tables or paragraphs
  24. * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
  25. *
  26. * 2. Only bitfield masks/values which are actually used by the driver
  27. * are defined.
  28. */
  29. /* a single RX descriptor. The controller has an array of these */
  30. struct lpc32xx_eth_rxdesc {
  31. u32 packet; /* Receive packet pointer */
  32. u32 control; /* Descriptor command status */
  33. };
  34. #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
  35. /* RX control bitfields/masks (see Table 330) */
  36. #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
  37. #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
  38. #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
  39. /* a single RX status. The controller has an array of these */
  40. struct lpc32xx_eth_rxstat {
  41. u32 statusinfo; /* Transmit Descriptor status */
  42. u32 statushashcrc; /* Transmit Descriptor CRCs */
  43. };
  44. #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
  45. /* RX statusinfo bitfields/masks (see Table 333) */
  46. #define RX_STAT_RXSIZE 0x000007FF
  47. /* Helper: OR of all errors except RANGE */
  48. #define RX_STAT_ERRORS 0x1B800000
  49. /* a single TX descriptor. The controller has an array of these */
  50. struct lpc32xx_eth_txdesc {
  51. u32 packet; /* Transmit packet pointer */
  52. u32 control; /* Descriptor control */
  53. };
  54. #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
  55. /* TX control bitfields/masks (see Table 335) */
  56. #define TX_CTRL_TXSIZE 0x000007FF
  57. #define TX_CTRL_LAST 0x40000000
  58. /* a single TX status. The controller has an array of these */
  59. struct lpc32xx_eth_txstat {
  60. u32 statusinfo; /* Transmit Descriptor status */
  61. };
  62. #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
  63. /* Ethernet MAC interface registers (see Table 283) */
  64. struct lpc32xx_eth_registers {
  65. /* MAC registers - 0x3106_0000 to 0x3106_01FC */
  66. u32 mac1; /* MAC configuration register 1 */
  67. u32 mac2; /* MAC configuration register 2 */
  68. u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
  69. u32 ipgr; /* Non-back-to-back IPG register */
  70. u32 clrt; /* Collision Window / Retry register */
  71. u32 maxf; /* Maximum Frame register */
  72. u32 supp; /* Phy Support register */
  73. u32 test;
  74. u32 mcfg; /* MII management configuration reg. */
  75. u32 mcmd; /* MII management command register */
  76. u32 madr; /* MII management address register */
  77. u32 mwtd; /* MII management wite data register */
  78. u32 mrdd; /* MII management read data register */
  79. u32 mind; /* MII management indicators register */
  80. u32 reserved1[2];
  81. u32 sa0; /* Station address register 0 */
  82. u32 sa1; /* Station address register 1 */
  83. u32 sa2; /* Station address register 2 */
  84. u32 reserved2[45];
  85. /* Control registers */
  86. u32 command;
  87. u32 status;
  88. u32 rxdescriptor;
  89. u32 rxstatus;
  90. u32 rxdescriptornumber; /* actually, number MINUS ONE */
  91. u32 rxproduceindex; /* head of rx desc fifo */
  92. u32 rxconsumeindex; /* tail of rx desc fifo */
  93. u32 txdescriptor;
  94. u32 txstatus;
  95. u32 txdescriptornumber; /* actually, number MINUS ONE */
  96. u32 txproduceindex; /* head of rx desc fifo */
  97. u32 txconsumeindex; /* tail of rx desc fifo */
  98. u32 reserved3[10];
  99. u32 tsv0; /* Transmit status vector register 0 */
  100. u32 tsv1; /* Transmit status vector register 1 */
  101. u32 rsv; /* Receive status vector register */
  102. u32 reserved4[3];
  103. u32 flowcontrolcounter;
  104. u32 flowcontrolstatus;
  105. u32 reserved5[34];
  106. /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
  107. u32 rxfilterctrl;
  108. u32 rxfilterwolstatus;
  109. u32 rxfilterwolclear;
  110. u32 reserved6;
  111. u32 hashfilterl;
  112. u32 hashfilterh;
  113. u32 reserved7[882];
  114. /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
  115. u32 intstatus; /* Interrupt status register */
  116. u32 intenable;
  117. u32 intclear;
  118. u32 intset;
  119. u32 reserved8;
  120. u32 powerdown;
  121. u32 reserved9;
  122. };
  123. /* MAC1 register bitfields/masks and offsets (see Table 283) */
  124. #define MAC1_RECV_ENABLE 0x00000001
  125. #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
  126. #define MAC1_SOFT_RESET 0x00008000
  127. /* Helper: general reset */
  128. #define MAC1_RESETS 0x0000CF00
  129. /* MAC2 register bitfields/masks and offsets (see Table 284) */
  130. #define MAC2_FULL_DUPLEX 0x00000001
  131. #define MAC2_CRC_ENABLE 0x00000010
  132. #define MAC2_PAD_CRC_ENABLE 0x00000020
  133. /* SUPP register bitfields/masks and offsets (see Table 290) */
  134. #define SUPP_SPEED 0x00000100
  135. /* MCFG register bitfields/masks and offsets (see Table 292) */
  136. #define MCFG_RESET_MII_MGMT 0x00008000
  137. /* divide clock by 28 (see Table 293) */
  138. #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
  139. /* MADR register bitfields/masks and offsets (see Table 295) */
  140. #define MADR_REG_MASK 0x0000001F
  141. #define MADR_PHY_MASK 0x00001F00
  142. #define MADR_REG_OFFSET 0
  143. #define MADR_PHY_OFFSET 8
  144. /* MIND register bitfields/masks (see Table 298) */
  145. #define MIND_BUSY 0x00000001
  146. /* COMMAND register bitfields/masks and offsets (see Table 283) */
  147. #define COMMAND_RXENABLE 0x00000001
  148. #define COMMAND_TXENABLE 0x00000002
  149. #define COMMAND_PASSRUNTFRAME 0x00000040
  150. #define COMMAND_RMII 0x00000200
  151. #define COMMAND_FULL_DUPLEX 0x00000400
  152. /* Helper: general reset */
  153. #define COMMAND_RESETS 0x00000038
  154. /* STATUS register bitfields/masks and offsets (see Table 283) */
  155. #define STATUS_RXSTATUS 0x00000001
  156. #define STATUS_TXSTATUS 0x00000002
  157. /* RXFILTERCTRL register bitfields/masks (see Table 319) */
  158. #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
  159. #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
  160. /* Buffers and descriptors */
  161. #define ATTRS(n) __aligned(n)
  162. #define TX_BUF_COUNT 4
  163. #define RX_BUF_COUNT 4
  164. struct lpc32xx_eth_buffers {
  165. ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
  166. ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
  167. ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
  168. ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
  169. ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
  170. ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
  171. };
  172. /* port device data struct */
  173. struct lpc32xx_eth_device {
  174. struct eth_device dev;
  175. struct lpc32xx_eth_registers *regs;
  176. struct lpc32xx_eth_buffers *bufs;
  177. bool phy_rmii;
  178. };
  179. #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
  180. /* generic macros */
  181. #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
  182. /* timeout for MII polling */
  183. #define MII_TIMEOUT 10000000
  184. /* limits for PHY and register addresses */
  185. #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
  186. #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
  187. DECLARE_GLOBAL_DATA_PTR;
  188. #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  189. /*
  190. * mii_reg_read - miiphy_read callback function.
  191. *
  192. * Returns 16bit phy register value, or 0xffff on error
  193. */
  194. static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data)
  195. {
  196. struct eth_device *dev = eth_get_dev_by_name(devname);
  197. struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  198. struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  199. u32 mind_reg;
  200. u32 timeout;
  201. /* check parameters */
  202. if (phy_adr > MII_MAX_PHY) {
  203. printf("%s:%u: Invalid PHY address %d\n",
  204. __func__, __LINE__, phy_adr);
  205. return -EFAULT;
  206. }
  207. if (reg_ofs > MII_MAX_REG) {
  208. printf("%s:%u: Invalid register offset %d\n",
  209. __func__, __LINE__, reg_ofs);
  210. return -EFAULT;
  211. }
  212. /* write the phy and reg addressse into the MII address reg */
  213. writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
  214. &regs->madr);
  215. /* write 1 to the MII command register to cause a read */
  216. writel(1, &regs->mcmd);
  217. /* wait till the MII is not busy */
  218. timeout = MII_TIMEOUT;
  219. do {
  220. /* read MII indicators register */
  221. mind_reg = readl(&regs->mind);
  222. if (--timeout == 0)
  223. break;
  224. } while (mind_reg & MIND_BUSY);
  225. /* write 0 to the MII command register to finish the read */
  226. writel(0, &regs->mcmd);
  227. if (timeout == 0) {
  228. printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
  229. return -EFAULT;
  230. }
  231. *data = (u16) readl(&regs->mrdd);
  232. debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
  233. reg_ofs, *data);
  234. return 0;
  235. }
  236. /*
  237. * mii_reg_write - imiiphy_write callback function.
  238. *
  239. * Returns 0 if write succeed, -EINVAL on bad parameters
  240. * -ETIME on timeout
  241. */
  242. static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
  243. {
  244. struct eth_device *dev = eth_get_dev_by_name(devname);
  245. struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  246. struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  247. u32 mind_reg;
  248. u32 timeout;
  249. /* check parameters */
  250. if (phy_adr > MII_MAX_PHY) {
  251. printf("%s:%u: Invalid PHY address %d\n",
  252. __func__, __LINE__, phy_adr);
  253. return -EFAULT;
  254. }
  255. if (reg_ofs > MII_MAX_REG) {
  256. printf("%s:%u: Invalid register offset %d\n",
  257. __func__, __LINE__, reg_ofs);
  258. return -EFAULT;
  259. }
  260. /* write the phy and reg addressse into the MII address reg */
  261. writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
  262. &regs->madr);
  263. /* write data to the MII write register */
  264. writel(data, &regs->mwtd);
  265. /* wait till the MII is not busy */
  266. timeout = MII_TIMEOUT;
  267. do {
  268. /* read MII indicators register */
  269. mind_reg = readl(&regs->mind);
  270. if (--timeout == 0)
  271. break;
  272. } while (mind_reg & MIND_BUSY);
  273. if (timeout == 0) {
  274. printf("%s:%u: MII busy timeout\n", __func__,
  275. __LINE__);
  276. return -EFAULT;
  277. }
  278. /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
  279. reg_ofs, data);*/
  280. return 0;
  281. }
  282. #endif
  283. #if defined(CONFIG_PHYLIB)
  284. int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
  285. int reg_addr)
  286. {
  287. u16 data;
  288. int ret;
  289. ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data);
  290. if (ret)
  291. return ret;
  292. return data;
  293. }
  294. int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
  295. int reg_addr, u16 data)
  296. {
  297. return mii_reg_write(bus->name, phy_addr, reg_addr, data);
  298. }
  299. #endif
  300. /*
  301. * Provide default Ethernet buffers base address if target did not.
  302. * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
  303. * maximize throughput.
  304. */
  305. #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
  306. #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
  307. #endif
  308. static struct lpc32xx_eth_device lpc32xx_eth = {
  309. .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
  310. .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
  311. #if defined(CONFIG_RMII)
  312. .phy_rmii = true,
  313. #endif
  314. };
  315. #define TX_TIMEOUT 10000
  316. static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
  317. {
  318. struct lpc32xx_eth_device *lpc32xx_eth_device =
  319. container_of(dev, struct lpc32xx_eth_device, dev);
  320. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  321. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  322. int timeout, tx_index;
  323. /* time out if transmit descriptor array remains full too long */
  324. timeout = TX_TIMEOUT;
  325. while ((readl(&regs->status) & STATUS_TXSTATUS) &&
  326. (readl(&regs->txconsumeindex)
  327. == readl(&regs->txproduceindex))) {
  328. if (timeout-- == 0)
  329. return -1;
  330. }
  331. /* determine next transmit packet index to use */
  332. tx_index = readl(&regs->txproduceindex);
  333. /* set up transmit packet */
  334. writel((u32)dataptr, &bufs->tx_desc[tx_index].packet);
  335. writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
  336. &bufs->tx_desc[tx_index].control);
  337. writel(0, &bufs->tx_stat[tx_index].statusinfo);
  338. /* pass transmit packet to DMA engine */
  339. tx_index = (tx_index + 1) % TX_BUF_COUNT;
  340. writel(tx_index, &regs->txproduceindex);
  341. /* transmission succeeded */
  342. return 0;
  343. }
  344. #define RX_TIMEOUT 1000000
  345. static int lpc32xx_eth_recv(struct eth_device *dev)
  346. {
  347. struct lpc32xx_eth_device *lpc32xx_eth_device =
  348. container_of(dev, struct lpc32xx_eth_device, dev);
  349. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  350. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  351. int timeout, rx_index;
  352. /* time out if receive descriptor array remains empty too long */
  353. timeout = RX_TIMEOUT;
  354. while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {
  355. if (timeout-- == 0)
  356. return -1;
  357. }
  358. /* determine next receive packet index to use */
  359. rx_index = readl(&regs->rxconsumeindex);
  360. /* if data was valid, pass it on */
  361. if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
  362. net_process_received_packet(
  363. &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
  364. (bufs->rx_stat[rx_index].statusinfo
  365. & RX_STAT_RXSIZE) + 1);
  366. }
  367. /* pass receive slot back to DMA engine */
  368. rx_index = (rx_index + 1) % RX_BUF_COUNT;
  369. writel(rx_index, &regs->rxconsumeindex);
  370. /* reception successful */
  371. return 0;
  372. }
  373. static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
  374. {
  375. struct lpc32xx_eth_device *lpc32xx_eth_device =
  376. container_of(dev, struct lpc32xx_eth_device, dev);
  377. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  378. /* Save station address */
  379. writel((unsigned long) (dev->enetaddr[0] |
  380. (dev->enetaddr[1] << 8)), &regs->sa2);
  381. writel((unsigned long) (dev->enetaddr[2] |
  382. (dev->enetaddr[3] << 8)), &regs->sa1);
  383. writel((unsigned long) (dev->enetaddr[4] |
  384. (dev->enetaddr[5] << 8)), &regs->sa0);
  385. return 0;
  386. }
  387. static int lpc32xx_eth_init(struct eth_device *dev)
  388. {
  389. struct lpc32xx_eth_device *lpc32xx_eth_device =
  390. container_of(dev, struct lpc32xx_eth_device, dev);
  391. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  392. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  393. int index;
  394. /* Initial MAC initialization */
  395. writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
  396. writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
  397. writel(PKTSIZE_ALIGN, &regs->maxf);
  398. /* Retries: 15 (0xF). Collision window: 57 (0x37). */
  399. writel(0x370F, &regs->clrt);
  400. /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
  401. writel(0x0012, &regs->ipgr);
  402. /* pass runt (smaller than 64 bytes) frames */
  403. if (lpc32xx_eth_device->phy_rmii)
  404. writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command);
  405. else
  406. writel(COMMAND_PASSRUNTFRAME, &regs->command);
  407. /* Configure Full/Half Duplex mode */
  408. if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
  409. setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);
  410. setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);
  411. writel(0x15, &regs->ipgt);
  412. } else {
  413. writel(0x12, &regs->ipgt);
  414. }
  415. /* Configure 100MBit/10MBit mode */
  416. if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
  417. writel(SUPP_SPEED, &regs->supp);
  418. else
  419. writel(0, &regs->supp);
  420. /* Save station address */
  421. writel((unsigned long) (dev->enetaddr[0] |
  422. (dev->enetaddr[1] << 8)), &regs->sa2);
  423. writel((unsigned long) (dev->enetaddr[2] |
  424. (dev->enetaddr[3] << 8)), &regs->sa1);
  425. writel((unsigned long) (dev->enetaddr[4] |
  426. (dev->enetaddr[5] << 8)), &regs->sa0);
  427. /* set up transmit buffers */
  428. for (index = 0; index < TX_BUF_COUNT; index++) {
  429. bufs->tx_desc[index].control = 0;
  430. bufs->tx_stat[index].statusinfo = 0;
  431. }
  432. writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);
  433. writel((u32)(&bufs->tx_stat), &regs->txstatus);
  434. writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);
  435. /* set up receive buffers */
  436. for (index = 0; index < RX_BUF_COUNT; index++) {
  437. bufs->rx_desc[index].packet =
  438. (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
  439. bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
  440. bufs->rx_stat[index].statusinfo = 0;
  441. bufs->rx_stat[index].statushashcrc = 0;
  442. }
  443. writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);
  444. writel((u32)(&bufs->rx_stat), &regs->rxstatus);
  445. writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);
  446. /* Enable broadcast and matching address packets */
  447. writel(RXFILTERCTRL_ACCEPTBROADCAST |
  448. RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);
  449. /* Clear and disable interrupts */
  450. writel(0xFFFF, &regs->intclear);
  451. writel(0, &regs->intenable);
  452. /* Enable receive and transmit mode of MAC ethernet core */
  453. setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
  454. setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);
  455. /*
  456. * Perform a 'dummy' first send to work around Ethernet.1
  457. * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
  458. * Use zeroed "index" variable as the dummy.
  459. */
  460. index = 0;
  461. lpc32xx_eth_send(dev, &index, 4);
  462. return 0;
  463. }
  464. static int lpc32xx_eth_halt(struct eth_device *dev)
  465. {
  466. struct lpc32xx_eth_device *lpc32xx_eth_device =
  467. container_of(dev, struct lpc32xx_eth_device, dev);
  468. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  469. /* Reset all MAC logic */
  470. writel(MAC1_RESETS, &regs->mac1);
  471. writel(COMMAND_RESETS, &regs->command);
  472. /* Let reset condition settle */
  473. udelay(2000);
  474. return 0;
  475. }
  476. #if defined(CONFIG_PHYLIB)
  477. int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
  478. {
  479. struct lpc32xx_eth_device *lpc32xx_eth_device =
  480. container_of(dev, struct lpc32xx_eth_device, dev);
  481. struct mii_dev *bus;
  482. struct phy_device *phydev;
  483. int ret;
  484. bus = mdio_alloc();
  485. if (!bus) {
  486. printf("mdio_alloc failed\n");
  487. return -ENOMEM;
  488. }
  489. bus->read = lpc32xx_eth_phy_read;
  490. bus->write = lpc32xx_eth_phy_write;
  491. strcpy(bus->name, dev->name);
  492. ret = mdio_register(bus);
  493. if (ret) {
  494. printf("mdio_register failed\n");
  495. free(bus);
  496. return -ENOMEM;
  497. }
  498. if (lpc32xx_eth_device->phy_rmii)
  499. phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
  500. else
  501. phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
  502. if (!phydev) {
  503. printf("phy_connect failed\n");
  504. return -ENODEV;
  505. }
  506. phy_config(phydev);
  507. phy_startup(phydev);
  508. return 0;
  509. }
  510. #endif
  511. int lpc32xx_eth_initialize(bd_t *bis)
  512. {
  513. struct eth_device *dev = &lpc32xx_eth.dev;
  514. struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
  515. /*
  516. * Set RMII management clock rate. With HCLK at 104 MHz and
  517. * a divider of 28, this will be 3.72 MHz.
  518. */
  519. writel(MCFG_RESET_MII_MGMT, &regs->mcfg);
  520. writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);
  521. /* Reset all MAC logic */
  522. writel(MAC1_RESETS, &regs->mac1);
  523. writel(COMMAND_RESETS, &regs->command);
  524. /* wait 10 ms for the whole I/F to reset */
  525. udelay(10000);
  526. /* must be less than sizeof(dev->name) */
  527. strcpy(dev->name, "eth0");
  528. dev->init = (void *)lpc32xx_eth_init;
  529. dev->halt = (void *)lpc32xx_eth_halt;
  530. dev->send = (void *)lpc32xx_eth_send;
  531. dev->recv = (void *)lpc32xx_eth_recv;
  532. dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
  533. /* Release SOFT reset to let MII talk to PHY */
  534. clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
  535. /* register driver before talking to phy */
  536. eth_register(dev);
  537. #if defined(CONFIG_PHYLIB)
  538. lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
  539. #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  540. miiphy_register(dev->name, mii_reg_read, mii_reg_write);
  541. #endif
  542. return 0;
  543. }