greth.c 17 KB

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  1. /* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
  2. *
  3. * Driver use polling mode (no Interrupt)
  4. *
  5. * (C) Copyright 2007
  6. * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /* #define DEBUG */
  11. #include <common.h>
  12. #include <command.h>
  13. #include <errno.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <malloc.h>
  17. #include <asm/processor.h>
  18. #include <ambapp.h>
  19. #include <asm/leon.h>
  20. #include <grlib/greth.h>
  21. /* Default to 3s timeout on autonegotiation */
  22. #ifndef GRETH_PHY_TIMEOUT_MS
  23. #define GRETH_PHY_TIMEOUT_MS 3000
  24. #endif
  25. /* Default to PHY adrress 0 not not specified */
  26. #ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
  27. #define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
  28. #else
  29. #define GRETH_PHY_ADR_DEFAULT 0
  30. #endif
  31. /* Let board select which GRETH to use as network interface, set
  32. * this to zero if only one GRETH is available.
  33. */
  34. #ifndef CONFIG_SYS_GRLIB_GRETH_INDEX
  35. #define CONFIG_SYS_GRLIB_GRETH_INDEX 0
  36. #endif
  37. /* ByPass Cache when reading regs */
  38. #define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
  39. /* Write-through cache ==> no bypassing needed on writes */
  40. #define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
  41. #define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
  42. #define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
  43. #define GRETH_RXBD_CNT 4
  44. #define GRETH_TXBD_CNT 1
  45. #define GRETH_RXBUF_SIZE 1540
  46. #define GRETH_BUF_ALIGN 4
  47. #define GRETH_RXBUF_EFF_SIZE \
  48. ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
  49. typedef struct {
  50. greth_regs *regs;
  51. int irq;
  52. struct eth_device *dev;
  53. /* Hardware info */
  54. unsigned char phyaddr;
  55. int gbit_mac;
  56. /* Current operating Mode */
  57. int gb; /* GigaBit */
  58. int fd; /* Full Duplex */
  59. int sp; /* 10/100Mbps speed (1=100,0=10) */
  60. int auto_neg; /* Auto negotiate done */
  61. unsigned char hwaddr[6]; /* MAC Address */
  62. /* Descriptors */
  63. greth_bd *rxbd_base, *rxbd_max;
  64. greth_bd *txbd_base, *txbd_max;
  65. greth_bd *rxbd_curr;
  66. /* rx buffers in rx descriptors */
  67. void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
  68. /* unused for gbit_mac, temp buffer for sending packets with unligned
  69. * start.
  70. * Pointer to packet allocated with malloc.
  71. */
  72. void *txbuf;
  73. struct {
  74. /* rx status */
  75. unsigned int rx_packets,
  76. rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
  77. /* tx stats */
  78. unsigned int tx_packets,
  79. tx_latecol_errors,
  80. tx_underrun_errors, tx_limit_errors, tx_errors;
  81. } stats;
  82. } greth_priv;
  83. /* Read MII register 'addr' from core 'regs' */
  84. static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
  85. {
  86. while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
  87. }
  88. GRETH_REGSAVE(&regs->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
  89. while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
  90. }
  91. if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
  92. return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
  93. } else {
  94. return -1;
  95. }
  96. }
  97. static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
  98. {
  99. while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
  100. }
  101. GRETH_REGSAVE(&regs->mdio,
  102. ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
  103. ((regaddr & 0x1F) << 6) | 1);
  104. while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
  105. }
  106. }
  107. /* init/start hardware and allocate descriptor buffers for rx side
  108. *
  109. */
  110. int greth_init(struct eth_device *dev, bd_t * bis)
  111. {
  112. int i;
  113. greth_priv *greth = dev->priv;
  114. greth_regs *regs = greth->regs;
  115. debug("greth_init\n");
  116. /* Reset core */
  117. GRETH_REGSAVE(&regs->control, (GRETH_RESET | (greth->gb << 8) |
  118. (greth->sp << 7) | (greth->fd << 4)));
  119. /* Wait for Reset to complete */
  120. while ( GRETH_REGLOAD(&regs->control) & GRETH_RESET) ;
  121. GRETH_REGSAVE(&regs->control,
  122. ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
  123. if (!greth->rxbd_base) {
  124. /* allocate descriptors */
  125. greth->rxbd_base = (greth_bd *)
  126. memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
  127. greth->txbd_base = (greth_bd *)
  128. memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
  129. /* allocate buffers to all descriptors */
  130. greth->rxbuf_base =
  131. malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
  132. }
  133. /* initate rx decriptors */
  134. for (i = 0; i < GRETH_RXBD_CNT; i++) {
  135. greth->rxbd_base[i].addr = (unsigned int)
  136. greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
  137. /* enable desciptor & set wrap bit if last descriptor */
  138. if (i >= (GRETH_RXBD_CNT - 1)) {
  139. greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
  140. } else {
  141. greth->rxbd_base[i].stat = GRETH_BD_EN;
  142. }
  143. }
  144. /* initiate indexes */
  145. greth->rxbd_curr = greth->rxbd_base;
  146. greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
  147. greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
  148. /*
  149. * greth->txbd_base->addr = 0;
  150. * greth->txbd_base->stat = GRETH_BD_WR;
  151. */
  152. /* initate tx decriptors */
  153. for (i = 0; i < GRETH_TXBD_CNT; i++) {
  154. greth->txbd_base[i].addr = 0;
  155. /* enable desciptor & set wrap bit if last descriptor */
  156. if (i >= (GRETH_TXBD_CNT - 1)) {
  157. greth->txbd_base[i].stat = GRETH_BD_WR;
  158. } else {
  159. greth->txbd_base[i].stat = 0;
  160. }
  161. }
  162. /**** SET HARDWARE REGS ****/
  163. /* Set pointer to tx/rx descriptor areas */
  164. GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
  165. GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
  166. /* Enable Transmitter, GRETH will now scan descriptors for packets
  167. * to transmitt */
  168. debug("greth_init: enabling receiver\n");
  169. GRETH_REGORIN(&regs->control, GRETH_RXEN);
  170. return 0;
  171. }
  172. /* Initiate PHY to a relevant speed
  173. * return:
  174. * - 0 = success
  175. * - 1 = timeout/fail
  176. */
  177. int greth_init_phy(greth_priv * dev, bd_t * bis)
  178. {
  179. greth_regs *regs = dev->regs;
  180. int tmp, tmp1, tmp2, i;
  181. unsigned int start, timeout;
  182. int phyaddr = GRETH_PHY_ADR_DEFAULT;
  183. #ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
  184. /* If BSP doesn't provide a hardcoded PHY address the driver will
  185. * try to autodetect PHY address by stopping the search on the first
  186. * PHY address which has REG0 implemented.
  187. */
  188. for (i=0; i<32; i++) {
  189. tmp = read_mii(i, 0, regs);
  190. if ( (tmp != 0) && (tmp != 0xffff) ) {
  191. phyaddr = i;
  192. break;
  193. }
  194. }
  195. #endif
  196. /* Save PHY Address */
  197. dev->phyaddr = phyaddr;
  198. debug("GRETH PHY ADDRESS: %d\n", phyaddr);
  199. /* X msecs to ticks */
  200. timeout = GRETH_PHY_TIMEOUT_MS * 1000;
  201. /* Get system timer0 current value
  202. * Total timeout is 5s
  203. */
  204. start = get_timer(0);
  205. /* get phy control register default values */
  206. while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
  207. if (get_timer(start) > timeout) {
  208. debug("greth_init_phy: PHY read 1 failed\n");
  209. return 1; /* Fail */
  210. }
  211. }
  212. /* reset PHY and wait for completion */
  213. write_mii(phyaddr, 0, 0x8000 | tmp, regs);
  214. while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
  215. if (get_timer(start) > timeout) {
  216. debug("greth_init_phy: PHY read 2 failed\n");
  217. return 1; /* Fail */
  218. }
  219. }
  220. /* Check if PHY is autoneg capable and then determine operating
  221. * mode, otherwise force it to 10 Mbit halfduplex
  222. */
  223. dev->gb = 0;
  224. dev->fd = 0;
  225. dev->sp = 0;
  226. dev->auto_neg = 0;
  227. if (!((tmp >> 12) & 1)) {
  228. write_mii(phyaddr, 0, 0, regs);
  229. } else {
  230. /* wait for auto negotiation to complete and then check operating mode */
  231. dev->auto_neg = 1;
  232. i = 0;
  233. while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
  234. if (get_timer(start) > timeout) {
  235. printf("Auto negotiation timed out. "
  236. "Selecting default config\n");
  237. tmp = read_mii(phyaddr, 0, regs);
  238. dev->gb = ((tmp >> 6) & 1)
  239. && !((tmp >> 13) & 1);
  240. dev->sp = !((tmp >> 6) & 1)
  241. && ((tmp >> 13) & 1);
  242. dev->fd = (tmp >> 8) & 1;
  243. goto auto_neg_done;
  244. }
  245. }
  246. if ((tmp >> 8) & 1) {
  247. tmp1 = read_mii(phyaddr, 9, regs);
  248. tmp2 = read_mii(phyaddr, 10, regs);
  249. if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
  250. (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
  251. dev->gb = 1;
  252. dev->fd = 1;
  253. }
  254. if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
  255. (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
  256. dev->gb = 1;
  257. dev->fd = 0;
  258. }
  259. }
  260. if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
  261. tmp1 = read_mii(phyaddr, 4, regs);
  262. tmp2 = read_mii(phyaddr, 5, regs);
  263. if ((tmp1 & GRETH_MII_100TXFD) &&
  264. (tmp2 & GRETH_MII_100TXFD)) {
  265. dev->sp = 1;
  266. dev->fd = 1;
  267. }
  268. if ((tmp1 & GRETH_MII_100TXHD) &&
  269. (tmp2 & GRETH_MII_100TXHD)) {
  270. dev->sp = 1;
  271. dev->fd = 0;
  272. }
  273. if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
  274. dev->fd = 1;
  275. }
  276. if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
  277. dev->gb = 0;
  278. dev->fd = 0;
  279. write_mii(phyaddr, 0, dev->sp << 13, regs);
  280. }
  281. }
  282. }
  283. auto_neg_done:
  284. debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
  285. %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
  286. /* Read out PHY info if extended registers are available */
  287. if (tmp & 1) {
  288. tmp1 = read_mii(phyaddr, 2, regs);
  289. tmp2 = read_mii(phyaddr, 3, regs);
  290. tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
  291. tmp = tmp2 & 0xF;
  292. tmp2 = (tmp2 >> 4) & 0x3F;
  293. debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
  294. tmp2, tmp);
  295. } else {
  296. printf("PHY info not available\n");
  297. }
  298. /* set speed and duplex bits in control register */
  299. GRETH_REGORIN(&regs->control,
  300. (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
  301. return 0;
  302. }
  303. void greth_halt(struct eth_device *dev)
  304. {
  305. greth_priv *greth;
  306. greth_regs *regs;
  307. int i;
  308. debug("greth_halt\n");
  309. if (!dev || !dev->priv)
  310. return;
  311. greth = dev->priv;
  312. regs = greth->regs;
  313. if (!regs)
  314. return;
  315. /* disable receiver/transmitter by clearing the enable bits */
  316. GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN | GRETH_TXEN));
  317. /* reset rx/tx descriptors */
  318. if (greth->rxbd_base) {
  319. for (i = 0; i < GRETH_RXBD_CNT; i++) {
  320. greth->rxbd_base[i].stat =
  321. (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
  322. }
  323. }
  324. if (greth->txbd_base) {
  325. for (i = 0; i < GRETH_TXBD_CNT; i++) {
  326. greth->txbd_base[i].stat =
  327. (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
  328. }
  329. }
  330. }
  331. int greth_send(struct eth_device *dev, void *eth_data, int data_length)
  332. {
  333. greth_priv *greth = dev->priv;
  334. greth_regs *regs = greth->regs;
  335. greth_bd *txbd;
  336. void *txbuf;
  337. unsigned int status;
  338. debug("greth_send\n");
  339. /* send data, wait for data to be sent, then return */
  340. if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
  341. && !greth->gbit_mac) {
  342. /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
  343. * and copy data to before giving it to GRETH.
  344. */
  345. if (!greth->txbuf) {
  346. greth->txbuf = malloc(GRETH_RXBUF_SIZE);
  347. }
  348. txbuf = greth->txbuf;
  349. /* copy data info buffer */
  350. memcpy((char *)txbuf, (char *)eth_data, data_length);
  351. /* keep buffer to next time */
  352. } else {
  353. txbuf = (void *)eth_data;
  354. }
  355. /* get descriptor to use, only 1 supported... hehe easy */
  356. txbd = greth->txbd_base;
  357. /* setup descriptor to wrap around to it self */
  358. txbd->addr = (unsigned int)txbuf;
  359. txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
  360. /* Remind Core which descriptor to use when sending */
  361. GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);
  362. /* initate send by enabling transmitter */
  363. GRETH_REGORIN(&regs->control, GRETH_TXEN);
  364. /* Wait for data to be sent */
  365. while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
  366. ;
  367. }
  368. /* was the packet transmitted succesfully? */
  369. if (status & GRETH_TXBD_ERR_AL) {
  370. greth->stats.tx_limit_errors++;
  371. }
  372. if (status & GRETH_TXBD_ERR_UE) {
  373. greth->stats.tx_underrun_errors++;
  374. }
  375. if (status & GRETH_TXBD_ERR_LC) {
  376. greth->stats.tx_latecol_errors++;
  377. }
  378. if (status &
  379. (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
  380. /* any error */
  381. greth->stats.tx_errors++;
  382. return -1;
  383. }
  384. /* bump tx packet counter */
  385. greth->stats.tx_packets++;
  386. /* return succefully */
  387. return 0;
  388. }
  389. int greth_recv(struct eth_device *dev)
  390. {
  391. greth_priv *greth = dev->priv;
  392. greth_regs *regs = greth->regs;
  393. greth_bd *rxbd;
  394. unsigned int status, len = 0, bad;
  395. char *d;
  396. int enable = 0;
  397. int i;
  398. /* Receive One packet only, but clear as many error packets as there are
  399. * available.
  400. */
  401. {
  402. /* current receive descriptor */
  403. rxbd = greth->rxbd_curr;
  404. /* get status of next received packet */
  405. status = GRETH_REGLOAD(&rxbd->stat);
  406. bad = 0;
  407. /* stop if no more packets received */
  408. if (status & GRETH_BD_EN) {
  409. goto done;
  410. }
  411. debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
  412. (unsigned int)rxbd, status, status & GRETH_BD_LEN);
  413. /* Check status for errors.
  414. */
  415. if (status & GRETH_RXBD_ERR_FT) {
  416. greth->stats.rx_length_errors++;
  417. bad = 1;
  418. }
  419. if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
  420. greth->stats.rx_frame_errors++;
  421. bad = 1;
  422. }
  423. if (status & GRETH_RXBD_ERR_CRC) {
  424. greth->stats.rx_crc_errors++;
  425. bad = 1;
  426. }
  427. if (bad) {
  428. greth->stats.rx_errors++;
  429. printf
  430. ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
  431. greth->stats.rx_length_errors,
  432. greth->stats.rx_frame_errors,
  433. greth->stats.rx_crc_errors, status,
  434. greth->stats.rx_packets);
  435. /* print all rx descriptors */
  436. for (i = 0; i < GRETH_RXBD_CNT; i++) {
  437. printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
  438. GRETH_REGLOAD(&greth->rxbd_base[i].stat),
  439. GRETH_REGLOAD(&greth->rxbd_base[i].addr));
  440. }
  441. } else {
  442. /* Process the incoming packet. */
  443. len = status & GRETH_BD_LEN;
  444. d = (char *)rxbd->addr;
  445. debug
  446. ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
  447. len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
  448. d[7]);
  449. /* flush all data cache to make sure we're not reading old packet data */
  450. sparc_dcache_flush_all();
  451. /* pass packet on to network subsystem */
  452. net_process_received_packet((void *)d, len);
  453. /* bump stats counters */
  454. greth->stats.rx_packets++;
  455. /* bad is now 0 ==> will stop loop */
  456. }
  457. /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
  458. rxbd->stat =
  459. GRETH_BD_EN |
  460. (((unsigned int)greth->rxbd_curr >=
  461. (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
  462. enable = 1;
  463. /* increase index */
  464. greth->rxbd_curr =
  465. ((unsigned int)greth->rxbd_curr >=
  466. (unsigned int)greth->rxbd_max) ? greth->
  467. rxbd_base : (greth->rxbd_curr + 1);
  468. }
  469. if (enable) {
  470. GRETH_REGORIN(&regs->control, GRETH_RXEN);
  471. }
  472. done:
  473. /* return positive length of packet or 0 if non received */
  474. return len;
  475. }
  476. void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
  477. {
  478. /* save new MAC address */
  479. greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
  480. greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
  481. greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
  482. greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
  483. greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
  484. greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
  485. greth->regs->esa_msb = (mac[0] << 8) | mac[1];
  486. greth->regs->esa_lsb =
  487. (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
  488. debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
  489. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  490. }
  491. int greth_initialize(bd_t * bis)
  492. {
  493. greth_priv *greth;
  494. ambapp_apbdev apbdev;
  495. struct eth_device *dev;
  496. int i;
  497. char *addr_str, *end;
  498. unsigned char addr[6];
  499. debug("Scanning for GRETH\n");
  500. /* Find Device & IRQ via AMBA Plug&Play information,
  501. * CONFIG_SYS_GRLIB_GRETH_INDEX select which GRETH if multiple
  502. * GRETHs in system.
  503. */
  504. if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_ETHMAC,
  505. CONFIG_SYS_GRLIB_GRETH_INDEX, &apbdev) != 1) {
  506. return -1; /* GRETH not found */
  507. }
  508. greth = (greth_priv *) malloc(sizeof(greth_priv));
  509. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  510. memset(dev, 0, sizeof(struct eth_device));
  511. memset(greth, 0, sizeof(greth_priv));
  512. greth->regs = (greth_regs *) apbdev.address;
  513. greth->irq = apbdev.irq;
  514. debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
  515. dev->priv = (void *)greth;
  516. dev->iobase = (unsigned int)greth->regs;
  517. dev->init = greth_init;
  518. dev->halt = greth_halt;
  519. dev->send = greth_send;
  520. dev->recv = greth_recv;
  521. greth->dev = dev;
  522. /* Reset Core */
  523. GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
  524. /* Wait for core to finish reset cycle */
  525. while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
  526. /* Get the phy address which assumed to have been set
  527. correctly with the reset value in hardware */
  528. greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
  529. /* Check if mac is gigabit capable */
  530. greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
  531. /* Make descriptor string */
  532. if (greth->gbit_mac) {
  533. strcpy(dev->name, "GRETH_10/100/GB");
  534. } else {
  535. strcpy(dev->name, "GRETH_10/100");
  536. }
  537. /* initiate PHY, select speed/duplex depending on connected PHY */
  538. if (greth_init_phy(greth, bis)) {
  539. /* Failed to init PHY (timedout) */
  540. debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
  541. return -1;
  542. }
  543. /* Register Device to EtherNet subsystem */
  544. eth_register(dev);
  545. /* Get MAC address */
  546. if ((addr_str = getenv("ethaddr")) != NULL) {
  547. for (i = 0; i < 6; i++) {
  548. addr[i] =
  549. addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
  550. if (addr_str) {
  551. addr_str = (*end) ? end + 1 : end;
  552. }
  553. }
  554. } else {
  555. /* No ethaddr set */
  556. return -EINVAL;
  557. }
  558. /* set and remember MAC address */
  559. greth_set_hwaddr(greth, addr);
  560. debug("GRETH[%p]: Initialized successfully\n", greth->regs);
  561. return 0;
  562. }