ftgmac100.c 13 KB

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  1. /*
  2. * Faraday FTGMAC100 Ethernet
  3. *
  4. * (C) Copyright 2009 Faraday Technology
  5. * Po-Yu Chuang <ratbert@faraday-tech.com>
  6. *
  7. * (C) Copyright 2010 Andes Technology
  8. * Macpaul Lin <macpaul@andestech.com>
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <malloc.h>
  15. #include <net.h>
  16. #include <asm/io.h>
  17. #include <asm/dma-mapping.h>
  18. #include <linux/mii.h>
  19. #include "ftgmac100.h"
  20. #define ETH_ZLEN 60
  21. #define CFG_XBUF_SIZE 1536
  22. /* RBSR - hw default init value is also 0x640 */
  23. #define RBSR_DEFAULT_VALUE 0x640
  24. /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
  25. #define PKTBUFSTX 4 /* must be power of 2 */
  26. struct ftgmac100_data {
  27. ulong txdes_dma;
  28. struct ftgmac100_txdes *txdes;
  29. ulong rxdes_dma;
  30. struct ftgmac100_rxdes *rxdes;
  31. int tx_index;
  32. int rx_index;
  33. int phy_addr;
  34. };
  35. /*
  36. * struct mii_bus functions
  37. */
  38. static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
  39. int regnum)
  40. {
  41. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  42. int phycr;
  43. int i;
  44. phycr = readl(&ftgmac100->phycr);
  45. /* preserve MDC cycle threshold */
  46. phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
  47. phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
  48. | FTGMAC100_PHYCR_REGAD(regnum)
  49. | FTGMAC100_PHYCR_MIIRD;
  50. writel(phycr, &ftgmac100->phycr);
  51. for (i = 0; i < 10; i++) {
  52. phycr = readl(&ftgmac100->phycr);
  53. if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
  54. int data;
  55. data = readl(&ftgmac100->phydata);
  56. return FTGMAC100_PHYDATA_MIIRDATA(data);
  57. }
  58. mdelay(10);
  59. }
  60. debug("mdio read timed out\n");
  61. return -1;
  62. }
  63. static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
  64. int regnum, u16 value)
  65. {
  66. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  67. int phycr;
  68. int data;
  69. int i;
  70. phycr = readl(&ftgmac100->phycr);
  71. /* preserve MDC cycle threshold */
  72. phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
  73. phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
  74. | FTGMAC100_PHYCR_REGAD(regnum)
  75. | FTGMAC100_PHYCR_MIIWR;
  76. data = FTGMAC100_PHYDATA_MIIWDATA(value);
  77. writel(data, &ftgmac100->phydata);
  78. writel(phycr, &ftgmac100->phycr);
  79. for (i = 0; i < 10; i++) {
  80. phycr = readl(&ftgmac100->phycr);
  81. if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
  82. debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
  83. "phy_addr: %x\n", phy_addr);
  84. return 0;
  85. }
  86. mdelay(1);
  87. }
  88. debug("mdio write timed out\n");
  89. return -1;
  90. }
  91. int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
  92. {
  93. *value = ftgmac100_mdiobus_read(dev , addr, reg);
  94. if (*value == -1)
  95. return -1;
  96. return 0;
  97. }
  98. int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
  99. {
  100. if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
  101. return -1;
  102. return 0;
  103. }
  104. static int ftgmac100_phy_reset(struct eth_device *dev)
  105. {
  106. struct ftgmac100_data *priv = dev->priv;
  107. int i;
  108. u16 status, adv;
  109. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  110. ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
  111. printf("%s: Starting autonegotiation...\n", dev->name);
  112. ftgmac100_phy_write(dev, priv->phy_addr,
  113. MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
  114. for (i = 0; i < 100000 / 100; i++) {
  115. ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
  116. if (status & BMSR_ANEGCOMPLETE)
  117. break;
  118. mdelay(1);
  119. }
  120. if (status & BMSR_ANEGCOMPLETE) {
  121. printf("%s: Autonegotiation complete\n", dev->name);
  122. } else {
  123. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  124. dev->name, status);
  125. return 0;
  126. }
  127. return 1;
  128. }
  129. static int ftgmac100_phy_init(struct eth_device *dev)
  130. {
  131. struct ftgmac100_data *priv = dev->priv;
  132. int phy_addr;
  133. u16 phy_id, status, adv, lpa, stat_ge;
  134. int media, speed, duplex;
  135. int i;
  136. /* Check if the PHY is up to snuff... */
  137. for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
  138. ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
  139. /*
  140. * When it is unable to found PHY,
  141. * the interface usually return 0xffff or 0x0000
  142. */
  143. if (phy_id != 0xffff && phy_id != 0x0) {
  144. printf("%s: found PHY at 0x%02x\n",
  145. dev->name, phy_addr);
  146. priv->phy_addr = phy_addr;
  147. break;
  148. }
  149. }
  150. if (phy_id == 0xffff || phy_id == 0x0) {
  151. printf("%s: no PHY present\n", dev->name);
  152. return 0;
  153. }
  154. ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
  155. if (!(status & BMSR_LSTATUS)) {
  156. /* Try to re-negotiate if we don't have link already. */
  157. ftgmac100_phy_reset(dev);
  158. for (i = 0; i < 100000 / 100; i++) {
  159. ftgmac100_phy_read(dev, priv->phy_addr,
  160. MII_BMSR, &status);
  161. if (status & BMSR_LSTATUS)
  162. break;
  163. udelay(100);
  164. }
  165. }
  166. if (!(status & BMSR_LSTATUS)) {
  167. printf("%s: link down\n", dev->name);
  168. return 0;
  169. }
  170. #ifdef CONFIG_FTGMAC100_EGIGA
  171. /* 1000 Base-T Status Register */
  172. ftgmac100_phy_read(dev, priv->phy_addr,
  173. MII_STAT1000, &stat_ge);
  174. speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
  175. ? 1 : 0);
  176. duplex = ((stat_ge & LPA_1000FULL)
  177. ? 1 : 0);
  178. if (speed) { /* Speed is 1000 */
  179. printf("%s: link up, 1000bps %s-duplex\n",
  180. dev->name, duplex ? "full" : "half");
  181. return 0;
  182. }
  183. #endif
  184. ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
  185. ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
  186. media = mii_nway_result(lpa & adv);
  187. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
  188. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  189. printf("%s: link up, %sMbps %s-duplex\n",
  190. dev->name, speed ? "100" : "10", duplex ? "full" : "half");
  191. return 1;
  192. }
  193. static int ftgmac100_update_link_speed(struct eth_device *dev)
  194. {
  195. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  196. struct ftgmac100_data *priv = dev->priv;
  197. unsigned short stat_fe;
  198. unsigned short stat_ge;
  199. unsigned int maccr;
  200. #ifdef CONFIG_FTGMAC100_EGIGA
  201. /* 1000 Base-T Status Register */
  202. ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
  203. #endif
  204. ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
  205. if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
  206. return 0;
  207. /* read MAC control register and clear related bits */
  208. maccr = readl(&ftgmac100->maccr) &
  209. ~(FTGMAC100_MACCR_GIGA_MODE |
  210. FTGMAC100_MACCR_FAST_MODE |
  211. FTGMAC100_MACCR_FULLDUP);
  212. #ifdef CONFIG_FTGMAC100_EGIGA
  213. if (stat_ge & LPA_1000FULL) {
  214. /* set gmac for 1000BaseTX and Full Duplex */
  215. maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
  216. }
  217. if (stat_ge & LPA_1000HALF) {
  218. /* set gmac for 1000BaseTX and Half Duplex */
  219. maccr |= FTGMAC100_MACCR_GIGA_MODE;
  220. }
  221. #endif
  222. if (stat_fe & BMSR_100FULL) {
  223. /* set MII for 100BaseTX and Full Duplex */
  224. maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
  225. }
  226. if (stat_fe & BMSR_10FULL) {
  227. /* set MII for 10BaseT and Full Duplex */
  228. maccr |= FTGMAC100_MACCR_FULLDUP;
  229. }
  230. if (stat_fe & BMSR_100HALF) {
  231. /* set MII for 100BaseTX and Half Duplex */
  232. maccr |= FTGMAC100_MACCR_FAST_MODE;
  233. }
  234. if (stat_fe & BMSR_10HALF) {
  235. /* set MII for 10BaseT and Half Duplex */
  236. /* we have already clear these bits, do nothing */
  237. ;
  238. }
  239. /* update MII config into maccr */
  240. writel(maccr, &ftgmac100->maccr);
  241. return 1;
  242. }
  243. /*
  244. * Reset MAC
  245. */
  246. static void ftgmac100_reset(struct eth_device *dev)
  247. {
  248. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  249. debug("%s()\n", __func__);
  250. writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
  251. while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
  252. ;
  253. }
  254. /*
  255. * Set MAC address
  256. */
  257. static void ftgmac100_set_mac(struct eth_device *dev,
  258. const unsigned char *mac)
  259. {
  260. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  261. unsigned int maddr = mac[0] << 8 | mac[1];
  262. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  263. debug("%s(%x %x)\n", __func__, maddr, laddr);
  264. writel(maddr, &ftgmac100->mac_madr);
  265. writel(laddr, &ftgmac100->mac_ladr);
  266. }
  267. static void ftgmac100_set_mac_from_env(struct eth_device *dev)
  268. {
  269. eth_getenv_enetaddr("ethaddr", dev->enetaddr);
  270. ftgmac100_set_mac(dev, dev->enetaddr);
  271. }
  272. /*
  273. * disable transmitter, receiver
  274. */
  275. static void ftgmac100_halt(struct eth_device *dev)
  276. {
  277. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  278. debug("%s()\n", __func__);
  279. writel(0, &ftgmac100->maccr);
  280. }
  281. static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
  282. {
  283. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  284. struct ftgmac100_data *priv = dev->priv;
  285. struct ftgmac100_txdes *txdes;
  286. struct ftgmac100_rxdes *rxdes;
  287. unsigned int maccr;
  288. void *buf;
  289. int i;
  290. debug("%s()\n", __func__);
  291. if (!priv->txdes) {
  292. txdes = dma_alloc_coherent(
  293. sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
  294. if (!txdes)
  295. panic("ftgmac100: out of memory\n");
  296. memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
  297. priv->txdes = txdes;
  298. }
  299. txdes = priv->txdes;
  300. if (!priv->rxdes) {
  301. rxdes = dma_alloc_coherent(
  302. sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
  303. if (!rxdes)
  304. panic("ftgmac100: out of memory\n");
  305. memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
  306. priv->rxdes = rxdes;
  307. }
  308. rxdes = priv->rxdes;
  309. /* set the ethernet address */
  310. ftgmac100_set_mac_from_env(dev);
  311. /* disable all interrupts */
  312. writel(0, &ftgmac100->ier);
  313. /* initialize descriptors */
  314. priv->tx_index = 0;
  315. priv->rx_index = 0;
  316. txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
  317. rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
  318. for (i = 0; i < PKTBUFSTX; i++) {
  319. /* TXBUF_BADR */
  320. if (!txdes[i].txdes2) {
  321. buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
  322. if (!buf)
  323. panic("ftgmac100: out of memory\n");
  324. txdes[i].txdes3 = virt_to_phys(buf);
  325. txdes[i].txdes2 = (uint)buf;
  326. }
  327. txdes[i].txdes1 = 0;
  328. }
  329. for (i = 0; i < PKTBUFSRX; i++) {
  330. /* RXBUF_BADR */
  331. if (!rxdes[i].rxdes2) {
  332. buf = net_rx_packets[i];
  333. rxdes[i].rxdes3 = virt_to_phys(buf);
  334. rxdes[i].rxdes2 = (uint)buf;
  335. }
  336. rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
  337. }
  338. /* transmit ring */
  339. writel(priv->txdes_dma, &ftgmac100->txr_badr);
  340. /* receive ring */
  341. writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
  342. /* poll receive descriptor automatically */
  343. writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
  344. /* config receive buffer size register */
  345. writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
  346. /* enable transmitter, receiver */
  347. maccr = FTGMAC100_MACCR_TXMAC_EN |
  348. FTGMAC100_MACCR_RXMAC_EN |
  349. FTGMAC100_MACCR_TXDMA_EN |
  350. FTGMAC100_MACCR_RXDMA_EN |
  351. FTGMAC100_MACCR_CRC_APD |
  352. FTGMAC100_MACCR_FULLDUP |
  353. FTGMAC100_MACCR_RX_RUNT |
  354. FTGMAC100_MACCR_RX_BROADPKT;
  355. writel(maccr, &ftgmac100->maccr);
  356. if (!ftgmac100_phy_init(dev)) {
  357. if (!ftgmac100_update_link_speed(dev))
  358. return -1;
  359. }
  360. return 0;
  361. }
  362. /*
  363. * Get a data block via Ethernet
  364. */
  365. static int ftgmac100_recv(struct eth_device *dev)
  366. {
  367. struct ftgmac100_data *priv = dev->priv;
  368. struct ftgmac100_rxdes *curr_des;
  369. unsigned short rxlen;
  370. curr_des = &priv->rxdes[priv->rx_index];
  371. if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
  372. return -1;
  373. if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
  374. FTGMAC100_RXDES0_CRC_ERR |
  375. FTGMAC100_RXDES0_FTL |
  376. FTGMAC100_RXDES0_RUNT |
  377. FTGMAC100_RXDES0_RX_ODD_NB)) {
  378. return -1;
  379. }
  380. rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
  381. debug("%s(): RX buffer %d, %x received\n",
  382. __func__, priv->rx_index, rxlen);
  383. /* invalidate d-cache */
  384. dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
  385. /* pass the packet up to the protocol layers. */
  386. net_process_received_packet((void *)curr_des->rxdes2, rxlen);
  387. /* release buffer to DMA */
  388. curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
  389. priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
  390. return 0;
  391. }
  392. /*
  393. * Send a data block via Ethernet
  394. */
  395. static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
  396. {
  397. struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
  398. struct ftgmac100_data *priv = dev->priv;
  399. struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
  400. if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
  401. debug("%s(): no TX descriptor available\n", __func__);
  402. return -1;
  403. }
  404. debug("%s(%x, %x)\n", __func__, (int)packet, length);
  405. length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
  406. memcpy((void *)curr_des->txdes2, (void *)packet, length);
  407. dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
  408. /* only one descriptor on TXBUF */
  409. curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
  410. curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
  411. FTGMAC100_TXDES0_LTS |
  412. FTGMAC100_TXDES0_TXBUF_SIZE(length) |
  413. FTGMAC100_TXDES0_TXDMA_OWN ;
  414. /* start transmit */
  415. writel(1, &ftgmac100->txpd);
  416. debug("%s(): packet sent\n", __func__);
  417. priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
  418. return 0;
  419. }
  420. int ftgmac100_initialize(bd_t *bd)
  421. {
  422. struct eth_device *dev;
  423. struct ftgmac100_data *priv;
  424. dev = malloc(sizeof *dev);
  425. if (!dev) {
  426. printf("%s(): failed to allocate dev\n", __func__);
  427. goto out;
  428. }
  429. /* Transmit and receive descriptors should align to 16 bytes */
  430. priv = memalign(16, sizeof(struct ftgmac100_data));
  431. if (!priv) {
  432. printf("%s(): failed to allocate priv\n", __func__);
  433. goto free_dev;
  434. }
  435. memset(dev, 0, sizeof(*dev));
  436. memset(priv, 0, sizeof(*priv));
  437. strcpy(dev->name, "FTGMAC100");
  438. dev->iobase = CONFIG_FTGMAC100_BASE;
  439. dev->init = ftgmac100_init;
  440. dev->halt = ftgmac100_halt;
  441. dev->send = ftgmac100_send;
  442. dev->recv = ftgmac100_recv;
  443. dev->priv = priv;
  444. eth_register(dev);
  445. ftgmac100_reset(dev);
  446. return 1;
  447. free_dev:
  448. free(dev);
  449. out:
  450. return 0;
  451. }