memac_phy.c 4.5 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. * Andy Fleming <afleming@gmail.com>
  4. * Roy Zang <tie-fei.zang@freescale.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. * Some part is taken from tsec.c
  8. */
  9. #include <common.h>
  10. #include <miiphy.h>
  11. #include <phy.h>
  12. #include <asm/io.h>
  13. #include <fsl_memac.h>
  14. #include <fm_eth.h>
  15. #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  16. #define memac_out_32(a, v) out_le32(a, v)
  17. #define memac_clrbits_32(a, v) clrbits_le32(a, v)
  18. #define memac_setbits_32(a, v) setbits_le32(a, v)
  19. #else
  20. #define memac_out_32(a, v) out_be32(a, v)
  21. #define memac_clrbits_32(a, v) clrbits_be32(a, v)
  22. #define memac_setbits_32(a, v) setbits_be32(a, v)
  23. #endif
  24. static u32 memac_in_32(u32 *reg)
  25. {
  26. #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  27. return in_le32(reg);
  28. #else
  29. return in_be32(reg);
  30. #endif
  31. }
  32. /*
  33. * Write value to the PHY for this device to the register at regnum, waiting
  34. * until the write is done before it returns. All PHY configuration has to be
  35. * done through the TSEC1 MIIM regs
  36. */
  37. int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
  38. int regnum, u16 value)
  39. {
  40. u32 mdio_ctl;
  41. struct memac_mdio_controller *regs = bus->priv;
  42. u32 c45 = 1; /* Default to 10G interface */
  43. if (dev_addr == MDIO_DEVAD_NONE) {
  44. c45 = 0; /* clause 22 */
  45. dev_addr = regnum & 0x1f;
  46. memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  47. } else
  48. memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  49. /* Wait till the bus is free */
  50. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  51. ;
  52. /* Set the port and dev addr */
  53. mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
  54. memac_out_32(&regs->mdio_ctl, mdio_ctl);
  55. /* Set the register address */
  56. if (c45)
  57. memac_out_32(&regs->mdio_addr, regnum & 0xffff);
  58. /* Wait till the bus is free */
  59. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  60. ;
  61. /* Write the value to the register */
  62. memac_out_32(&regs->mdio_data, MDIO_DATA(value));
  63. /* Wait till the MDIO write is complete */
  64. while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
  65. ;
  66. return 0;
  67. }
  68. /*
  69. * Reads from register regnum in the PHY for device dev, returning the value.
  70. * Clears miimcom first. All PHY configuration has to be done through the
  71. * TSEC1 MIIM regs
  72. */
  73. int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
  74. int regnum)
  75. {
  76. u32 mdio_ctl;
  77. struct memac_mdio_controller *regs = bus->priv;
  78. u32 c45 = 1;
  79. if (dev_addr == MDIO_DEVAD_NONE) {
  80. if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
  81. return 0xffff;
  82. c45 = 0; /* clause 22 */
  83. dev_addr = regnum & 0x1f;
  84. memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  85. } else
  86. memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  87. /* Wait till the bus is free */
  88. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  89. ;
  90. /* Set the Port and Device Addrs */
  91. mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
  92. memac_out_32(&regs->mdio_ctl, mdio_ctl);
  93. /* Set the register address */
  94. if (c45)
  95. memac_out_32(&regs->mdio_addr, regnum & 0xffff);
  96. /* Wait till the bus is free */
  97. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  98. ;
  99. /* Initiate the read */
  100. mdio_ctl |= MDIO_CTL_READ;
  101. memac_out_32(&regs->mdio_ctl, mdio_ctl);
  102. /* Wait till the MDIO write is complete */
  103. while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
  104. ;
  105. /* Return all Fs if nothing was there */
  106. if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
  107. return 0xffff;
  108. return memac_in_32(&regs->mdio_data) & 0xffff;
  109. }
  110. int memac_mdio_reset(struct mii_dev *bus)
  111. {
  112. return 0;
  113. }
  114. int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
  115. {
  116. struct mii_dev *bus = mdio_alloc();
  117. if (!bus) {
  118. printf("Failed to allocate FM TGEC MDIO bus\n");
  119. return -1;
  120. }
  121. bus->read = memac_mdio_read;
  122. bus->write = memac_mdio_write;
  123. bus->reset = memac_mdio_reset;
  124. strcpy(bus->name, info->name);
  125. bus->priv = info->regs;
  126. /*
  127. * On some platforms like B4860, default value of MDIO_CLK_DIV bits
  128. * in mdio_stat(mdio_cfg) register generates MDIO clock too high
  129. * (much higher than 2.5MHz), violating the IEEE specs.
  130. * On other platforms like T1040, default value of MDIO_CLK_DIV bits
  131. * is zero, so MDIO clock is disabled.
  132. * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
  133. * be properly initialized.
  134. * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
  135. * like T2080QDS, this bit default is '0', which leads to MDIO failure
  136. * on XAUI PHY, so set this bit definitely.
  137. */
  138. memac_setbits_32(
  139. &((struct memac_mdio_controller *)info->regs)->mdio_stat,
  140. MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
  141. return mdio_register(bus);
  142. }