dm9000x.c 16 KB

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  1. /*
  2. dm9000.c: Version 1.2 12/15/2003
  3. A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
  4. Copyright (C) 1997 Sten Wang
  5. * SPDX-License-Identifier: GPL-2.0+
  6. (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  7. V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
  8. 06/22/2001 Support DM9801 progrmming
  9. E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  10. E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  11. R17 = (R17 & 0xfff0) | NF + 3
  12. E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  13. R17 = (R17 & 0xfff0) | NF
  14. v1.00 modify by simon 2001.9.5
  15. change for kernel 2.4.x
  16. v1.1 11/09/2001 fix force mode bug
  17. v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
  18. Fixed phy reset.
  19. Added tx/rx 32 bit mode.
  20. Cleaned up for kernel merge.
  21. --------------------------------------
  22. 12/15/2003 Initial port to u-boot by
  23. Sascha Hauer <saschahauer@web.de>
  24. 06/03/2008 Remy Bohmer <linux@bohmer.net>
  25. - Fixed the driver to work with DM9000A.
  26. (check on ISR receive status bit before reading the
  27. FIFO as described in DM9000 programming guide and
  28. application notes)
  29. - Added autodetect of databus width.
  30. - Made debug code compile again.
  31. - Adapt eth_send such that it matches the DM9000*
  32. application notes. Needed to make it work properly
  33. for DM9000A.
  34. - Adapted reset procedure to match DM9000 application
  35. notes (i.e. double reset)
  36. - some minor code cleanups
  37. These changes are tested with DM9000{A,EP,E} together
  38. with a 200MHz Atmel AT91SAM9261 core
  39. TODO: external MII is not functional, only internal at the moment.
  40. */
  41. #include <common.h>
  42. #include <command.h>
  43. #include <net.h>
  44. #include <asm/io.h>
  45. #include <dm9000.h>
  46. #include "dm9000x.h"
  47. /* Board/System/Debug information/definition ---------------- */
  48. /* #define CONFIG_DM9000_DEBUG */
  49. #ifdef CONFIG_DM9000_DEBUG
  50. #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
  51. #define DM9000_DMP_PACKET(func,packet,length) \
  52. do { \
  53. int i; \
  54. printf("%s: length: %d\n", func, length); \
  55. for (i = 0; i < length; i++) { \
  56. if (i % 8 == 0) \
  57. printf("\n%s: %02x: ", func, i); \
  58. printf("%02x ", ((unsigned char *) packet)[i]); \
  59. } printf("\n"); \
  60. } while(0)
  61. #else
  62. #define DM9000_DBG(fmt,args...)
  63. #define DM9000_DMP_PACKET(func,packet,length)
  64. #endif
  65. /* Structure/enum declaration ------------------------------- */
  66. typedef struct board_info {
  67. u32 runt_length_counter; /* counter: RX length < 64byte */
  68. u32 long_length_counter; /* counter: RX length > 1514byte */
  69. u32 reset_counter; /* counter: RESET */
  70. u32 reset_tx_timeout; /* RESET caused by TX Timeout */
  71. u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
  72. u16 tx_pkt_cnt;
  73. u16 queue_start_addr;
  74. u16 dbug_cnt;
  75. u8 phy_addr;
  76. u8 device_wait_reset; /* device state */
  77. unsigned char srom[128];
  78. void (*outblk)(volatile void *data_ptr, int count);
  79. void (*inblk)(void *data_ptr, int count);
  80. void (*rx_status)(u16 *RxStatus, u16 *RxLen);
  81. struct eth_device netdev;
  82. } board_info_t;
  83. static board_info_t dm9000_info;
  84. /* function declaration ------------------------------------- */
  85. static int dm9000_probe(void);
  86. static u16 dm9000_phy_read(int);
  87. static void dm9000_phy_write(int, u16);
  88. static u8 DM9000_ior(int);
  89. static void DM9000_iow(int reg, u8 value);
  90. /* DM9000 network board routine ---------------------------- */
  91. #ifndef CONFIG_DM9000_BYTE_SWAPPED
  92. #define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
  93. #define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
  94. #define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
  95. #define DM9000_inb(r) readb((volatile u8 *)(r))
  96. #define DM9000_inw(r) readw((volatile u16 *)(r))
  97. #define DM9000_inl(r) readl((volatile u32 *)(r))
  98. #else
  99. #define DM9000_outb(d, r) __raw_writeb(d, r)
  100. #define DM9000_outw(d, r) __raw_writew(d, r)
  101. #define DM9000_outl(d, r) __raw_writel(d, r)
  102. #define DM9000_inb(r) __raw_readb(r)
  103. #define DM9000_inw(r) __raw_readw(r)
  104. #define DM9000_inl(r) __raw_readl(r)
  105. #endif
  106. #ifdef CONFIG_DM9000_DEBUG
  107. static void
  108. dump_regs(void)
  109. {
  110. DM9000_DBG("\n");
  111. DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
  112. DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
  113. DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
  114. DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
  115. DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
  116. DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
  117. DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
  118. DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
  119. DM9000_DBG("\n");
  120. }
  121. #endif
  122. static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
  123. {
  124. int i;
  125. for (i = 0; i < count; i++)
  126. DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
  127. }
  128. static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
  129. {
  130. int i;
  131. u32 tmplen = (count + 1) / 2;
  132. for (i = 0; i < tmplen; i++)
  133. DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
  134. }
  135. static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
  136. {
  137. int i;
  138. u32 tmplen = (count + 3) / 4;
  139. for (i = 0; i < tmplen; i++)
  140. DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
  141. }
  142. static void dm9000_inblk_8bit(void *data_ptr, int count)
  143. {
  144. int i;
  145. for (i = 0; i < count; i++)
  146. ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
  147. }
  148. static void dm9000_inblk_16bit(void *data_ptr, int count)
  149. {
  150. int i;
  151. u32 tmplen = (count + 1) / 2;
  152. for (i = 0; i < tmplen; i++)
  153. ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
  154. }
  155. static void dm9000_inblk_32bit(void *data_ptr, int count)
  156. {
  157. int i;
  158. u32 tmplen = (count + 3) / 4;
  159. for (i = 0; i < tmplen; i++)
  160. ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
  161. }
  162. static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
  163. {
  164. u32 tmpdata;
  165. DM9000_outb(DM9000_MRCMD, DM9000_IO);
  166. tmpdata = DM9000_inl(DM9000_DATA);
  167. *RxStatus = __le16_to_cpu(tmpdata);
  168. *RxLen = __le16_to_cpu(tmpdata >> 16);
  169. }
  170. static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
  171. {
  172. DM9000_outb(DM9000_MRCMD, DM9000_IO);
  173. *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
  174. *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
  175. }
  176. static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
  177. {
  178. DM9000_outb(DM9000_MRCMD, DM9000_IO);
  179. *RxStatus =
  180. __le16_to_cpu(DM9000_inb(DM9000_DATA) +
  181. (DM9000_inb(DM9000_DATA) << 8));
  182. *RxLen =
  183. __le16_to_cpu(DM9000_inb(DM9000_DATA) +
  184. (DM9000_inb(DM9000_DATA) << 8));
  185. }
  186. /*
  187. Search DM9000 board, allocate space and register it
  188. */
  189. int
  190. dm9000_probe(void)
  191. {
  192. u32 id_val;
  193. id_val = DM9000_ior(DM9000_VIDL);
  194. id_val |= DM9000_ior(DM9000_VIDH) << 8;
  195. id_val |= DM9000_ior(DM9000_PIDL) << 16;
  196. id_val |= DM9000_ior(DM9000_PIDH) << 24;
  197. if (id_val == DM9000_ID) {
  198. printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
  199. id_val);
  200. return 0;
  201. } else {
  202. printf("dm9000 not found at 0x%08x id: 0x%08x\n",
  203. CONFIG_DM9000_BASE, id_val);
  204. return -1;
  205. }
  206. }
  207. /* General Purpose dm9000 reset routine */
  208. static void
  209. dm9000_reset(void)
  210. {
  211. DM9000_DBG("resetting DM9000\n");
  212. /* Reset DM9000,
  213. see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
  214. /* DEBUG: Make all GPIO0 outputs, all others inputs */
  215. DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
  216. /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
  217. DM9000_iow(DM9000_GPR, 0);
  218. /* Step 2: Software reset */
  219. DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
  220. do {
  221. DM9000_DBG("resetting the DM9000, 1st reset\n");
  222. udelay(25); /* Wait at least 20 us */
  223. } while (DM9000_ior(DM9000_NCR) & 1);
  224. DM9000_iow(DM9000_NCR, 0);
  225. DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
  226. do {
  227. DM9000_DBG("resetting the DM9000, 2nd reset\n");
  228. udelay(25); /* Wait at least 20 us */
  229. } while (DM9000_ior(DM9000_NCR) & 1);
  230. /* Check whether the ethernet controller is present */
  231. if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
  232. (DM9000_ior(DM9000_PIDH) != 0x90))
  233. printf("ERROR: resetting DM9000 -> not responding\n");
  234. }
  235. /* Initialize dm9000 board
  236. */
  237. static int dm9000_init(struct eth_device *dev, bd_t *bd)
  238. {
  239. int i, oft, lnk;
  240. u8 io_mode;
  241. struct board_info *db = &dm9000_info;
  242. DM9000_DBG("%s\n", __func__);
  243. /* RESET device */
  244. dm9000_reset();
  245. if (dm9000_probe() < 0)
  246. return -1;
  247. /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
  248. io_mode = DM9000_ior(DM9000_ISR) >> 6;
  249. switch (io_mode) {
  250. case 0x0: /* 16-bit mode */
  251. printf("DM9000: running in 16 bit mode\n");
  252. db->outblk = dm9000_outblk_16bit;
  253. db->inblk = dm9000_inblk_16bit;
  254. db->rx_status = dm9000_rx_status_16bit;
  255. break;
  256. case 0x01: /* 32-bit mode */
  257. printf("DM9000: running in 32 bit mode\n");
  258. db->outblk = dm9000_outblk_32bit;
  259. db->inblk = dm9000_inblk_32bit;
  260. db->rx_status = dm9000_rx_status_32bit;
  261. break;
  262. case 0x02: /* 8 bit mode */
  263. printf("DM9000: running in 8 bit mode\n");
  264. db->outblk = dm9000_outblk_8bit;
  265. db->inblk = dm9000_inblk_8bit;
  266. db->rx_status = dm9000_rx_status_8bit;
  267. break;
  268. default:
  269. /* Assume 8 bit mode, will probably not work anyway */
  270. printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
  271. db->outblk = dm9000_outblk_8bit;
  272. db->inblk = dm9000_inblk_8bit;
  273. db->rx_status = dm9000_rx_status_8bit;
  274. break;
  275. }
  276. /* Program operating register, only internal phy supported */
  277. DM9000_iow(DM9000_NCR, 0x0);
  278. /* TX Polling clear */
  279. DM9000_iow(DM9000_TCR, 0);
  280. /* Less 3Kb, 200us */
  281. DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
  282. /* Flow Control : High/Low Water */
  283. DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
  284. /* SH FIXME: This looks strange! Flow Control */
  285. DM9000_iow(DM9000_FCR, 0x0);
  286. /* Special Mode */
  287. DM9000_iow(DM9000_SMCR, 0);
  288. /* clear TX status */
  289. DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
  290. /* Clear interrupt status */
  291. DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
  292. printf("MAC: %pM\n", dev->enetaddr);
  293. if (!is_valid_ethaddr(dev->enetaddr)) {
  294. printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
  295. }
  296. /* fill device MAC address registers */
  297. for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
  298. DM9000_iow(oft, dev->enetaddr[i]);
  299. for (i = 0, oft = 0x16; i < 8; i++, oft++)
  300. DM9000_iow(oft, 0xff);
  301. /* read back mac, just to be sure */
  302. for (i = 0, oft = 0x10; i < 6; i++, oft++)
  303. DM9000_DBG("%02x:", DM9000_ior(oft));
  304. DM9000_DBG("\n");
  305. /* Activate DM9000 */
  306. /* RX enable */
  307. DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
  308. /* Enable TX/RX interrupt mask */
  309. DM9000_iow(DM9000_IMR, IMR_PAR);
  310. i = 0;
  311. while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
  312. udelay(1000);
  313. i++;
  314. if (i == 10000) {
  315. printf("could not establish link\n");
  316. return 0;
  317. }
  318. }
  319. /* see what we've got */
  320. lnk = dm9000_phy_read(17) >> 12;
  321. printf("operating at ");
  322. switch (lnk) {
  323. case 1:
  324. printf("10M half duplex ");
  325. break;
  326. case 2:
  327. printf("10M full duplex ");
  328. break;
  329. case 4:
  330. printf("100M half duplex ");
  331. break;
  332. case 8:
  333. printf("100M full duplex ");
  334. break;
  335. default:
  336. printf("unknown: %d ", lnk);
  337. break;
  338. }
  339. printf("mode\n");
  340. return 0;
  341. }
  342. /*
  343. Hardware start transmission.
  344. Send a packet to media from the upper layer.
  345. */
  346. static int dm9000_send(struct eth_device *netdev, void *packet, int length)
  347. {
  348. int tmo;
  349. struct board_info *db = &dm9000_info;
  350. DM9000_DMP_PACKET(__func__ , packet, length);
  351. DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
  352. /* Move data to DM9000 TX RAM */
  353. DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
  354. /* push the data to the TX-fifo */
  355. (db->outblk)(packet, length);
  356. /* Set TX length to DM9000 */
  357. DM9000_iow(DM9000_TXPLL, length & 0xff);
  358. DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
  359. /* Issue TX polling command */
  360. DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
  361. /* wait for end of transmission */
  362. tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  363. while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
  364. !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
  365. if (get_timer(0) >= tmo) {
  366. printf("transmission timeout\n");
  367. break;
  368. }
  369. }
  370. DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
  371. DM9000_DBG("transmit done\n\n");
  372. return 0;
  373. }
  374. /*
  375. Stop the interface.
  376. The interface is stopped when it is brought.
  377. */
  378. static void dm9000_halt(struct eth_device *netdev)
  379. {
  380. DM9000_DBG("%s\n", __func__);
  381. /* RESET devie */
  382. dm9000_phy_write(0, 0x8000); /* PHY RESET */
  383. DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
  384. DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
  385. DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
  386. }
  387. /*
  388. Received a packet and pass to upper layer
  389. */
  390. static int dm9000_rx(struct eth_device *netdev)
  391. {
  392. u8 rxbyte;
  393. u8 *rdptr = (u8 *)net_rx_packets[0];
  394. u16 RxStatus, RxLen = 0;
  395. struct board_info *db = &dm9000_info;
  396. /* Check packet ready or not, we must check
  397. the ISR status first for DM9000A */
  398. if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
  399. return 0;
  400. DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
  401. /* There is _at least_ 1 package in the fifo, read them all */
  402. for (;;) {
  403. DM9000_ior(DM9000_MRCMDX); /* Dummy read */
  404. /* Get most updated data,
  405. only look at bits 0:1, See application notes DM9000 */
  406. rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
  407. /* Status check: this byte must be 0 or 1 */
  408. if (rxbyte > DM9000_PKT_RDY) {
  409. DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
  410. DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
  411. printf("DM9000 error: status check fail: 0x%x\n",
  412. rxbyte);
  413. return 0;
  414. }
  415. if (rxbyte != DM9000_PKT_RDY)
  416. return 0; /* No packet received, ignore */
  417. DM9000_DBG("receiving packet\n");
  418. /* A packet ready now & Get status/length */
  419. (db->rx_status)(&RxStatus, &RxLen);
  420. DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
  421. /* Move data from DM9000 */
  422. /* Read received packet from RX SRAM */
  423. (db->inblk)(rdptr, RxLen);
  424. if ((RxStatus & 0xbf00) || (RxLen < 0x40)
  425. || (RxLen > DM9000_PKT_MAX)) {
  426. if (RxStatus & 0x100) {
  427. printf("rx fifo error\n");
  428. }
  429. if (RxStatus & 0x200) {
  430. printf("rx crc error\n");
  431. }
  432. if (RxStatus & 0x8000) {
  433. printf("rx length error\n");
  434. }
  435. if (RxLen > DM9000_PKT_MAX) {
  436. printf("rx length too big\n");
  437. dm9000_reset();
  438. }
  439. } else {
  440. DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
  441. DM9000_DBG("passing packet to upper layer\n");
  442. net_process_received_packet(net_rx_packets[0], RxLen);
  443. }
  444. }
  445. return 0;
  446. }
  447. /*
  448. Read a word data from SROM
  449. */
  450. #if !defined(CONFIG_DM9000_NO_SROM)
  451. void dm9000_read_srom_word(int offset, u8 *to)
  452. {
  453. DM9000_iow(DM9000_EPAR, offset);
  454. DM9000_iow(DM9000_EPCR, 0x4);
  455. udelay(8000);
  456. DM9000_iow(DM9000_EPCR, 0x0);
  457. to[0] = DM9000_ior(DM9000_EPDRL);
  458. to[1] = DM9000_ior(DM9000_EPDRH);
  459. }
  460. void dm9000_write_srom_word(int offset, u16 val)
  461. {
  462. DM9000_iow(DM9000_EPAR, offset);
  463. DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
  464. DM9000_iow(DM9000_EPDRL, (val & 0xff));
  465. DM9000_iow(DM9000_EPCR, 0x12);
  466. udelay(8000);
  467. DM9000_iow(DM9000_EPCR, 0);
  468. }
  469. #endif
  470. static void dm9000_get_enetaddr(struct eth_device *dev)
  471. {
  472. #if !defined(CONFIG_DM9000_NO_SROM)
  473. int i;
  474. for (i = 0; i < 3; i++)
  475. dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
  476. #endif
  477. }
  478. /*
  479. Read a byte from I/O port
  480. */
  481. static u8
  482. DM9000_ior(int reg)
  483. {
  484. DM9000_outb(reg, DM9000_IO);
  485. return DM9000_inb(DM9000_DATA);
  486. }
  487. /*
  488. Write a byte to I/O port
  489. */
  490. static void
  491. DM9000_iow(int reg, u8 value)
  492. {
  493. DM9000_outb(reg, DM9000_IO);
  494. DM9000_outb(value, DM9000_DATA);
  495. }
  496. /*
  497. Read a word from phyxcer
  498. */
  499. static u16
  500. dm9000_phy_read(int reg)
  501. {
  502. u16 val;
  503. /* Fill the phyxcer register into REG_0C */
  504. DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
  505. DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
  506. udelay(100); /* Wait read complete */
  507. DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
  508. val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
  509. /* The read data keeps on REG_0D & REG_0E */
  510. DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
  511. return val;
  512. }
  513. /*
  514. Write a word to phyxcer
  515. */
  516. static void
  517. dm9000_phy_write(int reg, u16 value)
  518. {
  519. /* Fill the phyxcer register into REG_0C */
  520. DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
  521. /* Fill the written data into REG_0D & REG_0E */
  522. DM9000_iow(DM9000_EPDRL, (value & 0xff));
  523. DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
  524. DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
  525. udelay(500); /* Wait write complete */
  526. DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
  527. DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
  528. }
  529. int dm9000_initialize(bd_t *bis)
  530. {
  531. struct eth_device *dev = &(dm9000_info.netdev);
  532. /* Load MAC address from EEPROM */
  533. dm9000_get_enetaddr(dev);
  534. dev->init = dm9000_init;
  535. dev->halt = dm9000_halt;
  536. dev->send = dm9000_send;
  537. dev->recv = dm9000_rx;
  538. strcpy(dev->name, "dm9000");
  539. eth_register(dev);
  540. return 0;
  541. }