designware.c 17 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * Designware ethernet IP driver for U-Boot
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <miiphy.h>
  14. #include <malloc.h>
  15. #include <pci.h>
  16. #include <linux/compiler.h>
  17. #include <linux/err.h>
  18. #include <asm/io.h>
  19. #include "designware.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  22. {
  23. struct eth_mac_regs *mac_p = bus->priv;
  24. ulong start;
  25. u16 miiaddr;
  26. int timeout = CONFIG_MDIO_TIMEOUT;
  27. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  28. ((reg << MIIREGSHIFT) & MII_REGMSK);
  29. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  30. start = get_timer(0);
  31. while (get_timer(start) < timeout) {
  32. if (!(readl(&mac_p->miiaddr) & MII_BUSY))
  33. return readl(&mac_p->miidata);
  34. udelay(10);
  35. };
  36. return -ETIMEDOUT;
  37. }
  38. static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  39. u16 val)
  40. {
  41. struct eth_mac_regs *mac_p = bus->priv;
  42. ulong start;
  43. u16 miiaddr;
  44. int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
  45. writel(val, &mac_p->miidata);
  46. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  47. ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
  48. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  49. start = get_timer(0);
  50. while (get_timer(start) < timeout) {
  51. if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
  52. ret = 0;
  53. break;
  54. }
  55. udelay(10);
  56. };
  57. return ret;
  58. }
  59. static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
  60. {
  61. struct mii_dev *bus = mdio_alloc();
  62. if (!bus) {
  63. printf("Failed to allocate MDIO bus\n");
  64. return -ENOMEM;
  65. }
  66. bus->read = dw_mdio_read;
  67. bus->write = dw_mdio_write;
  68. snprintf(bus->name, sizeof(bus->name), "%s", name);
  69. bus->priv = (void *)mac_regs_p;
  70. return mdio_register(bus);
  71. }
  72. static void tx_descs_init(struct dw_eth_dev *priv)
  73. {
  74. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  75. struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
  76. char *txbuffs = &priv->txbuffs[0];
  77. struct dmamacdescr *desc_p;
  78. u32 idx;
  79. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  80. desc_p = &desc_table_p[idx];
  81. desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
  82. desc_p->dmamac_next = &desc_table_p[idx + 1];
  83. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  84. desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
  85. DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
  86. DESC_TXSTS_TXCHECKINSCTRL |
  87. DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
  88. desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
  89. desc_p->dmamac_cntl = 0;
  90. desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
  91. #else
  92. desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
  93. desc_p->txrx_status = 0;
  94. #endif
  95. }
  96. /* Correcting the last pointer of the chain */
  97. desc_p->dmamac_next = &desc_table_p[0];
  98. /* Flush all Tx buffer descriptors at once */
  99. flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
  100. (unsigned int)priv->tx_mac_descrtable +
  101. sizeof(priv->tx_mac_descrtable));
  102. writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
  103. priv->tx_currdescnum = 0;
  104. }
  105. static void rx_descs_init(struct dw_eth_dev *priv)
  106. {
  107. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  108. struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
  109. char *rxbuffs = &priv->rxbuffs[0];
  110. struct dmamacdescr *desc_p;
  111. u32 idx;
  112. /* Before passing buffers to GMAC we need to make sure zeros
  113. * written there right after "priv" structure allocation were
  114. * flushed into RAM.
  115. * Otherwise there's a chance to get some of them flushed in RAM when
  116. * GMAC is already pushing data to RAM via DMA. This way incoming from
  117. * GMAC data will be corrupted. */
  118. flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
  119. RX_TOTAL_BUFSIZE);
  120. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  121. desc_p = &desc_table_p[idx];
  122. desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
  123. desc_p->dmamac_next = &desc_table_p[idx + 1];
  124. desc_p->dmamac_cntl =
  125. (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
  126. DESC_RXCTRL_RXCHAIN;
  127. desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  128. }
  129. /* Correcting the last pointer of the chain */
  130. desc_p->dmamac_next = &desc_table_p[0];
  131. /* Flush all Rx buffer descriptors at once */
  132. flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
  133. (unsigned int)priv->rx_mac_descrtable +
  134. sizeof(priv->rx_mac_descrtable));
  135. writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
  136. priv->rx_currdescnum = 0;
  137. }
  138. static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
  139. {
  140. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  141. u32 macid_lo, macid_hi;
  142. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  143. (mac_id[3] << 24);
  144. macid_hi = mac_id[4] + (mac_id[5] << 8);
  145. writel(macid_hi, &mac_p->macaddr0hi);
  146. writel(macid_lo, &mac_p->macaddr0lo);
  147. return 0;
  148. }
  149. static void dw_adjust_link(struct eth_mac_regs *mac_p,
  150. struct phy_device *phydev)
  151. {
  152. u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
  153. if (!phydev->link) {
  154. printf("%s: No link.\n", phydev->dev->name);
  155. return;
  156. }
  157. if (phydev->speed != 1000)
  158. conf |= MII_PORTSELECT;
  159. if (phydev->speed == 100)
  160. conf |= FES_100;
  161. if (phydev->duplex)
  162. conf |= FULLDPLXMODE;
  163. writel(conf, &mac_p->conf);
  164. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  165. (phydev->duplex) ? "full" : "half",
  166. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  167. }
  168. static void _dw_eth_halt(struct dw_eth_dev *priv)
  169. {
  170. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  171. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  172. writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
  173. writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
  174. phy_shutdown(priv->phydev);
  175. }
  176. static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
  177. {
  178. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  179. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  180. unsigned int start;
  181. int ret;
  182. writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
  183. start = get_timer(0);
  184. while (readl(&dma_p->busmode) & DMAMAC_SRST) {
  185. if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
  186. printf("DMA reset timeout\n");
  187. return -ETIMEDOUT;
  188. }
  189. mdelay(100);
  190. };
  191. /*
  192. * Soft reset above clears HW address registers.
  193. * So we have to set it here once again.
  194. */
  195. _dw_write_hwaddr(priv, enetaddr);
  196. rx_descs_init(priv);
  197. tx_descs_init(priv);
  198. writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
  199. #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
  200. writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
  201. &dma_p->opmode);
  202. #else
  203. writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
  204. &dma_p->opmode);
  205. #endif
  206. writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
  207. #ifdef CONFIG_DW_AXI_BURST_LEN
  208. writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
  209. #endif
  210. /* Start up the PHY */
  211. ret = phy_startup(priv->phydev);
  212. if (ret) {
  213. printf("Could not initialize PHY %s\n",
  214. priv->phydev->dev->name);
  215. return ret;
  216. }
  217. dw_adjust_link(mac_p, priv->phydev);
  218. if (!priv->phydev->link)
  219. return -EIO;
  220. writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
  221. return 0;
  222. }
  223. static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
  224. {
  225. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  226. u32 desc_num = priv->tx_currdescnum;
  227. struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
  228. uint32_t desc_start = (uint32_t)desc_p;
  229. uint32_t desc_end = desc_start +
  230. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  231. uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
  232. uint32_t data_end = data_start +
  233. roundup(length, ARCH_DMA_MINALIGN);
  234. /*
  235. * Strictly we only need to invalidate the "txrx_status" field
  236. * for the following check, but on some platforms we cannot
  237. * invalidate only 4 bytes, so we flush the entire descriptor,
  238. * which is 16 bytes in total. This is safe because the
  239. * individual descriptors in the array are each aligned to
  240. * ARCH_DMA_MINALIGN and padded appropriately.
  241. */
  242. invalidate_dcache_range(desc_start, desc_end);
  243. /* Check if the descriptor is owned by CPU */
  244. if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
  245. printf("CPU not owner of tx frame\n");
  246. return -EPERM;
  247. }
  248. memcpy(desc_p->dmamac_addr, packet, length);
  249. /* Flush data to be sent */
  250. flush_dcache_range(data_start, data_end);
  251. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  252. desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
  253. desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
  254. DESC_TXCTRL_SIZE1MASK;
  255. desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
  256. desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
  257. #else
  258. desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
  259. DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
  260. DESC_TXCTRL_TXFIRST;
  261. desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
  262. #endif
  263. /* Flush modified buffer descriptor */
  264. flush_dcache_range(desc_start, desc_end);
  265. /* Test the wrap-around condition. */
  266. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  267. desc_num = 0;
  268. priv->tx_currdescnum = desc_num;
  269. /* Start the transmission */
  270. writel(POLL_DATA, &dma_p->txpolldemand);
  271. return 0;
  272. }
  273. static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
  274. {
  275. u32 status, desc_num = priv->rx_currdescnum;
  276. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  277. int length = -EAGAIN;
  278. uint32_t desc_start = (uint32_t)desc_p;
  279. uint32_t desc_end = desc_start +
  280. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  281. uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
  282. uint32_t data_end;
  283. /* Invalidate entire buffer descriptor */
  284. invalidate_dcache_range(desc_start, desc_end);
  285. status = desc_p->txrx_status;
  286. /* Check if the owner is the CPU */
  287. if (!(status & DESC_RXSTS_OWNBYDMA)) {
  288. length = (status & DESC_RXSTS_FRMLENMSK) >>
  289. DESC_RXSTS_FRMLENSHFT;
  290. /* Invalidate received data */
  291. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  292. invalidate_dcache_range(data_start, data_end);
  293. *packetp = desc_p->dmamac_addr;
  294. }
  295. return length;
  296. }
  297. static int _dw_free_pkt(struct dw_eth_dev *priv)
  298. {
  299. u32 desc_num = priv->rx_currdescnum;
  300. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  301. uint32_t desc_start = (uint32_t)desc_p;
  302. uint32_t desc_end = desc_start +
  303. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  304. /*
  305. * Make the current descriptor valid again and go to
  306. * the next one
  307. */
  308. desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
  309. /* Flush only status field - others weren't changed */
  310. flush_dcache_range(desc_start, desc_end);
  311. /* Test the wrap-around condition. */
  312. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  313. desc_num = 0;
  314. priv->rx_currdescnum = desc_num;
  315. return 0;
  316. }
  317. static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
  318. {
  319. struct phy_device *phydev;
  320. int mask = 0xffffffff;
  321. #ifdef CONFIG_PHY_ADDR
  322. mask = 1 << CONFIG_PHY_ADDR;
  323. #endif
  324. phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
  325. if (!phydev)
  326. return -ENODEV;
  327. phy_connect_dev(phydev, dev);
  328. phydev->supported &= PHY_GBIT_FEATURES;
  329. phydev->advertising = phydev->supported;
  330. priv->phydev = phydev;
  331. phy_config(phydev);
  332. return 0;
  333. }
  334. #ifndef CONFIG_DM_ETH
  335. static int dw_eth_init(struct eth_device *dev, bd_t *bis)
  336. {
  337. return _dw_eth_init(dev->priv, dev->enetaddr);
  338. }
  339. static int dw_eth_send(struct eth_device *dev, void *packet, int length)
  340. {
  341. return _dw_eth_send(dev->priv, packet, length);
  342. }
  343. static int dw_eth_recv(struct eth_device *dev)
  344. {
  345. uchar *packet;
  346. int length;
  347. length = _dw_eth_recv(dev->priv, &packet);
  348. if (length == -EAGAIN)
  349. return 0;
  350. net_process_received_packet(packet, length);
  351. _dw_free_pkt(dev->priv);
  352. return 0;
  353. }
  354. static void dw_eth_halt(struct eth_device *dev)
  355. {
  356. return _dw_eth_halt(dev->priv);
  357. }
  358. static int dw_write_hwaddr(struct eth_device *dev)
  359. {
  360. return _dw_write_hwaddr(dev->priv, dev->enetaddr);
  361. }
  362. int designware_initialize(ulong base_addr, u32 interface)
  363. {
  364. struct eth_device *dev;
  365. struct dw_eth_dev *priv;
  366. dev = (struct eth_device *) malloc(sizeof(struct eth_device));
  367. if (!dev)
  368. return -ENOMEM;
  369. /*
  370. * Since the priv structure contains the descriptors which need a strict
  371. * buswidth alignment, memalign is used to allocate memory
  372. */
  373. priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
  374. sizeof(struct dw_eth_dev));
  375. if (!priv) {
  376. free(dev);
  377. return -ENOMEM;
  378. }
  379. memset(dev, 0, sizeof(struct eth_device));
  380. memset(priv, 0, sizeof(struct dw_eth_dev));
  381. sprintf(dev->name, "dwmac.%lx", base_addr);
  382. dev->iobase = (int)base_addr;
  383. dev->priv = priv;
  384. priv->dev = dev;
  385. priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
  386. priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
  387. DW_DMA_BASE_OFFSET);
  388. dev->init = dw_eth_init;
  389. dev->send = dw_eth_send;
  390. dev->recv = dw_eth_recv;
  391. dev->halt = dw_eth_halt;
  392. dev->write_hwaddr = dw_write_hwaddr;
  393. eth_register(dev);
  394. priv->interface = interface;
  395. dw_mdio_init(dev->name, priv->mac_regs_p);
  396. priv->bus = miiphy_get_dev_by_name(dev->name);
  397. return dw_phy_init(priv, dev);
  398. }
  399. #endif
  400. #ifdef CONFIG_DM_ETH
  401. static int designware_eth_start(struct udevice *dev)
  402. {
  403. struct eth_pdata *pdata = dev_get_platdata(dev);
  404. return _dw_eth_init(dev->priv, pdata->enetaddr);
  405. }
  406. static int designware_eth_send(struct udevice *dev, void *packet, int length)
  407. {
  408. struct dw_eth_dev *priv = dev_get_priv(dev);
  409. return _dw_eth_send(priv, packet, length);
  410. }
  411. static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  412. {
  413. struct dw_eth_dev *priv = dev_get_priv(dev);
  414. return _dw_eth_recv(priv, packetp);
  415. }
  416. static int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
  417. int length)
  418. {
  419. struct dw_eth_dev *priv = dev_get_priv(dev);
  420. return _dw_free_pkt(priv);
  421. }
  422. static void designware_eth_stop(struct udevice *dev)
  423. {
  424. struct dw_eth_dev *priv = dev_get_priv(dev);
  425. return _dw_eth_halt(priv);
  426. }
  427. static int designware_eth_write_hwaddr(struct udevice *dev)
  428. {
  429. struct eth_pdata *pdata = dev_get_platdata(dev);
  430. struct dw_eth_dev *priv = dev_get_priv(dev);
  431. return _dw_write_hwaddr(priv, pdata->enetaddr);
  432. }
  433. static int designware_eth_bind(struct udevice *dev)
  434. {
  435. #ifdef CONFIG_DM_PCI
  436. static int num_cards;
  437. char name[20];
  438. /* Create a unique device name for PCI type devices */
  439. if (device_is_on_pci_bus(dev)) {
  440. sprintf(name, "eth_designware#%u", num_cards++);
  441. device_set_name(dev, name);
  442. }
  443. #endif
  444. return 0;
  445. }
  446. static int designware_eth_probe(struct udevice *dev)
  447. {
  448. struct eth_pdata *pdata = dev_get_platdata(dev);
  449. struct dw_eth_dev *priv = dev_get_priv(dev);
  450. u32 iobase = pdata->iobase;
  451. int ret;
  452. #ifdef CONFIG_DM_PCI
  453. /*
  454. * If we are on PCI bus, either directly attached to a PCI root port,
  455. * or via a PCI bridge, fill in platdata before we probe the hardware.
  456. */
  457. if (device_is_on_pci_bus(dev)) {
  458. pci_dev_t bdf = dm_pci_get_bdf(dev);
  459. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
  460. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  461. iobase = pci_mem_to_phys(bdf, iobase);
  462. pdata->iobase = iobase;
  463. pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
  464. }
  465. #endif
  466. debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
  467. priv->mac_regs_p = (struct eth_mac_regs *)iobase;
  468. priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
  469. priv->interface = pdata->phy_interface;
  470. dw_mdio_init(dev->name, priv->mac_regs_p);
  471. priv->bus = miiphy_get_dev_by_name(dev->name);
  472. ret = dw_phy_init(priv, dev);
  473. debug("%s, ret=%d\n", __func__, ret);
  474. return ret;
  475. }
  476. static int designware_eth_remove(struct udevice *dev)
  477. {
  478. struct dw_eth_dev *priv = dev_get_priv(dev);
  479. free(priv->phydev);
  480. mdio_unregister(priv->bus);
  481. mdio_free(priv->bus);
  482. return 0;
  483. }
  484. static const struct eth_ops designware_eth_ops = {
  485. .start = designware_eth_start,
  486. .send = designware_eth_send,
  487. .recv = designware_eth_recv,
  488. .free_pkt = designware_eth_free_pkt,
  489. .stop = designware_eth_stop,
  490. .write_hwaddr = designware_eth_write_hwaddr,
  491. };
  492. static int designware_eth_ofdata_to_platdata(struct udevice *dev)
  493. {
  494. struct eth_pdata *pdata = dev_get_platdata(dev);
  495. const char *phy_mode;
  496. pdata->iobase = dev_get_addr(dev);
  497. pdata->phy_interface = -1;
  498. phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
  499. if (phy_mode)
  500. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  501. if (pdata->phy_interface == -1) {
  502. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  503. return -EINVAL;
  504. }
  505. return 0;
  506. }
  507. static const struct udevice_id designware_eth_ids[] = {
  508. { .compatible = "allwinner,sun7i-a20-gmac" },
  509. { .compatible = "altr,socfpga-stmmac" },
  510. { }
  511. };
  512. U_BOOT_DRIVER(eth_designware) = {
  513. .name = "eth_designware",
  514. .id = UCLASS_ETH,
  515. .of_match = designware_eth_ids,
  516. .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
  517. .bind = designware_eth_bind,
  518. .probe = designware_eth_probe,
  519. .remove = designware_eth_remove,
  520. .ops = &designware_eth_ops,
  521. .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
  522. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  523. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  524. };
  525. static struct pci_device_id supported[] = {
  526. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
  527. { }
  528. };
  529. U_BOOT_PCI_DEVICE(eth_designware, supported);
  530. #endif