davinci_emac.c 23 KB

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  1. /*
  2. * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
  3. *
  4. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  5. *
  6. * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
  7. * follows:
  8. *
  9. * ----------------------------------------------------------------------------
  10. *
  11. * dm644x_emac.c
  12. *
  13. * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
  14. *
  15. * Copyright (C) 2005 Texas Instruments.
  16. *
  17. * ----------------------------------------------------------------------------
  18. *
  19. * SPDX-License-Identifier: GPL-2.0+
  20. *
  21. * Modifications:
  22. * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
  23. * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
  24. */
  25. #include <common.h>
  26. #include <command.h>
  27. #include <net.h>
  28. #include <miiphy.h>
  29. #include <malloc.h>
  30. #include <netdev.h>
  31. #include <linux/compiler.h>
  32. #include <asm/arch/emac_defs.h>
  33. #include <asm/io.h>
  34. #include "davinci_emac.h"
  35. unsigned int emac_dbg = 0;
  36. #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
  37. #ifdef EMAC_HW_RAM_ADDR
  38. static inline unsigned long BD_TO_HW(unsigned long x)
  39. {
  40. if (x == 0)
  41. return 0;
  42. return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
  43. }
  44. static inline unsigned long HW_TO_BD(unsigned long x)
  45. {
  46. if (x == 0)
  47. return 0;
  48. return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
  49. }
  50. #else
  51. #define BD_TO_HW(x) (x)
  52. #define HW_TO_BD(x) (x)
  53. #endif
  54. #ifdef DAVINCI_EMAC_GIG_ENABLE
  55. #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
  56. #else
  57. #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
  58. #endif
  59. #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
  60. #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
  61. EMAC_MDIO_CLOCK_FREQ) - 1)
  62. #endif
  63. static void davinci_eth_mdio_enable(void);
  64. static int gen_init_phy(int phy_addr);
  65. static int gen_is_phy_connected(int phy_addr);
  66. static int gen_get_link_speed(int phy_addr);
  67. static int gen_auto_negotiate(int phy_addr);
  68. void eth_mdio_enable(void)
  69. {
  70. davinci_eth_mdio_enable();
  71. }
  72. /* EMAC Addresses */
  73. static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
  74. static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
  75. static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
  76. /* EMAC descriptors */
  77. static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
  78. static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  79. static volatile emac_desc *emac_rx_active_head = 0;
  80. static volatile emac_desc *emac_rx_active_tail = 0;
  81. static int emac_rx_queue_active = 0;
  82. /* Receive packet buffers */
  83. static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
  84. __aligned(ARCH_DMA_MINALIGN);
  85. #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
  86. #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
  87. #endif
  88. /* PHY address for a discovered PHY (0xff - not found) */
  89. static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
  90. /* number of PHY found active */
  91. static u_int8_t num_phy;
  92. phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
  93. static inline void davinci_flush_rx_descs(void)
  94. {
  95. /* flush the whole RX descs area */
  96. flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
  97. EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  98. }
  99. static inline void davinci_invalidate_rx_descs(void)
  100. {
  101. /* invalidate the whole RX descs area */
  102. invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
  103. EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  104. }
  105. static inline void davinci_flush_desc(emac_desc *desc)
  106. {
  107. flush_dcache_range((unsigned long)desc,
  108. (unsigned long)desc + sizeof(*desc));
  109. }
  110. static int davinci_eth_set_mac_addr(struct eth_device *dev)
  111. {
  112. unsigned long mac_hi;
  113. unsigned long mac_lo;
  114. /*
  115. * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
  116. * receive)
  117. * Using channel 0 only - other channels are disabled
  118. * */
  119. writel(0, &adap_emac->MACINDEX);
  120. mac_hi = (dev->enetaddr[3] << 24) |
  121. (dev->enetaddr[2] << 16) |
  122. (dev->enetaddr[1] << 8) |
  123. (dev->enetaddr[0]);
  124. mac_lo = (dev->enetaddr[5] << 8) |
  125. (dev->enetaddr[4]);
  126. writel(mac_hi, &adap_emac->MACADDRHI);
  127. #if defined(DAVINCI_EMAC_VERSION2)
  128. writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
  129. &adap_emac->MACADDRLO);
  130. #else
  131. writel(mac_lo, &adap_emac->MACADDRLO);
  132. #endif
  133. writel(0, &adap_emac->MACHASH1);
  134. writel(0, &adap_emac->MACHASH2);
  135. /* Set source MAC address - REQUIRED */
  136. writel(mac_hi, &adap_emac->MACSRCADDRHI);
  137. writel(mac_lo, &adap_emac->MACSRCADDRLO);
  138. return 0;
  139. }
  140. static void davinci_eth_mdio_enable(void)
  141. {
  142. u_int32_t clkdiv;
  143. clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
  144. writel((clkdiv & 0xff) |
  145. MDIO_CONTROL_ENABLE |
  146. MDIO_CONTROL_FAULT |
  147. MDIO_CONTROL_FAULT_ENABLE,
  148. &adap_mdio->CONTROL);
  149. while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
  150. ;
  151. }
  152. /*
  153. * Tries to find an active connected PHY. Returns 1 if address if found.
  154. * If no active PHY (or more than one PHY) found returns 0.
  155. * Sets active_phy_addr variable.
  156. */
  157. static int davinci_eth_phy_detect(void)
  158. {
  159. u_int32_t phy_act_state;
  160. int i;
  161. int j;
  162. unsigned int count = 0;
  163. for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
  164. active_phy_addr[i] = 0xff;
  165. udelay(1000);
  166. phy_act_state = readl(&adap_mdio->ALIVE);
  167. if (phy_act_state == 0)
  168. return 0; /* No active PHYs */
  169. debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
  170. for (i = 0, j = 0; i < 32; i++)
  171. if (phy_act_state & (1 << i)) {
  172. count++;
  173. if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
  174. active_phy_addr[j++] = i;
  175. } else {
  176. printf("%s: to many PHYs detected.\n",
  177. __func__);
  178. count = 0;
  179. break;
  180. }
  181. }
  182. num_phy = count;
  183. return count;
  184. }
  185. /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
  186. int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
  187. {
  188. int tmp;
  189. while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
  190. ;
  191. writel(MDIO_USERACCESS0_GO |
  192. MDIO_USERACCESS0_WRITE_READ |
  193. ((reg_num & 0x1f) << 21) |
  194. ((phy_addr & 0x1f) << 16),
  195. &adap_mdio->USERACCESS0);
  196. /* Wait for command to complete */
  197. while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
  198. ;
  199. if (tmp & MDIO_USERACCESS0_ACK) {
  200. *data = tmp & 0xffff;
  201. return(1);
  202. }
  203. *data = -1;
  204. return(0);
  205. }
  206. /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
  207. int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
  208. {
  209. while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
  210. ;
  211. writel(MDIO_USERACCESS0_GO |
  212. MDIO_USERACCESS0_WRITE_WRITE |
  213. ((reg_num & 0x1f) << 21) |
  214. ((phy_addr & 0x1f) << 16) |
  215. (data & 0xffff),
  216. &adap_mdio->USERACCESS0);
  217. /* Wait for command to complete */
  218. while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
  219. ;
  220. return(1);
  221. }
  222. /* PHY functions for a generic PHY */
  223. static int gen_init_phy(int phy_addr)
  224. {
  225. int ret = 1;
  226. if (gen_get_link_speed(phy_addr)) {
  227. /* Try another time */
  228. ret = gen_get_link_speed(phy_addr);
  229. }
  230. return(ret);
  231. }
  232. static int gen_is_phy_connected(int phy_addr)
  233. {
  234. u_int16_t dummy;
  235. return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
  236. }
  237. static int get_active_phy(void)
  238. {
  239. int i;
  240. for (i = 0; i < num_phy; i++)
  241. if (phy[i].get_link_speed(active_phy_addr[i]))
  242. return i;
  243. return -1; /* Return error if no link */
  244. }
  245. static int gen_get_link_speed(int phy_addr)
  246. {
  247. u_int16_t tmp;
  248. if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
  249. (tmp & 0x04)) {
  250. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  251. defined(CONFIG_MACH_DAVINCI_DA850_EVM)
  252. davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
  253. /* Speed doesn't matter, there is no setting for it in EMAC. */
  254. if (tmp & (LPA_100FULL | LPA_10FULL)) {
  255. /* set EMAC for Full Duplex */
  256. writel(EMAC_MACCONTROL_MIIEN_ENABLE |
  257. EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
  258. &adap_emac->MACCONTROL);
  259. } else {
  260. /*set EMAC for Half Duplex */
  261. writel(EMAC_MACCONTROL_MIIEN_ENABLE,
  262. &adap_emac->MACCONTROL);
  263. }
  264. if (tmp & (LPA_100FULL | LPA_100HALF))
  265. writel(readl(&adap_emac->MACCONTROL) |
  266. EMAC_MACCONTROL_RMIISPEED_100,
  267. &adap_emac->MACCONTROL);
  268. else
  269. writel(readl(&adap_emac->MACCONTROL) &
  270. ~EMAC_MACCONTROL_RMIISPEED_100,
  271. &adap_emac->MACCONTROL);
  272. #endif
  273. return(1);
  274. }
  275. return(0);
  276. }
  277. static int gen_auto_negotiate(int phy_addr)
  278. {
  279. u_int16_t tmp;
  280. u_int16_t val;
  281. unsigned long cntr = 0;
  282. if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
  283. return 0;
  284. val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
  285. BMCR_SPEED100;
  286. davinci_eth_phy_write(phy_addr, MII_BMCR, val);
  287. if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
  288. return 0;
  289. val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
  290. ADVERTISE_10HALF);
  291. davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
  292. if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
  293. return(0);
  294. /* Restart Auto_negotiation */
  295. tmp |= BMCR_ANRESTART;
  296. davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
  297. /*check AutoNegotiate complete */
  298. do {
  299. udelay(40000);
  300. if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
  301. return 0;
  302. if (tmp & BMSR_ANEGCOMPLETE)
  303. break;
  304. cntr++;
  305. } while (cntr < 200);
  306. if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
  307. return(0);
  308. if (!(tmp & BMSR_ANEGCOMPLETE))
  309. return(0);
  310. return(gen_get_link_speed(phy_addr));
  311. }
  312. /* End of generic PHY functions */
  313. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  314. static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
  315. {
  316. return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
  317. }
  318. static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
  319. {
  320. return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
  321. }
  322. #endif
  323. static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
  324. {
  325. u_int16_t data;
  326. if (davinci_eth_phy_read(phy_addr, 0, &data)) {
  327. if (data & (1 << 6)) { /* speed selection MSB */
  328. /*
  329. * Check if link detected is giga-bit
  330. * If Gigabit mode detected, enable gigbit in MAC
  331. */
  332. writel(readl(&adap_emac->MACCONTROL) |
  333. EMAC_MACCONTROL_GIGFORCE |
  334. EMAC_MACCONTROL_GIGABIT_ENABLE,
  335. &adap_emac->MACCONTROL);
  336. }
  337. }
  338. }
  339. /* Eth device open */
  340. static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
  341. {
  342. dv_reg_p addr;
  343. u_int32_t clkdiv, cnt;
  344. volatile emac_desc *rx_desc;
  345. int index;
  346. debug_emac("+ emac_open\n");
  347. /* Reset EMAC module and disable interrupts in wrapper */
  348. writel(1, &adap_emac->SOFTRESET);
  349. while (readl(&adap_emac->SOFTRESET) != 0)
  350. ;
  351. #if defined(DAVINCI_EMAC_VERSION2)
  352. writel(1, &adap_ewrap->softrst);
  353. while (readl(&adap_ewrap->softrst) != 0)
  354. ;
  355. #else
  356. writel(0, &adap_ewrap->EWCTL);
  357. for (cnt = 0; cnt < 5; cnt++) {
  358. clkdiv = readl(&adap_ewrap->EWCTL);
  359. }
  360. #endif
  361. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  362. defined(CONFIG_MACH_DAVINCI_DA850_EVM)
  363. adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
  364. adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
  365. adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
  366. #endif
  367. rx_desc = emac_rx_desc;
  368. writel(1, &adap_emac->TXCONTROL);
  369. writel(1, &adap_emac->RXCONTROL);
  370. davinci_eth_set_mac_addr(dev);
  371. /* Set DMA 8 TX / 8 RX Head pointers to 0 */
  372. addr = &adap_emac->TX0HDP;
  373. for(cnt = 0; cnt < 16; cnt++)
  374. writel(0, addr++);
  375. addr = &adap_emac->RX0HDP;
  376. for(cnt = 0; cnt < 16; cnt++)
  377. writel(0, addr++);
  378. /* Clear Statistics (do this before setting MacControl register) */
  379. addr = &adap_emac->RXGOODFRAMES;
  380. for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
  381. writel(0, addr++);
  382. /* No multicast addressing */
  383. writel(0, &adap_emac->MACHASH1);
  384. writel(0, &adap_emac->MACHASH2);
  385. /* Create RX queue and set receive process in place */
  386. emac_rx_active_head = emac_rx_desc;
  387. for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
  388. rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
  389. rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
  390. rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
  391. rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
  392. rx_desc++;
  393. }
  394. /* Finalize the rx desc list */
  395. rx_desc--;
  396. rx_desc->next = 0;
  397. emac_rx_active_tail = rx_desc;
  398. emac_rx_queue_active = 1;
  399. davinci_flush_rx_descs();
  400. /* Enable TX/RX */
  401. writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
  402. writel(0, &adap_emac->RXBUFFEROFFSET);
  403. /*
  404. * No fancy configs - Use this for promiscous debug
  405. * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
  406. */
  407. writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
  408. /* Enable ch 0 only */
  409. writel(1, &adap_emac->RXUNICASTSET);
  410. /* Enable MII interface and Full duplex mode */
  411. #if defined(CONFIG_SOC_DA8XX) || \
  412. (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
  413. writel((EMAC_MACCONTROL_MIIEN_ENABLE |
  414. EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
  415. EMAC_MACCONTROL_RMIISPEED_100),
  416. &adap_emac->MACCONTROL);
  417. #else
  418. writel((EMAC_MACCONTROL_MIIEN_ENABLE |
  419. EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
  420. &adap_emac->MACCONTROL);
  421. #endif
  422. /* Init MDIO & get link state */
  423. clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
  424. writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
  425. &adap_mdio->CONTROL);
  426. /* We need to wait for MDIO to start */
  427. udelay(1000);
  428. index = get_active_phy();
  429. if (index == -1)
  430. return(0);
  431. emac_gigabit_enable(active_phy_addr[index]);
  432. /* Start receive process */
  433. writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
  434. debug_emac("- emac_open\n");
  435. return(1);
  436. }
  437. /* EMAC Channel Teardown */
  438. static void davinci_eth_ch_teardown(int ch)
  439. {
  440. dv_reg dly = 0xff;
  441. dv_reg cnt;
  442. debug_emac("+ emac_ch_teardown\n");
  443. if (ch == EMAC_CH_TX) {
  444. /* Init TX channel teardown */
  445. writel(0, &adap_emac->TXTEARDOWN);
  446. do {
  447. /*
  448. * Wait here for Tx teardown completion interrupt to
  449. * occur. Note: A task delay can be called here to pend
  450. * rather than occupying CPU cycles - anyway it has
  451. * been found that teardown takes very few cpu cycles
  452. * and does not affect functionality
  453. */
  454. dly--;
  455. udelay(1);
  456. if (dly == 0)
  457. break;
  458. cnt = readl(&adap_emac->TX0CP);
  459. } while (cnt != 0xfffffffc);
  460. writel(cnt, &adap_emac->TX0CP);
  461. writel(0, &adap_emac->TX0HDP);
  462. } else {
  463. /* Init RX channel teardown */
  464. writel(0, &adap_emac->RXTEARDOWN);
  465. do {
  466. /*
  467. * Wait here for Rx teardown completion interrupt to
  468. * occur. Note: A task delay can be called here to pend
  469. * rather than occupying CPU cycles - anyway it has
  470. * been found that teardown takes very few cpu cycles
  471. * and does not affect functionality
  472. */
  473. dly--;
  474. udelay(1);
  475. if (dly == 0)
  476. break;
  477. cnt = readl(&adap_emac->RX0CP);
  478. } while (cnt != 0xfffffffc);
  479. writel(cnt, &adap_emac->RX0CP);
  480. writel(0, &adap_emac->RX0HDP);
  481. }
  482. debug_emac("- emac_ch_teardown\n");
  483. }
  484. /* Eth device close */
  485. static void davinci_eth_close(struct eth_device *dev)
  486. {
  487. debug_emac("+ emac_close\n");
  488. davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
  489. if (readl(&adap_emac->RXCONTROL) & 1)
  490. davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
  491. /* Reset EMAC module and disable interrupts in wrapper */
  492. writel(1, &adap_emac->SOFTRESET);
  493. #if defined(DAVINCI_EMAC_VERSION2)
  494. writel(1, &adap_ewrap->softrst);
  495. #else
  496. writel(0, &adap_ewrap->EWCTL);
  497. #endif
  498. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  499. defined(CONFIG_MACH_DAVINCI_DA850_EVM)
  500. adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
  501. adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
  502. adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
  503. #endif
  504. debug_emac("- emac_close\n");
  505. }
  506. static int tx_send_loop = 0;
  507. /*
  508. * This function sends a single packet on the network and returns
  509. * positive number (number of bytes transmitted) or negative for error
  510. */
  511. static int davinci_eth_send_packet (struct eth_device *dev,
  512. void *packet, int length)
  513. {
  514. int ret_status = -1;
  515. int index;
  516. tx_send_loop = 0;
  517. index = get_active_phy();
  518. if (index == -1) {
  519. printf(" WARN: emac_send_packet: No link\n");
  520. return (ret_status);
  521. }
  522. emac_gigabit_enable(active_phy_addr[index]);
  523. /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
  524. if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
  525. length = EMAC_MIN_ETHERNET_PKT_SIZE;
  526. }
  527. /* Populate the TX descriptor */
  528. emac_tx_desc->next = 0;
  529. emac_tx_desc->buffer = (u_int8_t *) packet;
  530. emac_tx_desc->buff_off_len = (length & 0xffff);
  531. emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
  532. EMAC_CPPI_SOP_BIT |
  533. EMAC_CPPI_OWNERSHIP_BIT |
  534. EMAC_CPPI_EOP_BIT);
  535. flush_dcache_range((unsigned long)packet,
  536. (unsigned long)packet + length);
  537. davinci_flush_desc(emac_tx_desc);
  538. /* Send the packet */
  539. writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
  540. /* Wait for packet to complete or link down */
  541. while (1) {
  542. if (!phy[index].get_link_speed(active_phy_addr[index])) {
  543. davinci_eth_ch_teardown (EMAC_CH_TX);
  544. return (ret_status);
  545. }
  546. emac_gigabit_enable(active_phy_addr[index]);
  547. if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
  548. ret_status = length;
  549. break;
  550. }
  551. tx_send_loop++;
  552. }
  553. return (ret_status);
  554. }
  555. /*
  556. * This function handles receipt of a packet from the network
  557. */
  558. static int davinci_eth_rcv_packet (struct eth_device *dev)
  559. {
  560. volatile emac_desc *rx_curr_desc;
  561. volatile emac_desc *curr_desc;
  562. volatile emac_desc *tail_desc;
  563. int status, ret = -1;
  564. davinci_invalidate_rx_descs();
  565. rx_curr_desc = emac_rx_active_head;
  566. status = rx_curr_desc->pkt_flag_len;
  567. if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
  568. if (status & EMAC_CPPI_RX_ERROR_FRAME) {
  569. /* Error in packet - discard it and requeue desc */
  570. printf ("WARN: emac_rcv_pkt: Error in packet\n");
  571. } else {
  572. unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
  573. invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
  574. net_process_received_packet(
  575. rx_curr_desc->buffer,
  576. rx_curr_desc->buff_off_len & 0xffff);
  577. ret = rx_curr_desc->buff_off_len & 0xffff;
  578. }
  579. /* Ack received packet descriptor */
  580. writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
  581. curr_desc = rx_curr_desc;
  582. emac_rx_active_head =
  583. (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
  584. if (status & EMAC_CPPI_EOQ_BIT) {
  585. if (emac_rx_active_head) {
  586. writel(BD_TO_HW((ulong)emac_rx_active_head),
  587. &adap_emac->RX0HDP);
  588. } else {
  589. emac_rx_queue_active = 0;
  590. printf ("INFO:emac_rcv_packet: RX Queue not active\n");
  591. }
  592. }
  593. /* Recycle RX descriptor */
  594. rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
  595. rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
  596. rx_curr_desc->next = 0;
  597. davinci_flush_desc(rx_curr_desc);
  598. if (emac_rx_active_head == 0) {
  599. printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
  600. emac_rx_active_head = curr_desc;
  601. emac_rx_active_tail = curr_desc;
  602. if (emac_rx_queue_active != 0) {
  603. writel(BD_TO_HW((ulong)emac_rx_active_head),
  604. &adap_emac->RX0HDP);
  605. printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
  606. emac_rx_queue_active = 1;
  607. }
  608. } else {
  609. tail_desc = emac_rx_active_tail;
  610. emac_rx_active_tail = curr_desc;
  611. tail_desc->next = BD_TO_HW((ulong) curr_desc);
  612. status = tail_desc->pkt_flag_len;
  613. if (status & EMAC_CPPI_EOQ_BIT) {
  614. davinci_flush_desc(tail_desc);
  615. writel(BD_TO_HW((ulong)curr_desc),
  616. &adap_emac->RX0HDP);
  617. status &= ~EMAC_CPPI_EOQ_BIT;
  618. tail_desc->pkt_flag_len = status;
  619. }
  620. davinci_flush_desc(tail_desc);
  621. }
  622. return (ret);
  623. }
  624. return (0);
  625. }
  626. /*
  627. * This function initializes the emac hardware. It does NOT initialize
  628. * EMAC modules power or pin multiplexors, that is done by board_init()
  629. * much earlier in bootup process. Returns 1 on success, 0 otherwise.
  630. */
  631. int davinci_emac_initialize(void)
  632. {
  633. u_int32_t phy_id;
  634. u_int16_t tmp;
  635. int i;
  636. int ret;
  637. struct eth_device *dev;
  638. dev = malloc(sizeof *dev);
  639. if (dev == NULL)
  640. return -1;
  641. memset(dev, 0, sizeof *dev);
  642. strcpy(dev->name, "DaVinci-EMAC");
  643. dev->iobase = 0;
  644. dev->init = davinci_eth_open;
  645. dev->halt = davinci_eth_close;
  646. dev->send = davinci_eth_send_packet;
  647. dev->recv = davinci_eth_rcv_packet;
  648. dev->write_hwaddr = davinci_eth_set_mac_addr;
  649. eth_register(dev);
  650. davinci_eth_mdio_enable();
  651. /* let the EMAC detect the PHYs */
  652. udelay(5000);
  653. for (i = 0; i < 256; i++) {
  654. if (readl(&adap_mdio->ALIVE))
  655. break;
  656. udelay(1000);
  657. }
  658. if (i >= 256) {
  659. printf("No ETH PHY detected!!!\n");
  660. return(0);
  661. }
  662. /* Find if PHY(s) is/are connected */
  663. ret = davinci_eth_phy_detect();
  664. if (!ret)
  665. return(0);
  666. else
  667. debug_emac(" %d ETH PHY detected\n", ret);
  668. /* Get PHY ID and initialize phy_ops for a detected PHY */
  669. for (i = 0; i < num_phy; i++) {
  670. if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
  671. &tmp)) {
  672. active_phy_addr[i] = 0xff;
  673. continue;
  674. }
  675. phy_id = (tmp << 16) & 0xffff0000;
  676. if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
  677. &tmp)) {
  678. active_phy_addr[i] = 0xff;
  679. continue;
  680. }
  681. phy_id |= tmp & 0x0000ffff;
  682. switch (phy_id) {
  683. #ifdef PHY_KSZ8873
  684. case PHY_KSZ8873:
  685. sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
  686. active_phy_addr[i]);
  687. phy[i].init = ksz8873_init_phy;
  688. phy[i].is_phy_connected = ksz8873_is_phy_connected;
  689. phy[i].get_link_speed = ksz8873_get_link_speed;
  690. phy[i].auto_negotiate = ksz8873_auto_negotiate;
  691. break;
  692. #endif
  693. #ifdef PHY_LXT972
  694. case PHY_LXT972:
  695. sprintf(phy[i].name, "LXT972 @ 0x%02x",
  696. active_phy_addr[i]);
  697. phy[i].init = lxt972_init_phy;
  698. phy[i].is_phy_connected = lxt972_is_phy_connected;
  699. phy[i].get_link_speed = lxt972_get_link_speed;
  700. phy[i].auto_negotiate = lxt972_auto_negotiate;
  701. break;
  702. #endif
  703. #ifdef PHY_DP83848
  704. case PHY_DP83848:
  705. sprintf(phy[i].name, "DP83848 @ 0x%02x",
  706. active_phy_addr[i]);
  707. phy[i].init = dp83848_init_phy;
  708. phy[i].is_phy_connected = dp83848_is_phy_connected;
  709. phy[i].get_link_speed = dp83848_get_link_speed;
  710. phy[i].auto_negotiate = dp83848_auto_negotiate;
  711. break;
  712. #endif
  713. #ifdef PHY_ET1011C
  714. case PHY_ET1011C:
  715. sprintf(phy[i].name, "ET1011C @ 0x%02x",
  716. active_phy_addr[i]);
  717. phy[i].init = gen_init_phy;
  718. phy[i].is_phy_connected = gen_is_phy_connected;
  719. phy[i].get_link_speed = et1011c_get_link_speed;
  720. phy[i].auto_negotiate = gen_auto_negotiate;
  721. break;
  722. #endif
  723. default:
  724. sprintf(phy[i].name, "GENERIC @ 0x%02x",
  725. active_phy_addr[i]);
  726. phy[i].init = gen_init_phy;
  727. phy[i].is_phy_connected = gen_is_phy_connected;
  728. phy[i].get_link_speed = gen_get_link_speed;
  729. phy[i].auto_negotiate = gen_auto_negotiate;
  730. }
  731. debug("Ethernet PHY: %s\n", phy[i].name);
  732. miiphy_register(phy[i].name, davinci_mii_phy_read,
  733. davinci_mii_phy_write);
  734. }
  735. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  736. defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
  737. !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
  738. for (i = 0; i < num_phy; i++) {
  739. if (phy[i].is_phy_connected(i))
  740. phy[i].auto_negotiate(i);
  741. }
  742. #endif
  743. return(1);
  744. }