at91_emac.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508
  1. /*
  2. * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
  3. * Jens Scharsig (esw@bus-elektronik.de)
  4. *
  5. * (C) Copyright 2003
  6. * Author : Hamid Ikdoumi (Atmel)
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/at91_emac.h>
  13. #include <asm/arch/at91_pmc.h>
  14. #include <asm/arch/at91_pio.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <malloc.h>
  18. #include <miiphy.h>
  19. #include <linux/mii.h>
  20. #undef MII_DEBUG
  21. #undef ET_DEBUG
  22. #if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
  23. #error AT91 EMAC supports max 1024 RX buffers. \
  24. Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
  25. #endif
  26. #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
  27. #define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
  28. #endif
  29. /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
  30. #if (AT91C_MASTER_CLOCK > 80000000)
  31. #define HCLK_DIV AT91_EMAC_CFG_MCLK_64
  32. #elif (AT91C_MASTER_CLOCK > 40000000)
  33. #define HCLK_DIV AT91_EMAC_CFG_MCLK_32
  34. #elif (AT91C_MASTER_CLOCK > 20000000)
  35. #define HCLK_DIV AT91_EMAC_CFG_MCLK_16
  36. #else
  37. #define HCLK_DIV AT91_EMAC_CFG_MCLK_8
  38. #endif
  39. #ifdef ET_DEBUG
  40. #define DEBUG_AT91EMAC 1
  41. #else
  42. #define DEBUG_AT91EMAC 0
  43. #endif
  44. #ifdef MII_DEBUG
  45. #define DEBUG_AT91PHY 1
  46. #else
  47. #define DEBUG_AT91PHY 0
  48. #endif
  49. #ifndef CONFIG_DRIVER_AT91EMAC_QUIET
  50. #define VERBOSEP 1
  51. #else
  52. #define VERBOSEP 0
  53. #endif
  54. #define RBF_ADDR 0xfffffffc
  55. #define RBF_OWNER (1<<0)
  56. #define RBF_WRAP (1<<1)
  57. #define RBF_BROADCAST (1<<31)
  58. #define RBF_MULTICAST (1<<30)
  59. #define RBF_UNICAST (1<<29)
  60. #define RBF_EXTERNAL (1<<28)
  61. #define RBF_UNKNOWN (1<<27)
  62. #define RBF_SIZE 0x07ff
  63. #define RBF_LOCAL4 (1<<26)
  64. #define RBF_LOCAL3 (1<<25)
  65. #define RBF_LOCAL2 (1<<24)
  66. #define RBF_LOCAL1 (1<<23)
  67. #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
  68. #define RBF_FRAMELEN 0x600
  69. typedef struct {
  70. unsigned long addr, size;
  71. } rbf_t;
  72. typedef struct {
  73. rbf_t rbfdt[RBF_FRAMEMAX];
  74. unsigned long rbindex;
  75. } emac_device;
  76. void at91emac_EnableMDIO(at91_emac_t *at91mac)
  77. {
  78. /* Mac CTRL reg set for MDIO enable */
  79. writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
  80. }
  81. void at91emac_DisableMDIO(at91_emac_t *at91mac)
  82. {
  83. /* Mac CTRL reg set for MDIO disable */
  84. writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
  85. }
  86. int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
  87. unsigned char reg, unsigned short *value)
  88. {
  89. unsigned long netstat;
  90. at91emac_EnableMDIO(at91mac);
  91. writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
  92. AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
  93. AT91_EMAC_MAN_PHYA(addr),
  94. &at91mac->man);
  95. do {
  96. netstat = readl(&at91mac->sr);
  97. debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
  98. } while (!(netstat & AT91_EMAC_SR_IDLE));
  99. *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
  100. at91emac_DisableMDIO(at91mac);
  101. debug_cond(DEBUG_AT91PHY,
  102. "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
  103. return 0;
  104. }
  105. int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
  106. unsigned char reg, unsigned short value)
  107. {
  108. unsigned long netstat;
  109. debug_cond(DEBUG_AT91PHY,
  110. "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
  111. at91emac_EnableMDIO(at91mac);
  112. writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
  113. AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
  114. AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
  115. &at91mac->man);
  116. do {
  117. netstat = readl(&at91mac->sr);
  118. debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
  119. } while (!(netstat & AT91_EMAC_SR_IDLE));
  120. at91emac_DisableMDIO(at91mac);
  121. return 0;
  122. }
  123. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  124. at91_emac_t *get_emacbase_by_name(const char *devname)
  125. {
  126. struct eth_device *netdev;
  127. netdev = eth_get_dev_by_name(devname);
  128. return (at91_emac_t *) netdev->iobase;
  129. }
  130. int at91emac_mii_read(const char *devname, unsigned char addr,
  131. unsigned char reg, unsigned short *value)
  132. {
  133. at91_emac_t *emac;
  134. emac = get_emacbase_by_name(devname);
  135. at91emac_read(emac , addr, reg, value);
  136. return 0;
  137. }
  138. int at91emac_mii_write(const char *devname, unsigned char addr,
  139. unsigned char reg, unsigned short value)
  140. {
  141. at91_emac_t *emac;
  142. emac = get_emacbase_by_name(devname);
  143. at91emac_write(emac, addr, reg, value);
  144. return 0;
  145. }
  146. #endif
  147. static int at91emac_phy_reset(struct eth_device *netdev)
  148. {
  149. int i;
  150. u16 status, adv;
  151. at91_emac_t *emac;
  152. emac = (at91_emac_t *) netdev->iobase;
  153. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  154. at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  155. MII_ADVERTISE, adv);
  156. debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
  157. at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
  158. (BMCR_ANENABLE | BMCR_ANRESTART));
  159. for (i = 0; i < 30000; i++) {
  160. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  161. MII_BMSR, &status);
  162. if (status & BMSR_ANEGCOMPLETE)
  163. break;
  164. udelay(100);
  165. }
  166. if (status & BMSR_ANEGCOMPLETE) {
  167. debug_cond(VERBOSEP,
  168. "%s: Autonegotiation complete\n", netdev->name);
  169. } else {
  170. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  171. netdev->name, status);
  172. return -1;
  173. }
  174. return 0;
  175. }
  176. static int at91emac_phy_init(struct eth_device *netdev)
  177. {
  178. u16 phy_id, status, adv, lpa;
  179. int media, speed, duplex;
  180. int i;
  181. at91_emac_t *emac;
  182. emac = (at91_emac_t *) netdev->iobase;
  183. /* Check if the PHY is up to snuff... */
  184. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  185. MII_PHYSID1, &phy_id);
  186. if (phy_id == 0xffff) {
  187. printf("%s: No PHY present\n", netdev->name);
  188. return -1;
  189. }
  190. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  191. MII_BMSR, &status);
  192. if (!(status & BMSR_LSTATUS)) {
  193. /* Try to re-negotiate if we don't have link already. */
  194. if (at91emac_phy_reset(netdev))
  195. return -2;
  196. for (i = 0; i < 100000 / 100; i++) {
  197. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  198. MII_BMSR, &status);
  199. if (status & BMSR_LSTATUS)
  200. break;
  201. udelay(100);
  202. }
  203. }
  204. if (!(status & BMSR_LSTATUS)) {
  205. debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
  206. return -3;
  207. } else {
  208. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  209. MII_ADVERTISE, &adv);
  210. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  211. MII_LPA, &lpa);
  212. media = mii_nway_result(lpa & adv);
  213. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  214. ? 1 : 0);
  215. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  216. debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
  217. netdev->name,
  218. speed ? "100" : "10",
  219. duplex ? "full" : "half");
  220. }
  221. return 0;
  222. }
  223. int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
  224. {
  225. unsigned short stat1;
  226. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
  227. if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
  228. return -1;
  229. if (stat1 & BMSR_100FULL) {
  230. /*set Emac for 100BaseTX and Full Duplex */
  231. writel(readl(&emac->cfg) |
  232. AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
  233. &emac->cfg);
  234. return 0;
  235. }
  236. if (stat1 & BMSR_10FULL) {
  237. /*set MII for 10BaseT and Full Duplex */
  238. writel((readl(&emac->cfg) &
  239. ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
  240. ) | AT91_EMAC_CFG_FD,
  241. &emac->cfg);
  242. return 0;
  243. }
  244. if (stat1 & BMSR_100HALF) {
  245. /*set MII for 100BaseTX and Half Duplex */
  246. writel((readl(&emac->cfg) &
  247. ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
  248. ) | AT91_EMAC_CFG_SPD,
  249. &emac->cfg);
  250. return 0;
  251. }
  252. if (stat1 & BMSR_10HALF) {
  253. /*set MII for 10BaseT and Half Duplex */
  254. writel((readl(&emac->cfg) &
  255. ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
  256. &emac->cfg);
  257. return 0;
  258. }
  259. return 0;
  260. }
  261. static int at91emac_init(struct eth_device *netdev, bd_t *bd)
  262. {
  263. int i;
  264. u32 value;
  265. emac_device *dev;
  266. at91_emac_t *emac;
  267. at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
  268. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  269. emac = (at91_emac_t *) netdev->iobase;
  270. dev = (emac_device *) netdev->priv;
  271. /* PIO Disable Register */
  272. value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC |
  273. ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 |
  274. ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS |
  275. ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 |
  276. ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
  277. writel(value, &pio->pioa.pdr);
  278. writel(value, &pio->pioa.asr);
  279. #ifdef CONFIG_RMII
  280. value = ATMEL_PMX_BA_ERXCK;
  281. #else
  282. value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL |
  283. ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 |
  284. ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER |
  285. ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
  286. #endif
  287. writel(value, &pio->piob.pdr);
  288. writel(value, &pio->piob.bsr);
  289. writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  290. writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
  291. /* Init Ethernet buffers */
  292. for (i = 0; i < RBF_FRAMEMAX; i++) {
  293. dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i];
  294. dev->rbfdt[i].size = 0;
  295. }
  296. dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
  297. dev->rbindex = 0;
  298. writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
  299. writel(readl(&emac->rsr) &
  300. ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
  301. &emac->rsr);
  302. value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
  303. HCLK_DIV;
  304. #ifdef CONFIG_RMII
  305. value |= AT91_EMAC_CFG_RMII;
  306. #endif
  307. writel(value, &emac->cfg);
  308. writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
  309. &emac->ctl);
  310. if (!at91emac_phy_init(netdev)) {
  311. at91emac_UpdateLinkSpeed(emac);
  312. return 0;
  313. }
  314. return -1;
  315. }
  316. static void at91emac_halt(struct eth_device *netdev)
  317. {
  318. at91_emac_t *emac;
  319. emac = (at91_emac_t *) netdev->iobase;
  320. writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
  321. &emac->ctl);
  322. debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
  323. }
  324. static int at91emac_send(struct eth_device *netdev, void *packet, int length)
  325. {
  326. at91_emac_t *emac;
  327. emac = (at91_emac_t *) netdev->iobase;
  328. while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
  329. ;
  330. writel((u32) packet, &emac->tar);
  331. writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
  332. while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
  333. ;
  334. debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
  335. writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
  336. return 0;
  337. }
  338. static int at91emac_recv(struct eth_device *netdev)
  339. {
  340. emac_device *dev;
  341. at91_emac_t *emac;
  342. rbf_t *rbfp;
  343. int size;
  344. emac = (at91_emac_t *) netdev->iobase;
  345. dev = (emac_device *) netdev->priv;
  346. rbfp = &dev->rbfdt[dev->rbindex];
  347. while (rbfp->addr & RBF_OWNER) {
  348. size = rbfp->size & RBF_SIZE;
  349. net_process_received_packet(net_rx_packets[dev->rbindex], size);
  350. debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
  351. dev->rbindex, size, rbfp->addr);
  352. rbfp->addr &= ~RBF_OWNER;
  353. rbfp->size = 0;
  354. if (dev->rbindex < (RBF_FRAMEMAX-1))
  355. dev->rbindex++;
  356. else
  357. dev->rbindex = 0;
  358. rbfp = &(dev->rbfdt[dev->rbindex]);
  359. if (!(rbfp->addr & RBF_OWNER))
  360. writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
  361. &emac->rsr);
  362. }
  363. if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
  364. /* EMAC silicon bug 41.3.1 workaround 1 */
  365. writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
  366. writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
  367. dev->rbindex = 0;
  368. printf("%s: reset receiver (EMAC dead lock bug)\n",
  369. netdev->name);
  370. }
  371. return 0;
  372. }
  373. static int at91emac_write_hwaddr(struct eth_device *netdev)
  374. {
  375. at91_emac_t *emac;
  376. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  377. emac = (at91_emac_t *) netdev->iobase;
  378. writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  379. debug_cond(DEBUG_AT91EMAC,
  380. "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
  381. netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
  382. netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
  383. writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
  384. netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
  385. &emac->sa2l);
  386. writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
  387. debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
  388. readl(&emac->sa2h), readl(&emac->sa2l));
  389. return 0;
  390. }
  391. int at91emac_register(bd_t *bis, unsigned long iobase)
  392. {
  393. emac_device *emac;
  394. emac_device *emacfix;
  395. struct eth_device *dev;
  396. if (iobase == 0)
  397. iobase = ATMEL_BASE_EMAC;
  398. emac = malloc(sizeof(*emac)+512);
  399. if (emac == NULL)
  400. return -1;
  401. dev = malloc(sizeof(*dev));
  402. if (dev == NULL) {
  403. free(emac);
  404. return -1;
  405. }
  406. /* alignment as per Errata (64 bytes) is insufficient! */
  407. emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
  408. memset(emacfix, 0, sizeof(emac_device));
  409. memset(dev, 0, sizeof(*dev));
  410. strcpy(dev->name, "emac");
  411. dev->iobase = iobase;
  412. dev->priv = emacfix;
  413. dev->init = at91emac_init;
  414. dev->halt = at91emac_halt;
  415. dev->send = at91emac_send;
  416. dev->recv = at91emac_recv;
  417. dev->write_hwaddr = at91emac_write_hwaddr;
  418. eth_register(dev);
  419. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  420. miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
  421. #endif
  422. return 1;
  423. }