sata_dwc.c 46 KB

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  1. /*
  2. * sata_dwc.c
  3. *
  4. * Synopsys DesignWare Cores (DWC) SATA host driver
  5. *
  6. * Author: Mark Miesfeld <mmiesfeld@amcc.com>
  7. *
  8. * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
  9. * Copyright 2008 DENX Software Engineering
  10. *
  11. * Based on versions provided by AMCC and Synopsys which are:
  12. * Copyright 2006 Applied Micro Circuits Corporation
  13. * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
  14. *
  15. * SPDX-License-Identifier: GPL-2.0+
  16. */
  17. /*
  18. * SATA support based on the chip canyonlands.
  19. *
  20. * 04-17-2009
  21. * The local version of this driver for the canyonlands board
  22. * does not use interrupts but polls the chip instead.
  23. */
  24. #include <common.h>
  25. #include <command.h>
  26. #include <pci.h>
  27. #include <asm/processor.h>
  28. #include <asm/errno.h>
  29. #include <asm/io.h>
  30. #include <malloc.h>
  31. #include <ata.h>
  32. #include <sata.h>
  33. #include <linux/ctype.h>
  34. #include "sata_dwc.h"
  35. #define DMA_NUM_CHANS 1
  36. #define DMA_NUM_CHAN_REGS 8
  37. #define AHB_DMA_BRST_DFLT 16
  38. struct dmareg {
  39. u32 low;
  40. u32 high;
  41. };
  42. struct dma_chan_regs {
  43. struct dmareg sar;
  44. struct dmareg dar;
  45. struct dmareg llp;
  46. struct dmareg ctl;
  47. struct dmareg sstat;
  48. struct dmareg dstat;
  49. struct dmareg sstatar;
  50. struct dmareg dstatar;
  51. struct dmareg cfg;
  52. struct dmareg sgr;
  53. struct dmareg dsr;
  54. };
  55. struct dma_interrupt_regs {
  56. struct dmareg tfr;
  57. struct dmareg block;
  58. struct dmareg srctran;
  59. struct dmareg dsttran;
  60. struct dmareg error;
  61. };
  62. struct ahb_dma_regs {
  63. struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
  64. struct dma_interrupt_regs interrupt_raw;
  65. struct dma_interrupt_regs interrupt_status;
  66. struct dma_interrupt_regs interrupt_mask;
  67. struct dma_interrupt_regs interrupt_clear;
  68. struct dmareg statusInt;
  69. struct dmareg rq_srcreg;
  70. struct dmareg rq_dstreg;
  71. struct dmareg rq_sgl_srcreg;
  72. struct dmareg rq_sgl_dstreg;
  73. struct dmareg rq_lst_srcreg;
  74. struct dmareg rq_lst_dstreg;
  75. struct dmareg dma_cfg;
  76. struct dmareg dma_chan_en;
  77. struct dmareg dma_id;
  78. struct dmareg dma_test;
  79. struct dmareg res1;
  80. struct dmareg res2;
  81. /* DMA Comp Params
  82. * Param 6 = dma_param[0], Param 5 = dma_param[1],
  83. * Param 4 = dma_param[2] ...
  84. */
  85. struct dmareg dma_params[6];
  86. };
  87. #define DMA_EN 0x00000001
  88. #define DMA_DI 0x00000000
  89. #define DMA_CHANNEL(ch) (0x00000001 << (ch))
  90. #define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
  91. ((0x000000001 << (ch)) << 8))
  92. #define DMA_DISABLE_CHAN(ch) (0x00000000 | \
  93. ((0x000000001 << (ch)) << 8))
  94. #define SATA_DWC_MAX_PORTS 1
  95. #define SATA_DWC_SCR_OFFSET 0x24
  96. #define SATA_DWC_REG_OFFSET 0x64
  97. struct sata_dwc_regs {
  98. u32 fptagr;
  99. u32 fpbor;
  100. u32 fptcr;
  101. u32 dmacr;
  102. u32 dbtsr;
  103. u32 intpr;
  104. u32 intmr;
  105. u32 errmr;
  106. u32 llcr;
  107. u32 phycr;
  108. u32 physr;
  109. u32 rxbistpd;
  110. u32 rxbistpd1;
  111. u32 rxbistpd2;
  112. u32 txbistpd;
  113. u32 txbistpd1;
  114. u32 txbistpd2;
  115. u32 bistcr;
  116. u32 bistfctr;
  117. u32 bistsr;
  118. u32 bistdecr;
  119. u32 res[15];
  120. u32 testr;
  121. u32 versionr;
  122. u32 idr;
  123. u32 unimpl[192];
  124. u32 dmadr[256];
  125. };
  126. #define SATA_DWC_TXFIFO_DEPTH 0x01FF
  127. #define SATA_DWC_RXFIFO_DEPTH 0x01FF
  128. #define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH)
  129. #define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \
  130. SATA_DWC_RXFIFO_DEPTH) << 16)
  131. #define SATA_DWC_INTPR_DMAT 0x00000001
  132. #define SATA_DWC_INTPR_NEWFP 0x00000002
  133. #define SATA_DWC_INTPR_PMABRT 0x00000004
  134. #define SATA_DWC_INTPR_ERR 0x00000008
  135. #define SATA_DWC_INTPR_NEWBIST 0x00000010
  136. #define SATA_DWC_INTPR_IPF 0x10000000
  137. #define SATA_DWC_INTMR_DMATM 0x00000001
  138. #define SATA_DWC_INTMR_NEWFPM 0x00000002
  139. #define SATA_DWC_INTMR_PMABRTM 0x00000004
  140. #define SATA_DWC_INTMR_ERRM 0x00000008
  141. #define SATA_DWC_INTMR_NEWBISTM 0x00000010
  142. #define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
  143. #define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
  144. #define SATA_DWC_QCMD_MAX 32
  145. #define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
  146. #define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \
  147. (ap)->private_data
  148. struct sata_dwc_device {
  149. struct device *dev;
  150. struct ata_probe_ent *pe;
  151. struct ata_host *host;
  152. u8 *reg_base;
  153. struct sata_dwc_regs *sata_dwc_regs;
  154. int irq_dma;
  155. };
  156. struct sata_dwc_device_port {
  157. struct sata_dwc_device *hsdev;
  158. int cmd_issued[SATA_DWC_QCMD_MAX];
  159. u32 dma_chan[SATA_DWC_QCMD_MAX];
  160. int dma_pending[SATA_DWC_QCMD_MAX];
  161. };
  162. enum {
  163. SATA_DWC_CMD_ISSUED_NOT = 0,
  164. SATA_DWC_CMD_ISSUED_PEND = 1,
  165. SATA_DWC_CMD_ISSUED_EXEC = 2,
  166. SATA_DWC_CMD_ISSUED_NODATA = 3,
  167. SATA_DWC_DMA_PENDING_NONE = 0,
  168. SATA_DWC_DMA_PENDING_TX = 1,
  169. SATA_DWC_DMA_PENDING_RX = 2,
  170. };
  171. #define msleep(a) udelay(a * 1000)
  172. #define ssleep(a) msleep(a * 1000)
  173. static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100);
  174. enum sata_dev_state {
  175. SATA_INIT = 0,
  176. SATA_READY = 1,
  177. SATA_NODEVICE = 2,
  178. SATA_ERROR = 3,
  179. };
  180. enum sata_dev_state dev_state = SATA_INIT;
  181. static struct ahb_dma_regs *sata_dma_regs = 0;
  182. static struct ata_host *phost;
  183. static struct ata_port ap;
  184. static struct ata_port *pap = &ap;
  185. static struct ata_device ata_device;
  186. static struct sata_dwc_device_port dwc_devp;
  187. static void *scr_addr_sstatus;
  188. static u32 temp_n_block = 0;
  189. static unsigned ata_exec_internal(struct ata_device *dev,
  190. struct ata_taskfile *tf, const u8 *cdb,
  191. int dma_dir, unsigned int buflen,
  192. unsigned long timeout);
  193. static unsigned int ata_dev_set_feature(struct ata_device *dev,
  194. u8 enable,u8 feature);
  195. static unsigned int ata_dev_init_params(struct ata_device *dev,
  196. u16 heads, u16 sectors);
  197. static u8 ata_irq_on(struct ata_port *ap);
  198. static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
  199. unsigned int tag);
  200. static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
  201. u8 status, int in_wq);
  202. static void ata_tf_to_host(struct ata_port *ap,
  203. const struct ata_taskfile *tf);
  204. static void ata_exec_command(struct ata_port *ap,
  205. const struct ata_taskfile *tf);
  206. static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
  207. static u8 ata_check_altstatus(struct ata_port *ap);
  208. static u8 ata_check_status(struct ata_port *ap);
  209. static void ata_dev_select(struct ata_port *ap, unsigned int device,
  210. unsigned int wait, unsigned int can_sleep);
  211. static void ata_qc_issue(struct ata_queued_cmd *qc);
  212. static void ata_tf_load(struct ata_port *ap,
  213. const struct ata_taskfile *tf);
  214. static int ata_dev_read_sectors(unsigned char* pdata,
  215. unsigned long datalen, u32 block, u32 n_block);
  216. static int ata_dev_write_sectors(unsigned char* pdata,
  217. unsigned long datalen , u32 block, u32 n_block);
  218. static void ata_std_dev_select(struct ata_port *ap, unsigned int device);
  219. static void ata_qc_complete(struct ata_queued_cmd *qc);
  220. static void __ata_qc_complete(struct ata_queued_cmd *qc);
  221. static void fill_result_tf(struct ata_queued_cmd *qc);
  222. static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
  223. static void ata_mmio_data_xfer(struct ata_device *dev,
  224. unsigned char *buf,
  225. unsigned int buflen,int do_write);
  226. static void ata_pio_task(struct ata_port *arg_ap);
  227. static void __ata_port_freeze(struct ata_port *ap);
  228. static int ata_port_freeze(struct ata_port *ap);
  229. static void ata_qc_free(struct ata_queued_cmd *qc);
  230. static void ata_pio_sectors(struct ata_queued_cmd *qc);
  231. static void ata_pio_sector(struct ata_queued_cmd *qc);
  232. static void ata_pio_queue_task(struct ata_port *ap,
  233. void *data,unsigned long delay);
  234. static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq);
  235. static int sata_dwc_softreset(struct ata_port *ap);
  236. static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
  237. unsigned int flags, u16 *id);
  238. static int check_sata_dev_state(void);
  239. static const struct ata_port_info sata_dwc_port_info[] = {
  240. {
  241. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  242. ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING |
  243. ATA_FLAG_SRST | ATA_FLAG_NCQ,
  244. .pio_mask = 0x1f,
  245. .mwdma_mask = 0x07,
  246. .udma_mask = 0x7f,
  247. },
  248. };
  249. int init_sata(int dev)
  250. {
  251. struct sata_dwc_device hsdev;
  252. struct ata_host host;
  253. struct ata_port_info pi = sata_dwc_port_info[0];
  254. struct ata_link *link;
  255. struct sata_dwc_device_port hsdevp = dwc_devp;
  256. u8 *base = 0;
  257. u8 *sata_dma_regs_addr = 0;
  258. u8 status;
  259. unsigned long base_addr = 0;
  260. int chan = 0;
  261. int rc;
  262. int i;
  263. phost = &host;
  264. base = (u8*)SATA_BASE_ADDR;
  265. hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
  266. host.n_ports = SATA_DWC_MAX_PORTS;
  267. for (i = 0; i < SATA_DWC_MAX_PORTS; i++) {
  268. ap.pflags |= ATA_PFLAG_INITIALIZING;
  269. ap.flags = ATA_FLAG_DISABLED;
  270. ap.print_id = -1;
  271. ap.ctl = ATA_DEVCTL_OBS;
  272. ap.host = &host;
  273. ap.last_ctl = 0xFF;
  274. link = &ap.link;
  275. link->ap = &ap;
  276. link->pmp = 0;
  277. link->active_tag = ATA_TAG_POISON;
  278. link->hw_sata_spd_limit = 0;
  279. ap.port_no = i;
  280. host.ports[i] = &ap;
  281. }
  282. ap.pio_mask = pi.pio_mask;
  283. ap.mwdma_mask = pi.mwdma_mask;
  284. ap.udma_mask = pi.udma_mask;
  285. ap.flags |= pi.flags;
  286. ap.link.flags |= pi.link_flags;
  287. host.ports[0]->ioaddr.cmd_addr = base;
  288. host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
  289. scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
  290. base_addr = (unsigned long)base;
  291. host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00;
  292. host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00;
  293. host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04;
  294. host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04;
  295. host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08;
  296. host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c;
  297. host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10;
  298. host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14;
  299. host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18;
  300. host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c;
  301. host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c;
  302. host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20;
  303. host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20;
  304. sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR;
  305. sata_dma_regs = (void *__iomem)sata_dma_regs_addr;
  306. status = ata_check_altstatus(&ap);
  307. if (status == 0x7f) {
  308. printf("Hard Disk not found.\n");
  309. dev_state = SATA_NODEVICE;
  310. rc = false;
  311. return rc;
  312. }
  313. printf("Waiting for device...");
  314. i = 0;
  315. while (1) {
  316. udelay(10000);
  317. status = ata_check_altstatus(&ap);
  318. if ((status & ATA_BUSY) == 0) {
  319. printf("\n");
  320. break;
  321. }
  322. i++;
  323. if (i > (ATA_RESET_TIME * 100)) {
  324. printf("** TimeOUT **\n");
  325. dev_state = SATA_NODEVICE;
  326. rc = false;
  327. return rc;
  328. }
  329. if ((i >= 100) && ((i % 100) == 0))
  330. printf(".");
  331. }
  332. rc = sata_dwc_softreset(&ap);
  333. if (rc) {
  334. printf("sata_dwc : error. soft reset failed\n");
  335. return rc;
  336. }
  337. for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
  338. out_le32(&(sata_dma_regs->interrupt_mask.error.low),
  339. DMA_DISABLE_CHAN(chan));
  340. out_le32(&(sata_dma_regs->interrupt_mask.tfr.low),
  341. DMA_DISABLE_CHAN(chan));
  342. }
  343. out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI);
  344. out_le32(&hsdev.sata_dwc_regs->intmr,
  345. SATA_DWC_INTMR_ERRM |
  346. SATA_DWC_INTMR_PMABRTM);
  347. /* Unmask the error bits that should trigger
  348. * an error interrupt by setting the error mask register.
  349. */
  350. out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
  351. hsdev.host = ap.host;
  352. memset(&hsdevp, 0, sizeof(hsdevp));
  353. hsdevp.hsdev = &hsdev;
  354. for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
  355. hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
  356. out_le32((void __iomem *)scr_addr_sstatus + 4,
  357. in_le32((void __iomem *)scr_addr_sstatus + 4));
  358. rc = 0;
  359. return rc;
  360. }
  361. int reset_sata(int dev)
  362. {
  363. return 0;
  364. }
  365. static u8 ata_check_altstatus(struct ata_port *ap)
  366. {
  367. u8 val = 0;
  368. val = readb(ap->ioaddr.altstatus_addr);
  369. return val;
  370. }
  371. static int sata_dwc_softreset(struct ata_port *ap)
  372. {
  373. u8 nsect,lbal = 0;
  374. u8 tmp = 0;
  375. struct ata_ioports *ioaddr = &ap->ioaddr;
  376. in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
  377. writeb(0x55, ioaddr->nsect_addr);
  378. writeb(0xaa, ioaddr->lbal_addr);
  379. writeb(0xaa, ioaddr->nsect_addr);
  380. writeb(0x55, ioaddr->lbal_addr);
  381. writeb(0x55, ioaddr->nsect_addr);
  382. writeb(0xaa, ioaddr->lbal_addr);
  383. nsect = readb(ioaddr->nsect_addr);
  384. lbal = readb(ioaddr->lbal_addr);
  385. if ((nsect == 0x55) && (lbal == 0xaa)) {
  386. printf("Device found\n");
  387. } else {
  388. printf("No device found\n");
  389. dev_state = SATA_NODEVICE;
  390. return false;
  391. }
  392. tmp = ATA_DEVICE_OBS;
  393. writeb(tmp, ioaddr->device_addr);
  394. writeb(ap->ctl, ioaddr->ctl_addr);
  395. udelay(200);
  396. writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
  397. udelay(200);
  398. writeb(ap->ctl, ioaddr->ctl_addr);
  399. msleep(150);
  400. ata_check_status(ap);
  401. msleep(50);
  402. ata_check_status(ap);
  403. while (1) {
  404. u8 status = ata_check_status(ap);
  405. if (!(status & ATA_BUSY))
  406. break;
  407. printf("Hard Disk status is BUSY.\n");
  408. msleep(50);
  409. }
  410. tmp = ATA_DEVICE_OBS;
  411. writeb(tmp, ioaddr->device_addr);
  412. nsect = readb(ioaddr->nsect_addr);
  413. lbal = readb(ioaddr->lbal_addr);
  414. return 0;
  415. }
  416. static u8 ata_check_status(struct ata_port *ap)
  417. {
  418. u8 val = 0;
  419. val = readb(ap->ioaddr.status_addr);
  420. return val;
  421. }
  422. static int ata_id_has_hipm(const u16 *id)
  423. {
  424. u16 val = id[76];
  425. if (val == 0 || val == 0xffff)
  426. return -1;
  427. return val & (1 << 9);
  428. }
  429. static int ata_id_has_dipm(const u16 *id)
  430. {
  431. u16 val = id[78];
  432. if (val == 0 || val == 0xffff)
  433. return -1;
  434. return val & (1 << 3);
  435. }
  436. int scan_sata(int dev)
  437. {
  438. int i;
  439. int rc;
  440. u8 status;
  441. const u16 *id;
  442. struct ata_device *ata_dev = &ata_device;
  443. unsigned long pio_mask, mwdma_mask;
  444. char revbuf[7];
  445. u16 iobuf[ATA_SECTOR_WORDS];
  446. memset(iobuf, 0, sizeof(iobuf));
  447. if (dev_state == SATA_NODEVICE)
  448. return 1;
  449. printf("Waiting for device...");
  450. i = 0;
  451. while (1) {
  452. udelay(10000);
  453. status = ata_check_altstatus(&ap);
  454. if ((status & ATA_BUSY) == 0) {
  455. printf("\n");
  456. break;
  457. }
  458. i++;
  459. if (i > (ATA_RESET_TIME * 100)) {
  460. printf("** TimeOUT **\n");
  461. dev_state = SATA_NODEVICE;
  462. return 1;
  463. }
  464. if ((i >= 100) && ((i % 100) == 0))
  465. printf(".");
  466. }
  467. udelay(1000);
  468. rc = ata_dev_read_id(ata_dev, &ata_dev->class,
  469. ATA_READID_POSTRESET,ata_dev->id);
  470. if (rc) {
  471. printf("sata_dwc : error. failed sata scan\n");
  472. return 1;
  473. }
  474. /* SATA drives indicate we have a bridge. We don't know which
  475. * end of the link the bridge is which is a problem
  476. */
  477. if (ata_id_is_sata(ata_dev->id))
  478. ap.cbl = ATA_CBL_SATA;
  479. id = ata_dev->id;
  480. ata_dev->flags &= ~ATA_DFLAG_CFG_MASK;
  481. ata_dev->max_sectors = 0;
  482. ata_dev->cdb_len = 0;
  483. ata_dev->n_sectors = 0;
  484. ata_dev->cylinders = 0;
  485. ata_dev->heads = 0;
  486. ata_dev->sectors = 0;
  487. if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
  488. pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
  489. pio_mask <<= 3;
  490. pio_mask |= 0x7;
  491. } else {
  492. /* If word 64 isn't valid then Word 51 high byte holds
  493. * the PIO timing number for the maximum. Turn it into
  494. * a mask.
  495. */
  496. u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
  497. if (mode < 5) {
  498. pio_mask = (2 << mode) - 1;
  499. } else {
  500. pio_mask = 1;
  501. }
  502. }
  503. mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
  504. if (ata_id_is_cfa(id)) {
  505. int pio = id[163] & 0x7;
  506. int dma = (id[163] >> 3) & 7;
  507. if (pio)
  508. pio_mask |= (1 << 5);
  509. if (pio > 1)
  510. pio_mask |= (1 << 6);
  511. if (dma)
  512. mwdma_mask |= (1 << 3);
  513. if (dma > 1)
  514. mwdma_mask |= (1 << 4);
  515. }
  516. if (ata_dev->class == ATA_DEV_ATA) {
  517. if (ata_id_is_cfa(id)) {
  518. if (id[162] & 1)
  519. printf("supports DRM functions and may "
  520. "not be fully accessable.\n");
  521. strcpy(revbuf, "CFA");
  522. } else {
  523. if (ata_id_has_tpm(id))
  524. printf("supports DRM functions and may "
  525. "not be fully accessable.\n");
  526. }
  527. ata_dev->n_sectors = ata_id_n_sectors((u16*)id);
  528. if (ata_dev->id[59] & 0x100)
  529. ata_dev->multi_count = ata_dev->id[59] & 0xff;
  530. if (ata_id_has_lba(id)) {
  531. char ncq_desc[20];
  532. ata_dev->flags |= ATA_DFLAG_LBA;
  533. if (ata_id_has_lba48(id)) {
  534. ata_dev->flags |= ATA_DFLAG_LBA48;
  535. if (ata_dev->n_sectors >= (1UL << 28) &&
  536. ata_id_has_flush_ext(id))
  537. ata_dev->flags |= ATA_DFLAG_FLUSH_EXT;
  538. }
  539. if (!ata_id_has_ncq(ata_dev->id))
  540. ncq_desc[0] = '\0';
  541. if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
  542. strcpy(ncq_desc, "NCQ (not used)");
  543. if (ap.flags & ATA_FLAG_NCQ)
  544. ata_dev->flags |= ATA_DFLAG_NCQ;
  545. }
  546. ata_dev->cdb_len = 16;
  547. }
  548. ata_dev->max_sectors = ATA_MAX_SECTORS;
  549. if (ata_dev->flags & ATA_DFLAG_LBA48)
  550. ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48;
  551. if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) {
  552. if (ata_id_has_hipm(ata_dev->id))
  553. ata_dev->flags |= ATA_DFLAG_HIPM;
  554. if (ata_id_has_dipm(ata_dev->id))
  555. ata_dev->flags |= ATA_DFLAG_DIPM;
  556. }
  557. if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) {
  558. ata_dev->udma_mask &= ATA_UDMA5;
  559. ata_dev->max_sectors = ATA_MAX_SECTORS;
  560. }
  561. if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
  562. printf("Drive reports diagnostics failure."
  563. "This may indicate a drive\n");
  564. printf("fault or invalid emulation."
  565. "Contact drive vendor for information.\n");
  566. }
  567. rc = check_sata_dev_state();
  568. ata_id_c_string(ata_dev->id,
  569. (unsigned char *)sata_dev_desc[dev].revision,
  570. ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision));
  571. ata_id_c_string(ata_dev->id,
  572. (unsigned char *)sata_dev_desc[dev].vendor,
  573. ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor));
  574. ata_id_c_string(ata_dev->id,
  575. (unsigned char *)sata_dev_desc[dev].product,
  576. ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product));
  577. sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors;
  578. #ifdef CONFIG_LBA48
  579. if (ata_dev->id[83] & (1 << 10)) {
  580. sata_dev_desc[dev].lba48 = 1;
  581. } else {
  582. sata_dev_desc[dev].lba48 = 0;
  583. }
  584. #endif
  585. return 0;
  586. }
  587. static u8 ata_busy_wait(struct ata_port *ap,
  588. unsigned int bits,unsigned int max)
  589. {
  590. u8 status;
  591. do {
  592. udelay(10);
  593. status = ata_check_status(ap);
  594. max--;
  595. } while (status != 0xff && (status & bits) && (max > 0));
  596. return status;
  597. }
  598. static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
  599. unsigned int flags, u16 *id)
  600. {
  601. struct ata_port *ap = pap;
  602. unsigned int class = *p_class;
  603. struct ata_taskfile tf;
  604. unsigned int err_mask = 0;
  605. const char *reason;
  606. int may_fallback = 1, tried_spinup = 0;
  607. u8 status;
  608. int rc;
  609. status = ata_busy_wait(ap, ATA_BUSY, 30000);
  610. if (status & ATA_BUSY) {
  611. printf("BSY = 0 check. timeout.\n");
  612. rc = false;
  613. return rc;
  614. }
  615. ata_dev_select(ap, dev->devno, 1, 1);
  616. retry:
  617. memset(&tf, 0, sizeof(tf));
  618. ap->print_id = 1;
  619. ap->flags &= ~ATA_FLAG_DISABLED;
  620. tf.ctl = ap->ctl;
  621. tf.device = ATA_DEVICE_OBS;
  622. tf.command = ATA_CMD_ID_ATA;
  623. tf.protocol = ATA_PROT_PIO;
  624. /* Some devices choke if TF registers contain garbage. Make
  625. * sure those are properly initialized.
  626. */
  627. tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
  628. /* Device presence detection is unreliable on some
  629. * controllers. Always poll IDENTIFY if available.
  630. */
  631. tf.flags |= ATA_TFLAG_POLLING;
  632. temp_n_block = 1;
  633. err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
  634. sizeof(id[0]) * ATA_ID_WORDS, 0);
  635. if (err_mask) {
  636. if (err_mask & AC_ERR_NODEV_HINT) {
  637. printf("NODEV after polling detection\n");
  638. return -ENOENT;
  639. }
  640. if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
  641. /* Device or controller might have reported
  642. * the wrong device class. Give a shot at the
  643. * other IDENTIFY if the current one is
  644. * aborted by the device.
  645. */
  646. if (may_fallback) {
  647. may_fallback = 0;
  648. if (class == ATA_DEV_ATA) {
  649. class = ATA_DEV_ATAPI;
  650. } else {
  651. class = ATA_DEV_ATA;
  652. }
  653. goto retry;
  654. }
  655. /* Control reaches here iff the device aborted
  656. * both flavors of IDENTIFYs which happens
  657. * sometimes with phantom devices.
  658. */
  659. printf("both IDENTIFYs aborted, assuming NODEV\n");
  660. return -ENOENT;
  661. }
  662. rc = -EIO;
  663. reason = "I/O error";
  664. goto err_out;
  665. }
  666. /* Falling back doesn't make sense if ID data was read
  667. * successfully at least once.
  668. */
  669. may_fallback = 0;
  670. unsigned int id_cnt;
  671. for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++)
  672. id[id_cnt] = le16_to_cpu(id[id_cnt]);
  673. rc = -EINVAL;
  674. reason = "device reports invalid type";
  675. if (class == ATA_DEV_ATA) {
  676. if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
  677. goto err_out;
  678. } else {
  679. if (ata_id_is_ata(id))
  680. goto err_out;
  681. }
  682. if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
  683. tried_spinup = 1;
  684. /*
  685. * Drive powered-up in standby mode, and requires a specific
  686. * SET_FEATURES spin-up subcommand before it will accept
  687. * anything other than the original IDENTIFY command.
  688. */
  689. err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
  690. if (err_mask && id[2] != 0x738c) {
  691. rc = -EIO;
  692. reason = "SPINUP failed";
  693. goto err_out;
  694. }
  695. /*
  696. * If the drive initially returned incomplete IDENTIFY info,
  697. * we now must reissue the IDENTIFY command.
  698. */
  699. if (id[2] == 0x37c8)
  700. goto retry;
  701. }
  702. if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
  703. /*
  704. * The exact sequence expected by certain pre-ATA4 drives is:
  705. * SRST RESET
  706. * IDENTIFY (optional in early ATA)
  707. * INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
  708. * anything else..
  709. * Some drives were very specific about that exact sequence.
  710. *
  711. * Note that ATA4 says lba is mandatory so the second check
  712. * shoud never trigger.
  713. */
  714. if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
  715. err_mask = ata_dev_init_params(dev, id[3], id[6]);
  716. if (err_mask) {
  717. rc = -EIO;
  718. reason = "INIT_DEV_PARAMS failed";
  719. goto err_out;
  720. }
  721. /* current CHS translation info (id[53-58]) might be
  722. * changed. reread the identify device info.
  723. */
  724. flags &= ~ATA_READID_POSTRESET;
  725. goto retry;
  726. }
  727. }
  728. *p_class = class;
  729. return 0;
  730. err_out:
  731. printf("failed to READ ID (%s, err_mask=0x%x)\n", reason, err_mask);
  732. return rc;
  733. }
  734. static u8 ata_wait_idle(struct ata_port *ap)
  735. {
  736. u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
  737. return status;
  738. }
  739. static void ata_dev_select(struct ata_port *ap, unsigned int device,
  740. unsigned int wait, unsigned int can_sleep)
  741. {
  742. if (wait)
  743. ata_wait_idle(ap);
  744. ata_std_dev_select(ap, device);
  745. if (wait)
  746. ata_wait_idle(ap);
  747. }
  748. static void ata_std_dev_select(struct ata_port *ap, unsigned int device)
  749. {
  750. u8 tmp;
  751. if (device == 0) {
  752. tmp = ATA_DEVICE_OBS;
  753. } else {
  754. tmp = ATA_DEVICE_OBS | ATA_DEV1;
  755. }
  756. writeb(tmp, ap->ioaddr.device_addr);
  757. readb(ap->ioaddr.altstatus_addr);
  758. udelay(1);
  759. }
  760. static int waiting_for_reg_state(volatile u8 *offset,
  761. int timeout_msec,
  762. u32 sign)
  763. {
  764. int i;
  765. u32 status;
  766. for (i = 0; i < timeout_msec; i++) {
  767. status = readl(offset);
  768. if ((status & sign) != 0)
  769. break;
  770. msleep(1);
  771. }
  772. return (i < timeout_msec) ? 0 : -1;
  773. }
  774. static void ata_qc_reinit(struct ata_queued_cmd *qc)
  775. {
  776. qc->dma_dir = DMA_NONE;
  777. qc->flags = 0;
  778. qc->nbytes = qc->extrabytes = qc->curbytes = 0;
  779. qc->n_elem = 0;
  780. qc->err_mask = 0;
  781. qc->sect_size = ATA_SECT_SIZE;
  782. qc->nbytes = ATA_SECT_SIZE * temp_n_block;
  783. memset(&qc->tf, 0, sizeof(qc->tf));
  784. qc->tf.ctl = 0;
  785. qc->tf.device = ATA_DEVICE_OBS;
  786. qc->result_tf.command = ATA_DRDY;
  787. qc->result_tf.feature = 0;
  788. }
  789. struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
  790. unsigned int tag)
  791. {
  792. if (tag < ATA_MAX_QUEUE)
  793. return &ap->qcmd[tag];
  794. return NULL;
  795. }
  796. static void __ata_port_freeze(struct ata_port *ap)
  797. {
  798. printf("set port freeze.\n");
  799. ap->pflags |= ATA_PFLAG_FROZEN;
  800. }
  801. static int ata_port_freeze(struct ata_port *ap)
  802. {
  803. __ata_port_freeze(ap);
  804. return 0;
  805. }
  806. unsigned ata_exec_internal(struct ata_device *dev,
  807. struct ata_taskfile *tf, const u8 *cdb,
  808. int dma_dir, unsigned int buflen,
  809. unsigned long timeout)
  810. {
  811. struct ata_link *link = dev->link;
  812. struct ata_port *ap = pap;
  813. struct ata_queued_cmd *qc;
  814. unsigned int tag, preempted_tag;
  815. u32 preempted_sactive, preempted_qc_active;
  816. int preempted_nr_active_links;
  817. unsigned int err_mask;
  818. int rc = 0;
  819. u8 status;
  820. status = ata_busy_wait(ap, ATA_BUSY, 300000);
  821. if (status & ATA_BUSY) {
  822. printf("BSY = 0 check. timeout.\n");
  823. rc = false;
  824. return rc;
  825. }
  826. if (ap->pflags & ATA_PFLAG_FROZEN)
  827. return AC_ERR_SYSTEM;
  828. tag = ATA_TAG_INTERNAL;
  829. if (test_and_set_bit(tag, &ap->qc_allocated)) {
  830. rc = false;
  831. return rc;
  832. }
  833. qc = __ata_qc_from_tag(ap, tag);
  834. qc->tag = tag;
  835. qc->ap = ap;
  836. qc->dev = dev;
  837. ata_qc_reinit(qc);
  838. preempted_tag = link->active_tag;
  839. preempted_sactive = link->sactive;
  840. preempted_qc_active = ap->qc_active;
  841. preempted_nr_active_links = ap->nr_active_links;
  842. link->active_tag = ATA_TAG_POISON;
  843. link->sactive = 0;
  844. ap->qc_active = 0;
  845. ap->nr_active_links = 0;
  846. qc->tf = *tf;
  847. if (cdb)
  848. memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
  849. qc->flags |= ATA_QCFLAG_RESULT_TF;
  850. qc->dma_dir = dma_dir;
  851. qc->private_data = 0;
  852. ata_qc_issue(qc);
  853. if (!timeout)
  854. timeout = ata_probe_timeout * 1000 / HZ;
  855. status = ata_busy_wait(ap, ATA_BUSY, 30000);
  856. if (status & ATA_BUSY) {
  857. printf("BSY = 0 check. timeout.\n");
  858. printf("altstatus = 0x%x.\n", status);
  859. qc->err_mask |= AC_ERR_OTHER;
  860. return qc->err_mask;
  861. }
  862. if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) {
  863. u8 status = 0;
  864. u8 errorStatus = 0;
  865. status = readb(ap->ioaddr.altstatus_addr);
  866. if ((status & 0x01) != 0) {
  867. errorStatus = readb(ap->ioaddr.feature_addr);
  868. if (errorStatus == 0x04 &&
  869. qc->tf.command == ATA_CMD_PIO_READ_EXT){
  870. printf("Hard Disk doesn't support LBA48\n");
  871. dev_state = SATA_ERROR;
  872. qc->err_mask |= AC_ERR_OTHER;
  873. return qc->err_mask;
  874. }
  875. }
  876. qc->err_mask |= AC_ERR_OTHER;
  877. return qc->err_mask;
  878. }
  879. status = ata_busy_wait(ap, ATA_BUSY, 10);
  880. if (status & ATA_BUSY) {
  881. printf("BSY = 0 check. timeout.\n");
  882. qc->err_mask |= AC_ERR_OTHER;
  883. return qc->err_mask;
  884. }
  885. ata_pio_task(ap);
  886. if (!rc) {
  887. if (qc->flags & ATA_QCFLAG_ACTIVE) {
  888. qc->err_mask |= AC_ERR_TIMEOUT;
  889. ata_port_freeze(ap);
  890. }
  891. }
  892. if (qc->flags & ATA_QCFLAG_FAILED) {
  893. if (qc->result_tf.command & (ATA_ERR | ATA_DF))
  894. qc->err_mask |= AC_ERR_DEV;
  895. if (!qc->err_mask)
  896. qc->err_mask |= AC_ERR_OTHER;
  897. if (qc->err_mask & ~AC_ERR_OTHER)
  898. qc->err_mask &= ~AC_ERR_OTHER;
  899. }
  900. *tf = qc->result_tf;
  901. err_mask = qc->err_mask;
  902. ata_qc_free(qc);
  903. link->active_tag = preempted_tag;
  904. link->sactive = preempted_sactive;
  905. ap->qc_active = preempted_qc_active;
  906. ap->nr_active_links = preempted_nr_active_links;
  907. if (ap->flags & ATA_FLAG_DISABLED) {
  908. err_mask |= AC_ERR_SYSTEM;
  909. ap->flags &= ~ATA_FLAG_DISABLED;
  910. }
  911. return err_mask;
  912. }
  913. static void ata_qc_issue(struct ata_queued_cmd *qc)
  914. {
  915. struct ata_port *ap = qc->ap;
  916. struct ata_link *link = qc->dev->link;
  917. u8 prot = qc->tf.protocol;
  918. if (ata_is_ncq(prot)) {
  919. if (!link->sactive)
  920. ap->nr_active_links++;
  921. link->sactive |= 1 << qc->tag;
  922. } else {
  923. ap->nr_active_links++;
  924. link->active_tag = qc->tag;
  925. }
  926. qc->flags |= ATA_QCFLAG_ACTIVE;
  927. ap->qc_active |= 1 << qc->tag;
  928. if (qc->dev->flags & ATA_DFLAG_SLEEPING) {
  929. msleep(1);
  930. return;
  931. }
  932. qc->err_mask |= ata_qc_issue_prot(qc);
  933. if (qc->err_mask)
  934. goto err;
  935. return;
  936. err:
  937. ata_qc_complete(qc);
  938. }
  939. static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
  940. {
  941. struct ata_port *ap = qc->ap;
  942. if (ap->flags & ATA_FLAG_PIO_POLLING) {
  943. switch (qc->tf.protocol) {
  944. case ATA_PROT_PIO:
  945. case ATA_PROT_NODATA:
  946. case ATAPI_PROT_PIO:
  947. case ATAPI_PROT_NODATA:
  948. qc->tf.flags |= ATA_TFLAG_POLLING;
  949. break;
  950. default:
  951. break;
  952. }
  953. }
  954. ata_dev_select(ap, qc->dev->devno, 1, 0);
  955. switch (qc->tf.protocol) {
  956. case ATA_PROT_PIO:
  957. if (qc->tf.flags & ATA_TFLAG_POLLING)
  958. qc->tf.ctl |= ATA_NIEN;
  959. ata_tf_to_host(ap, &qc->tf);
  960. ap->hsm_task_state = HSM_ST;
  961. if (qc->tf.flags & ATA_TFLAG_POLLING)
  962. ata_pio_queue_task(ap, qc, 0);
  963. break;
  964. default:
  965. return AC_ERR_SYSTEM;
  966. }
  967. return 0;
  968. }
  969. static void ata_tf_to_host(struct ata_port *ap,
  970. const struct ata_taskfile *tf)
  971. {
  972. ata_tf_load(ap, tf);
  973. ata_exec_command(ap, tf);
  974. }
  975. static void ata_tf_load(struct ata_port *ap,
  976. const struct ata_taskfile *tf)
  977. {
  978. struct ata_ioports *ioaddr = &ap->ioaddr;
  979. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  980. if (tf->ctl != ap->last_ctl) {
  981. if (ioaddr->ctl_addr)
  982. writeb(tf->ctl, ioaddr->ctl_addr);
  983. ap->last_ctl = tf->ctl;
  984. ata_wait_idle(ap);
  985. }
  986. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  987. writeb(tf->hob_feature, ioaddr->feature_addr);
  988. writeb(tf->hob_nsect, ioaddr->nsect_addr);
  989. writeb(tf->hob_lbal, ioaddr->lbal_addr);
  990. writeb(tf->hob_lbam, ioaddr->lbam_addr);
  991. writeb(tf->hob_lbah, ioaddr->lbah_addr);
  992. }
  993. if (is_addr) {
  994. writeb(tf->feature, ioaddr->feature_addr);
  995. writeb(tf->nsect, ioaddr->nsect_addr);
  996. writeb(tf->lbal, ioaddr->lbal_addr);
  997. writeb(tf->lbam, ioaddr->lbam_addr);
  998. writeb(tf->lbah, ioaddr->lbah_addr);
  999. }
  1000. if (tf->flags & ATA_TFLAG_DEVICE)
  1001. writeb(tf->device, ioaddr->device_addr);
  1002. ata_wait_idle(ap);
  1003. }
  1004. static void ata_exec_command(struct ata_port *ap,
  1005. const struct ata_taskfile *tf)
  1006. {
  1007. writeb(tf->command, ap->ioaddr.command_addr);
  1008. readb(ap->ioaddr.altstatus_addr);
  1009. udelay(1);
  1010. }
  1011. static void ata_pio_queue_task(struct ata_port *ap,
  1012. void *data,unsigned long delay)
  1013. {
  1014. ap->port_task_data = data;
  1015. }
  1016. static unsigned int ac_err_mask(u8 status)
  1017. {
  1018. if (status & (ATA_BUSY | ATA_DRQ))
  1019. return AC_ERR_HSM;
  1020. if (status & (ATA_ERR | ATA_DF))
  1021. return AC_ERR_DEV;
  1022. return 0;
  1023. }
  1024. static unsigned int __ac_err_mask(u8 status)
  1025. {
  1026. unsigned int mask = ac_err_mask(status);
  1027. if (mask == 0)
  1028. return AC_ERR_OTHER;
  1029. return mask;
  1030. }
  1031. static void ata_pio_task(struct ata_port *arg_ap)
  1032. {
  1033. struct ata_port *ap = arg_ap;
  1034. struct ata_queued_cmd *qc = ap->port_task_data;
  1035. u8 status;
  1036. int poll_next;
  1037. fsm_start:
  1038. /*
  1039. * This is purely heuristic. This is a fast path.
  1040. * Sometimes when we enter, BSY will be cleared in
  1041. * a chk-status or two. If not, the drive is probably seeking
  1042. * or something. Snooze for a couple msecs, then
  1043. * chk-status again. If still busy, queue delayed work.
  1044. */
  1045. status = ata_busy_wait(ap, ATA_BUSY, 5);
  1046. if (status & ATA_BUSY) {
  1047. msleep(2);
  1048. status = ata_busy_wait(ap, ATA_BUSY, 10);
  1049. if (status & ATA_BUSY) {
  1050. ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
  1051. return;
  1052. }
  1053. }
  1054. poll_next = ata_hsm_move(ap, qc, status, 1);
  1055. /* another command or interrupt handler
  1056. * may be running at this point.
  1057. */
  1058. if (poll_next)
  1059. goto fsm_start;
  1060. }
  1061. static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
  1062. u8 status, int in_wq)
  1063. {
  1064. int poll_next;
  1065. fsm_start:
  1066. switch (ap->hsm_task_state) {
  1067. case HSM_ST_FIRST:
  1068. poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
  1069. if ((status & ATA_DRQ) == 0) {
  1070. if (status & (ATA_ERR | ATA_DF)) {
  1071. qc->err_mask |= AC_ERR_DEV;
  1072. } else {
  1073. qc->err_mask |= AC_ERR_HSM;
  1074. }
  1075. ap->hsm_task_state = HSM_ST_ERR;
  1076. goto fsm_start;
  1077. }
  1078. /* Device should not ask for data transfer (DRQ=1)
  1079. * when it finds something wrong.
  1080. * We ignore DRQ here and stop the HSM by
  1081. * changing hsm_task_state to HSM_ST_ERR and
  1082. * let the EH abort the command or reset the device.
  1083. */
  1084. if (status & (ATA_ERR | ATA_DF)) {
  1085. if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
  1086. printf("DRQ=1 with device error, "
  1087. "dev_stat 0x%X\n", status);
  1088. qc->err_mask |= AC_ERR_HSM;
  1089. ap->hsm_task_state = HSM_ST_ERR;
  1090. goto fsm_start;
  1091. }
  1092. }
  1093. if (qc->tf.protocol == ATA_PROT_PIO) {
  1094. /* PIO data out protocol.
  1095. * send first data block.
  1096. */
  1097. /* ata_pio_sectors() might change the state
  1098. * to HSM_ST_LAST. so, the state is changed here
  1099. * before ata_pio_sectors().
  1100. */
  1101. ap->hsm_task_state = HSM_ST;
  1102. ata_pio_sectors(qc);
  1103. } else {
  1104. printf("protocol is not ATA_PROT_PIO \n");
  1105. }
  1106. break;
  1107. case HSM_ST:
  1108. if ((status & ATA_DRQ) == 0) {
  1109. if (status & (ATA_ERR | ATA_DF)) {
  1110. qc->err_mask |= AC_ERR_DEV;
  1111. } else {
  1112. /* HSM violation. Let EH handle this.
  1113. * Phantom devices also trigger this
  1114. * condition. Mark hint.
  1115. */
  1116. qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT;
  1117. }
  1118. ap->hsm_task_state = HSM_ST_ERR;
  1119. goto fsm_start;
  1120. }
  1121. /* For PIO reads, some devices may ask for
  1122. * data transfer (DRQ=1) alone with ERR=1.
  1123. * We respect DRQ here and transfer one
  1124. * block of junk data before changing the
  1125. * hsm_task_state to HSM_ST_ERR.
  1126. *
  1127. * For PIO writes, ERR=1 DRQ=1 doesn't make
  1128. * sense since the data block has been
  1129. * transferred to the device.
  1130. */
  1131. if (status & (ATA_ERR | ATA_DF)) {
  1132. qc->err_mask |= AC_ERR_DEV;
  1133. if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
  1134. ata_pio_sectors(qc);
  1135. status = ata_wait_idle(ap);
  1136. }
  1137. if (status & (ATA_BUSY | ATA_DRQ))
  1138. qc->err_mask |= AC_ERR_HSM;
  1139. /* ata_pio_sectors() might change the
  1140. * state to HSM_ST_LAST. so, the state
  1141. * is changed after ata_pio_sectors().
  1142. */
  1143. ap->hsm_task_state = HSM_ST_ERR;
  1144. goto fsm_start;
  1145. }
  1146. ata_pio_sectors(qc);
  1147. if (ap->hsm_task_state == HSM_ST_LAST &&
  1148. (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
  1149. status = ata_wait_idle(ap);
  1150. goto fsm_start;
  1151. }
  1152. poll_next = 1;
  1153. break;
  1154. case HSM_ST_LAST:
  1155. if (!ata_ok(status)) {
  1156. qc->err_mask |= __ac_err_mask(status);
  1157. ap->hsm_task_state = HSM_ST_ERR;
  1158. goto fsm_start;
  1159. }
  1160. ap->hsm_task_state = HSM_ST_IDLE;
  1161. ata_hsm_qc_complete(qc, in_wq);
  1162. poll_next = 0;
  1163. break;
  1164. case HSM_ST_ERR:
  1165. /* make sure qc->err_mask is available to
  1166. * know what's wrong and recover
  1167. */
  1168. ap->hsm_task_state = HSM_ST_IDLE;
  1169. ata_hsm_qc_complete(qc, in_wq);
  1170. poll_next = 0;
  1171. break;
  1172. default:
  1173. poll_next = 0;
  1174. }
  1175. return poll_next;
  1176. }
  1177. static void ata_pio_sectors(struct ata_queued_cmd *qc)
  1178. {
  1179. struct ata_port *ap;
  1180. ap = pap;
  1181. qc->pdata = ap->pdata;
  1182. ata_pio_sector(qc);
  1183. readb(qc->ap->ioaddr.altstatus_addr);
  1184. udelay(1);
  1185. }
  1186. static void ata_pio_sector(struct ata_queued_cmd *qc)
  1187. {
  1188. int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
  1189. struct ata_port *ap = qc->ap;
  1190. unsigned int offset;
  1191. unsigned char *buf;
  1192. char temp_data_buf[512];
  1193. if (qc->curbytes == qc->nbytes - qc->sect_size)
  1194. ap->hsm_task_state = HSM_ST_LAST;
  1195. offset = qc->curbytes;
  1196. switch (qc->tf.command) {
  1197. case ATA_CMD_ID_ATA:
  1198. buf = (unsigned char *)&ata_device.id[0];
  1199. break;
  1200. case ATA_CMD_PIO_READ_EXT:
  1201. case ATA_CMD_PIO_READ:
  1202. case ATA_CMD_PIO_WRITE_EXT:
  1203. case ATA_CMD_PIO_WRITE:
  1204. buf = qc->pdata + offset;
  1205. break;
  1206. default:
  1207. buf = (unsigned char *)&temp_data_buf[0];
  1208. }
  1209. ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write);
  1210. qc->curbytes += qc->sect_size;
  1211. }
  1212. static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf,
  1213. unsigned int buflen, int do_write)
  1214. {
  1215. struct ata_port *ap = pap;
  1216. void __iomem *data_addr = ap->ioaddr.data_addr;
  1217. unsigned int words = buflen >> 1;
  1218. u16 *buf16 = (u16 *)buf;
  1219. unsigned int i = 0;
  1220. udelay(100);
  1221. if (do_write) {
  1222. for (i = 0; i < words; i++)
  1223. writew(le16_to_cpu(buf16[i]), data_addr);
  1224. } else {
  1225. for (i = 0; i < words; i++)
  1226. buf16[i] = cpu_to_le16(readw(data_addr));
  1227. }
  1228. if (buflen & 0x01) {
  1229. __le16 align_buf[1] = { 0 };
  1230. unsigned char *trailing_buf = buf + buflen - 1;
  1231. if (do_write) {
  1232. memcpy(align_buf, trailing_buf, 1);
  1233. writew(le16_to_cpu(align_buf[0]), data_addr);
  1234. } else {
  1235. align_buf[0] = cpu_to_le16(readw(data_addr));
  1236. memcpy(trailing_buf, align_buf, 1);
  1237. }
  1238. }
  1239. }
  1240. static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
  1241. {
  1242. struct ata_port *ap = qc->ap;
  1243. if (in_wq) {
  1244. /* EH might have kicked in while host lock is
  1245. * released.
  1246. */
  1247. qc = &ap->qcmd[qc->tag];
  1248. if (qc) {
  1249. if (!(qc->err_mask & AC_ERR_HSM)) {
  1250. ata_irq_on(ap);
  1251. ata_qc_complete(qc);
  1252. } else {
  1253. ata_port_freeze(ap);
  1254. }
  1255. }
  1256. } else {
  1257. if (!(qc->err_mask & AC_ERR_HSM)) {
  1258. ata_qc_complete(qc);
  1259. } else {
  1260. ata_port_freeze(ap);
  1261. }
  1262. }
  1263. }
  1264. static u8 ata_irq_on(struct ata_port *ap)
  1265. {
  1266. struct ata_ioports *ioaddr = &ap->ioaddr;
  1267. u8 tmp;
  1268. ap->ctl &= ~ATA_NIEN;
  1269. ap->last_ctl = ap->ctl;
  1270. if (ioaddr->ctl_addr)
  1271. writeb(ap->ctl, ioaddr->ctl_addr);
  1272. tmp = ata_wait_idle(ap);
  1273. return tmp;
  1274. }
  1275. static unsigned int ata_tag_internal(unsigned int tag)
  1276. {
  1277. return tag == ATA_MAX_QUEUE - 1;
  1278. }
  1279. static void ata_qc_complete(struct ata_queued_cmd *qc)
  1280. {
  1281. struct ata_device *dev = qc->dev;
  1282. if (qc->err_mask)
  1283. qc->flags |= ATA_QCFLAG_FAILED;
  1284. if (qc->flags & ATA_QCFLAG_FAILED) {
  1285. if (!ata_tag_internal(qc->tag)) {
  1286. fill_result_tf(qc);
  1287. return;
  1288. }
  1289. }
  1290. if (qc->flags & ATA_QCFLAG_RESULT_TF)
  1291. fill_result_tf(qc);
  1292. /* Some commands need post-processing after successful
  1293. * completion.
  1294. */
  1295. switch (qc->tf.command) {
  1296. case ATA_CMD_SET_FEATURES:
  1297. if (qc->tf.feature != SETFEATURES_WC_ON &&
  1298. qc->tf.feature != SETFEATURES_WC_OFF)
  1299. break;
  1300. case ATA_CMD_INIT_DEV_PARAMS:
  1301. case ATA_CMD_SET_MULTI:
  1302. break;
  1303. case ATA_CMD_SLEEP:
  1304. dev->flags |= ATA_DFLAG_SLEEPING;
  1305. break;
  1306. }
  1307. __ata_qc_complete(qc);
  1308. }
  1309. static void fill_result_tf(struct ata_queued_cmd *qc)
  1310. {
  1311. struct ata_port *ap = qc->ap;
  1312. qc->result_tf.flags = qc->tf.flags;
  1313. ata_tf_read(ap, &qc->result_tf);
  1314. }
  1315. static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  1316. {
  1317. struct ata_ioports *ioaddr = &ap->ioaddr;
  1318. tf->command = ata_check_status(ap);
  1319. tf->feature = readb(ioaddr->error_addr);
  1320. tf->nsect = readb(ioaddr->nsect_addr);
  1321. tf->lbal = readb(ioaddr->lbal_addr);
  1322. tf->lbam = readb(ioaddr->lbam_addr);
  1323. tf->lbah = readb(ioaddr->lbah_addr);
  1324. tf->device = readb(ioaddr->device_addr);
  1325. if (tf->flags & ATA_TFLAG_LBA48) {
  1326. if (ioaddr->ctl_addr) {
  1327. writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  1328. tf->hob_feature = readb(ioaddr->error_addr);
  1329. tf->hob_nsect = readb(ioaddr->nsect_addr);
  1330. tf->hob_lbal = readb(ioaddr->lbal_addr);
  1331. tf->hob_lbam = readb(ioaddr->lbam_addr);
  1332. tf->hob_lbah = readb(ioaddr->lbah_addr);
  1333. writeb(tf->ctl, ioaddr->ctl_addr);
  1334. ap->last_ctl = tf->ctl;
  1335. } else {
  1336. printf("sata_dwc warnning register read.\n");
  1337. }
  1338. }
  1339. }
  1340. static void __ata_qc_complete(struct ata_queued_cmd *qc)
  1341. {
  1342. struct ata_port *ap = qc->ap;
  1343. struct ata_link *link = qc->dev->link;
  1344. link->active_tag = ATA_TAG_POISON;
  1345. ap->nr_active_links--;
  1346. if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link)
  1347. ap->excl_link = NULL;
  1348. qc->flags &= ~ATA_QCFLAG_ACTIVE;
  1349. ap->qc_active &= ~(1 << qc->tag);
  1350. }
  1351. static void ata_qc_free(struct ata_queued_cmd *qc)
  1352. {
  1353. struct ata_port *ap = qc->ap;
  1354. unsigned int tag;
  1355. qc->flags = 0;
  1356. tag = qc->tag;
  1357. if (tag < ATA_MAX_QUEUE) {
  1358. qc->tag = ATA_TAG_POISON;
  1359. clear_bit(tag, &ap->qc_allocated);
  1360. }
  1361. }
  1362. static int check_sata_dev_state(void)
  1363. {
  1364. unsigned long datalen;
  1365. unsigned char *pdata;
  1366. int ret = 0;
  1367. int i = 0;
  1368. char temp_data_buf[512];
  1369. while (1) {
  1370. udelay(10000);
  1371. pdata = (unsigned char*)&temp_data_buf[0];
  1372. datalen = 512;
  1373. ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
  1374. if (ret == true)
  1375. break;
  1376. i++;
  1377. if (i > (ATA_RESET_TIME * 100)) {
  1378. printf("** TimeOUT **\n");
  1379. dev_state = SATA_NODEVICE;
  1380. return false;
  1381. }
  1382. if ((i >= 100) && ((i % 100) == 0))
  1383. printf(".");
  1384. }
  1385. dev_state = SATA_READY;
  1386. return true;
  1387. }
  1388. static unsigned int ata_dev_set_feature(struct ata_device *dev,
  1389. u8 enable, u8 feature)
  1390. {
  1391. struct ata_taskfile tf;
  1392. struct ata_port *ap;
  1393. ap = pap;
  1394. unsigned int err_mask;
  1395. memset(&tf, 0, sizeof(tf));
  1396. tf.ctl = ap->ctl;
  1397. tf.device = ATA_DEVICE_OBS;
  1398. tf.command = ATA_CMD_SET_FEATURES;
  1399. tf.feature = enable;
  1400. tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
  1401. tf.protocol = ATA_PROT_NODATA;
  1402. tf.nsect = feature;
  1403. err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
  1404. return err_mask;
  1405. }
  1406. static unsigned int ata_dev_init_params(struct ata_device *dev,
  1407. u16 heads, u16 sectors)
  1408. {
  1409. struct ata_taskfile tf;
  1410. struct ata_port *ap;
  1411. ap = pap;
  1412. unsigned int err_mask;
  1413. if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
  1414. return AC_ERR_INVALID;
  1415. memset(&tf, 0, sizeof(tf));
  1416. tf.ctl = ap->ctl;
  1417. tf.device = ATA_DEVICE_OBS;
  1418. tf.command = ATA_CMD_INIT_DEV_PARAMS;
  1419. tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
  1420. tf.protocol = ATA_PROT_NODATA;
  1421. tf.nsect = sectors;
  1422. tf.device |= (heads - 1) & 0x0f;
  1423. err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
  1424. if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
  1425. err_mask = 0;
  1426. return err_mask;
  1427. }
  1428. #if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
  1429. #define SATA_MAX_READ_BLK 0xFF
  1430. #else
  1431. #define SATA_MAX_READ_BLK 0xFFFF
  1432. #endif
  1433. ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
  1434. {
  1435. ulong start,blks, buf_addr;
  1436. unsigned short smallblks;
  1437. unsigned long datalen;
  1438. unsigned char *pdata;
  1439. device &= 0xff;
  1440. u32 block = 0;
  1441. u32 n_block = 0;
  1442. if (dev_state != SATA_READY)
  1443. return 0;
  1444. buf_addr = (unsigned long)buffer;
  1445. start = blknr;
  1446. blks = blkcnt;
  1447. do {
  1448. pdata = (unsigned char *)buf_addr;
  1449. if (blks > SATA_MAX_READ_BLK) {
  1450. datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
  1451. smallblks = SATA_MAX_READ_BLK;
  1452. block = (u32)start;
  1453. n_block = (u32)smallblks;
  1454. start += SATA_MAX_READ_BLK;
  1455. blks -= SATA_MAX_READ_BLK;
  1456. } else {
  1457. datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
  1458. datalen = sata_dev_desc[device].blksz * blks;
  1459. smallblks = (unsigned short)blks;
  1460. block = (u32)start;
  1461. n_block = (u32)smallblks;
  1462. start += blks;
  1463. blks = 0;
  1464. }
  1465. if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) {
  1466. printf("sata_dwc : Hard disk read error.\n");
  1467. blkcnt -= blks;
  1468. break;
  1469. }
  1470. buf_addr += datalen;
  1471. } while (blks != 0);
  1472. return (blkcnt);
  1473. }
  1474. static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
  1475. u32 block, u32 n_block)
  1476. {
  1477. struct ata_port *ap = pap;
  1478. struct ata_device *dev = &ata_device;
  1479. struct ata_taskfile tf;
  1480. unsigned int class = ATA_DEV_ATA;
  1481. unsigned int err_mask = 0;
  1482. const char *reason;
  1483. int may_fallback = 1;
  1484. if (dev_state == SATA_ERROR)
  1485. return false;
  1486. ata_dev_select(ap, dev->devno, 1, 1);
  1487. retry:
  1488. memset(&tf, 0, sizeof(tf));
  1489. tf.ctl = ap->ctl;
  1490. ap->print_id = 1;
  1491. ap->flags &= ~ATA_FLAG_DISABLED;
  1492. ap->pdata = pdata;
  1493. tf.device = ATA_DEVICE_OBS;
  1494. temp_n_block = n_block;
  1495. #ifdef CONFIG_LBA48
  1496. tf.command = ATA_CMD_PIO_READ_EXT;
  1497. tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
  1498. tf.hob_feature = 31;
  1499. tf.feature = 31;
  1500. tf.hob_nsect = (n_block >> 8) & 0xff;
  1501. tf.nsect = n_block & 0xff;
  1502. tf.hob_lbah = 0x0;
  1503. tf.hob_lbam = 0x0;
  1504. tf.hob_lbal = (block >> 24) & 0xff;
  1505. tf.lbah = (block >> 16) & 0xff;
  1506. tf.lbam = (block >> 8) & 0xff;
  1507. tf.lbal = block & 0xff;
  1508. tf.device = 1 << 6;
  1509. if (tf.flags & ATA_TFLAG_FUA)
  1510. tf.device |= 1 << 7;
  1511. #else
  1512. tf.command = ATA_CMD_PIO_READ;
  1513. tf.flags |= ATA_TFLAG_LBA ;
  1514. tf.feature = 31;
  1515. tf.nsect = n_block & 0xff;
  1516. tf.lbah = (block >> 16) & 0xff;
  1517. tf.lbam = (block >> 8) & 0xff;
  1518. tf.lbal = block & 0xff;
  1519. tf.device = (block >> 24) & 0xf;
  1520. tf.device |= 1 << 6;
  1521. if (tf.flags & ATA_TFLAG_FUA)
  1522. tf.device |= 1 << 7;
  1523. #endif
  1524. tf.protocol = ATA_PROT_PIO;
  1525. /* Some devices choke if TF registers contain garbage. Make
  1526. * sure those are properly initialized.
  1527. */
  1528. tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
  1529. tf.flags |= ATA_TFLAG_POLLING;
  1530. err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
  1531. if (err_mask) {
  1532. if (err_mask & AC_ERR_NODEV_HINT) {
  1533. printf("READ_SECTORS NODEV after polling detection\n");
  1534. return -ENOENT;
  1535. }
  1536. if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
  1537. /* Device or controller might have reported
  1538. * the wrong device class. Give a shot at the
  1539. * other IDENTIFY if the current one is
  1540. * aborted by the device.
  1541. */
  1542. if (may_fallback) {
  1543. may_fallback = 0;
  1544. if (class == ATA_DEV_ATA) {
  1545. class = ATA_DEV_ATAPI;
  1546. } else {
  1547. class = ATA_DEV_ATA;
  1548. }
  1549. goto retry;
  1550. }
  1551. /* Control reaches here iff the device aborted
  1552. * both flavors of IDENTIFYs which happens
  1553. * sometimes with phantom devices.
  1554. */
  1555. printf("both IDENTIFYs aborted, assuming NODEV\n");
  1556. return -ENOENT;
  1557. }
  1558. reason = "I/O error";
  1559. goto err_out;
  1560. }
  1561. return true;
  1562. err_out:
  1563. printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
  1564. return false;
  1565. }
  1566. #if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
  1567. #define SATA_MAX_WRITE_BLK 0xFF
  1568. #else
  1569. #define SATA_MAX_WRITE_BLK 0xFFFF
  1570. #endif
  1571. ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
  1572. {
  1573. ulong start,blks, buf_addr;
  1574. unsigned short smallblks;
  1575. unsigned long datalen;
  1576. unsigned char *pdata;
  1577. device &= 0xff;
  1578. u32 block = 0;
  1579. u32 n_block = 0;
  1580. if (dev_state != SATA_READY)
  1581. return 0;
  1582. buf_addr = (unsigned long)buffer;
  1583. start = blknr;
  1584. blks = blkcnt;
  1585. do {
  1586. pdata = (unsigned char *)buf_addr;
  1587. if (blks > SATA_MAX_WRITE_BLK) {
  1588. datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK;
  1589. smallblks = SATA_MAX_WRITE_BLK;
  1590. block = (u32)start;
  1591. n_block = (u32)smallblks;
  1592. start += SATA_MAX_WRITE_BLK;
  1593. blks -= SATA_MAX_WRITE_BLK;
  1594. } else {
  1595. datalen = sata_dev_desc[device].blksz * blks;
  1596. smallblks = (unsigned short)blks;
  1597. block = (u32)start;
  1598. n_block = (u32)smallblks;
  1599. start += blks;
  1600. blks = 0;
  1601. }
  1602. if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) {
  1603. printf("sata_dwc : Hard disk read error.\n");
  1604. blkcnt -= blks;
  1605. break;
  1606. }
  1607. buf_addr += datalen;
  1608. } while (blks != 0);
  1609. return (blkcnt);
  1610. }
  1611. static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
  1612. u32 block, u32 n_block)
  1613. {
  1614. struct ata_port *ap = pap;
  1615. struct ata_device *dev = &ata_device;
  1616. struct ata_taskfile tf;
  1617. unsigned int class = ATA_DEV_ATA;
  1618. unsigned int err_mask = 0;
  1619. const char *reason;
  1620. int may_fallback = 1;
  1621. if (dev_state == SATA_ERROR)
  1622. return false;
  1623. ata_dev_select(ap, dev->devno, 1, 1);
  1624. retry:
  1625. memset(&tf, 0, sizeof(tf));
  1626. tf.ctl = ap->ctl;
  1627. ap->print_id = 1;
  1628. ap->flags &= ~ATA_FLAG_DISABLED;
  1629. ap->pdata = pdata;
  1630. tf.device = ATA_DEVICE_OBS;
  1631. temp_n_block = n_block;
  1632. #ifdef CONFIG_LBA48
  1633. tf.command = ATA_CMD_PIO_WRITE_EXT;
  1634. tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE;
  1635. tf.hob_feature = 31;
  1636. tf.feature = 31;
  1637. tf.hob_nsect = (n_block >> 8) & 0xff;
  1638. tf.nsect = n_block & 0xff;
  1639. tf.hob_lbah = 0x0;
  1640. tf.hob_lbam = 0x0;
  1641. tf.hob_lbal = (block >> 24) & 0xff;
  1642. tf.lbah = (block >> 16) & 0xff;
  1643. tf.lbam = (block >> 8) & 0xff;
  1644. tf.lbal = block & 0xff;
  1645. tf.device = 1 << 6;
  1646. if (tf.flags & ATA_TFLAG_FUA)
  1647. tf.device |= 1 << 7;
  1648. #else
  1649. tf.command = ATA_CMD_PIO_WRITE;
  1650. tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE;
  1651. tf.feature = 31;
  1652. tf.nsect = n_block & 0xff;
  1653. tf.lbah = (block >> 16) & 0xff;
  1654. tf.lbam = (block >> 8) & 0xff;
  1655. tf.lbal = block & 0xff;
  1656. tf.device = (block >> 24) & 0xf;
  1657. tf.device |= 1 << 6;
  1658. if (tf.flags & ATA_TFLAG_FUA)
  1659. tf.device |= 1 << 7;
  1660. #endif
  1661. tf.protocol = ATA_PROT_PIO;
  1662. /* Some devices choke if TF registers contain garbage. Make
  1663. * sure those are properly initialized.
  1664. */
  1665. tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
  1666. tf.flags |= ATA_TFLAG_POLLING;
  1667. err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
  1668. if (err_mask) {
  1669. if (err_mask & AC_ERR_NODEV_HINT) {
  1670. printf("READ_SECTORS NODEV after polling detection\n");
  1671. return -ENOENT;
  1672. }
  1673. if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
  1674. /* Device or controller might have reported
  1675. * the wrong device class. Give a shot at the
  1676. * other IDENTIFY if the current one is
  1677. * aborted by the device.
  1678. */
  1679. if (may_fallback) {
  1680. may_fallback = 0;
  1681. if (class == ATA_DEV_ATA) {
  1682. class = ATA_DEV_ATAPI;
  1683. } else {
  1684. class = ATA_DEV_ATA;
  1685. }
  1686. goto retry;
  1687. }
  1688. /* Control reaches here iff the device aborted
  1689. * both flavors of IDENTIFYs which happens
  1690. * sometimes with phantom devices.
  1691. */
  1692. printf("both IDENTIFYs aborted, assuming NODEV\n");
  1693. return -ENOENT;
  1694. }
  1695. reason = "I/O error";
  1696. goto err_out;
  1697. }
  1698. return true;
  1699. err_out:
  1700. printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
  1701. return false;
  1702. }