board.c 11 KB

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  1. /*
  2. * board.c
  3. *
  4. * Board functions for TI AM335X based boards
  5. *
  6. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <spl.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/omap.h>
  16. #include <asm/arch/ddr_defs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/mmc_host_def.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/arch/mem.h>
  22. #include <asm/arch/mux.h>
  23. #include <asm/io.h>
  24. #include <asm/emif.h>
  25. #include <asm/gpio.h>
  26. #include <i2c.h>
  27. #include <miiphy.h>
  28. #include <cpsw.h>
  29. #include <power/tps65217.h>
  30. #include <power/tps65910.h>
  31. #include <environment.h>
  32. #include <watchdog.h>
  33. #include "board.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. /* GPIO that controls power to DDR on EVM-SK */
  36. #define GPIO_DDR_VTT_EN 7
  37. #define DIP_S1 44
  38. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39. static int baltos_set_console(void)
  40. {
  41. int val, i, dips = 0;
  42. char buf[7];
  43. for (i = 0; i < 4; i++) {
  44. sprintf(buf, "dip_s%d", i + 1);
  45. if (gpio_request(DIP_S1 + i, buf)) {
  46. printf("failed to export GPIO %d\n", DIP_S1 + i);
  47. return 0;
  48. }
  49. if (gpio_direction_input(DIP_S1 + i)) {
  50. printf("failed to set GPIO %d direction\n", DIP_S1 + i);
  51. return 0;
  52. }
  53. val = gpio_get_value(DIP_S1 + i);
  54. dips |= val << i;
  55. }
  56. printf("DIPs: 0x%1x\n", (~dips) & 0xf);
  57. if ((dips & 0xf) == 0xe)
  58. setenv("console", "ttyUSB0,115200n8");
  59. return 0;
  60. }
  61. static int read_eeprom(BSP_VS_HWPARAM *header)
  62. {
  63. i2c_set_bus_num(1);
  64. /* Check if baseboard eeprom is available */
  65. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  66. puts("Could not probe the EEPROM; something fundamentally "
  67. "wrong on the I2C bus.\n");
  68. return -ENODEV;
  69. }
  70. /* read the eeprom using i2c */
  71. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  72. sizeof(BSP_VS_HWPARAM))) {
  73. puts("Could not read the EEPROM; something fundamentally"
  74. " wrong on the I2C bus.\n");
  75. return -EIO;
  76. }
  77. if (header->Magic != 0xDEADBEEF) {
  78. printf("Incorrect magic number (0x%x) in EEPROM\n",
  79. header->Magic);
  80. /* fill default values */
  81. header->SystemId = 211;
  82. header->MAC1[0] = 0x00;
  83. header->MAC1[1] = 0x00;
  84. header->MAC1[2] = 0x00;
  85. header->MAC1[3] = 0x00;
  86. header->MAC1[4] = 0x00;
  87. header->MAC1[5] = 0x01;
  88. header->MAC2[0] = 0x00;
  89. header->MAC2[1] = 0x00;
  90. header->MAC2[2] = 0x00;
  91. header->MAC2[3] = 0x00;
  92. header->MAC2[4] = 0x00;
  93. header->MAC2[5] = 0x02;
  94. header->MAC3[0] = 0x00;
  95. header->MAC3[1] = 0x00;
  96. header->MAC3[2] = 0x00;
  97. header->MAC3[3] = 0x00;
  98. header->MAC3[4] = 0x00;
  99. header->MAC3[5] = 0x03;
  100. }
  101. return 0;
  102. }
  103. #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  104. static const struct ddr_data ddr3_baltos_data = {
  105. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  106. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  107. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  108. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  109. };
  110. static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
  111. .cmd0csratio = MT41K256M16HA125E_RATIO,
  112. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  113. .cmd1csratio = MT41K256M16HA125E_RATIO,
  114. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  115. .cmd2csratio = MT41K256M16HA125E_RATIO,
  116. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  117. };
  118. static struct emif_regs ddr3_baltos_emif_reg_data = {
  119. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  120. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  121. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  122. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  123. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  124. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  125. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  126. };
  127. #ifdef CONFIG_SPL_OS_BOOT
  128. int spl_start_uboot(void)
  129. {
  130. /* break into full u-boot on 'c' */
  131. return (serial_tstc() && serial_getc() == 'c');
  132. }
  133. #endif
  134. #define OSC (V_OSCK/1000000)
  135. const struct dpll_params dpll_ddr = {
  136. 266, OSC-1, 1, -1, -1, -1, -1};
  137. const struct dpll_params dpll_ddr_evm_sk = {
  138. 303, OSC-1, 1, -1, -1, -1, -1};
  139. const struct dpll_params dpll_ddr_baltos = {
  140. 400, OSC-1, 1, -1, -1, -1, -1};
  141. void am33xx_spl_board_init(void)
  142. {
  143. int mpu_vdd;
  144. int sil_rev;
  145. /* Get the frequency */
  146. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  147. /*
  148. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  149. * MPU frequencies we support we use a CORE voltage of
  150. * 1.1375V. For MPU voltage we need to switch based on
  151. * the frequency we are running at.
  152. */
  153. i2c_set_bus_num(1);
  154. printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
  155. if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
  156. puts("i2c: cannot access TPS65910\n");
  157. return;
  158. }
  159. /*
  160. * Depending on MPU clock and PG we will need a different
  161. * VDD to drive at that speed.
  162. */
  163. sil_rev = readl(&cdev->deviceid) >> 28;
  164. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
  165. dpll_mpu_opp100.m);
  166. /* Tell the TPS65910 to use i2c */
  167. tps65910_set_i2c_control();
  168. /* First update MPU voltage. */
  169. if (tps65910_voltage_update(MPU, mpu_vdd))
  170. return;
  171. /* Second, update the CORE voltage. */
  172. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
  173. return;
  174. /* Set CORE Frequencies to OPP100 */
  175. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  176. /* Set MPU Frequency to what we detected now that voltages are set */
  177. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  178. writel(0x000010ff, PRM_DEVICE_INST + 4);
  179. }
  180. const struct dpll_params *get_dpll_ddr_params(void)
  181. {
  182. enable_i2c1_pin_mux();
  183. i2c_set_bus_num(1);
  184. return &dpll_ddr_baltos;
  185. }
  186. void set_uart_mux_conf(void)
  187. {
  188. enable_uart0_pin_mux();
  189. }
  190. void set_mux_conf_regs(void)
  191. {
  192. enable_board_pin_mux();
  193. }
  194. const struct ctrl_ioregs ioregs_baltos = {
  195. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  196. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  197. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  198. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  199. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  200. };
  201. void sdram_init(void)
  202. {
  203. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  204. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  205. config_ddr(400, &ioregs_baltos,
  206. &ddr3_baltos_data,
  207. &ddr3_baltos_cmd_ctrl_data,
  208. &ddr3_baltos_emif_reg_data, 0);
  209. }
  210. #endif
  211. /*
  212. * Basic board specific setup. Pinmux has been handled already.
  213. */
  214. int board_init(void)
  215. {
  216. #if defined(CONFIG_HW_WATCHDOG)
  217. hw_watchdog_init();
  218. #endif
  219. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  220. #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
  221. gpmc_init();
  222. #endif
  223. return 0;
  224. }
  225. int ft_board_setup(void *blob, bd_t *bd)
  226. {
  227. int node, ret;
  228. unsigned char mac_addr[6];
  229. BSP_VS_HWPARAM header;
  230. /* get production data */
  231. if (read_eeprom(&header))
  232. return 0;
  233. /* setup MAC1 */
  234. mac_addr[0] = header.MAC1[0];
  235. mac_addr[1] = header.MAC1[1];
  236. mac_addr[2] = header.MAC1[2];
  237. mac_addr[3] = header.MAC1[3];
  238. mac_addr[4] = header.MAC1[4];
  239. mac_addr[5] = header.MAC1[5];
  240. node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
  241. if (node < 0) {
  242. printf("no /soc/fman/ethernet path offset\n");
  243. return -ENODEV;
  244. }
  245. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  246. if (ret) {
  247. printf("error setting local-mac-address property\n");
  248. return -ENODEV;
  249. }
  250. /* setup MAC2 */
  251. mac_addr[0] = header.MAC2[0];
  252. mac_addr[1] = header.MAC2[1];
  253. mac_addr[2] = header.MAC2[2];
  254. mac_addr[3] = header.MAC2[3];
  255. mac_addr[4] = header.MAC2[4];
  256. mac_addr[5] = header.MAC2[5];
  257. node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
  258. if (node < 0) {
  259. printf("no /soc/fman/ethernet path offset\n");
  260. return -ENODEV;
  261. }
  262. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  263. if (ret) {
  264. printf("error setting local-mac-address property\n");
  265. return -ENODEV;
  266. }
  267. printf("\nFDT was successfully setup\n");
  268. return 0;
  269. }
  270. static struct module_pin_mux dip_pin_mux[] = {
  271. {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
  272. {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
  273. {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
  274. {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
  275. {-1},
  276. };
  277. #ifdef CONFIG_BOARD_LATE_INIT
  278. int board_late_init(void)
  279. {
  280. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  281. BSP_VS_HWPARAM header;
  282. char model[4];
  283. /* get production data */
  284. if (read_eeprom(&header)) {
  285. strcpy(model, "211");
  286. } else {
  287. sprintf(model, "%d", header.SystemId);
  288. if (header.SystemId == 215) {
  289. configure_module_pin_mux(dip_pin_mux);
  290. baltos_set_console();
  291. }
  292. }
  293. setenv("board_name", model);
  294. #endif
  295. return 0;
  296. }
  297. #endif
  298. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  299. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  300. static void cpsw_control(int enabled)
  301. {
  302. /* VTP can be added here */
  303. return;
  304. }
  305. static struct cpsw_slave_data cpsw_slaves[] = {
  306. {
  307. .slave_reg_ofs = 0x208,
  308. .sliver_reg_ofs = 0xd80,
  309. .phy_addr = 0,
  310. },
  311. {
  312. .slave_reg_ofs = 0x308,
  313. .sliver_reg_ofs = 0xdc0,
  314. .phy_addr = 7,
  315. },
  316. };
  317. static struct cpsw_platform_data cpsw_data = {
  318. .mdio_base = CPSW_MDIO_BASE,
  319. .cpsw_base = CPSW_BASE,
  320. .mdio_div = 0xff,
  321. .channels = 8,
  322. .cpdma_reg_ofs = 0x800,
  323. .slaves = 2,
  324. .slave_data = cpsw_slaves,
  325. .active_slave = 1,
  326. .ale_reg_ofs = 0xd00,
  327. .ale_entries = 1024,
  328. .host_port_reg_ofs = 0x108,
  329. .hw_stats_reg_ofs = 0x900,
  330. .bd_ram_ofs = 0x2000,
  331. .mac_control = (1 << 5),
  332. .control = cpsw_control,
  333. .host_port_num = 0,
  334. .version = CPSW_CTRL_VERSION_2,
  335. };
  336. #endif
  337. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
  338. && defined(CONFIG_SPL_BUILD)) || \
  339. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  340. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  341. !defined(CONFIG_SPL_BUILD))
  342. int board_eth_init(bd_t *bis)
  343. {
  344. int rv, n = 0;
  345. uint8_t mac_addr[6];
  346. uint32_t mac_hi, mac_lo;
  347. __maybe_unused struct am335x_baseboard_id header;
  348. /*
  349. * Note here that we're using CPSW1 since that has a 1Gbit PHY while
  350. * CSPW0 has a 100Mbit PHY.
  351. *
  352. * On product, CPSW1 maps to port labeled WAN.
  353. */
  354. /* try reading mac address from efuse */
  355. mac_lo = readl(&cdev->macid1l);
  356. mac_hi = readl(&cdev->macid1h);
  357. mac_addr[0] = mac_hi & 0xFF;
  358. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  359. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  360. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  361. mac_addr[4] = mac_lo & 0xFF;
  362. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  363. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  364. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  365. if (!getenv("ethaddr")) {
  366. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  367. if (is_valid_ethaddr(mac_addr))
  368. eth_setenv_enetaddr("ethaddr", mac_addr);
  369. }
  370. #ifdef CONFIG_DRIVER_TI_CPSW
  371. writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
  372. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
  373. rv = cpsw_register(&cpsw_data);
  374. if (rv < 0)
  375. printf("Error %d registering CPSW switch\n", rv);
  376. else
  377. n += rv;
  378. #endif
  379. /*
  380. *
  381. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  382. * operating points. So we must set the TX clock delay feature
  383. * in the AR8051 PHY. Since we only support a single ethernet
  384. * device in U-Boot, we only do this for the first instance.
  385. */
  386. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  387. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  388. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  389. #define AR8051_RGMII_TX_CLK_DLY 0x100
  390. const char *devname;
  391. devname = miiphy_get_current_dev();
  392. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
  393. AR8051_DEBUG_RGMII_CLK_DLY_REG);
  394. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
  395. AR8051_RGMII_TX_CLK_DLY);
  396. #endif
  397. return n;
  398. }
  399. #endif