board.c 10 KB

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  1. /*
  2. * Board functions for TI AM335X based rut board
  3. * (C) Copyright 2013 Siemens Schweiz AG
  4. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * u-boot:/board/ti/am335x/board.c
  8. *
  9. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <errno.h>
  15. #include <spi.h>
  16. #include <spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/io.h>
  26. #include <asm/emif.h>
  27. #include <asm/gpio.h>
  28. #include <i2c.h>
  29. #include <miiphy.h>
  30. #include <cpsw.h>
  31. #include <video.h>
  32. #include <watchdog.h>
  33. #include "board.h"
  34. #include "../common/factoryset.h"
  35. #include "../../../drivers/video/da8xx-fb.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. /*
  38. * Read header information from EEPROM into global structure.
  39. */
  40. static int read_eeprom(void)
  41. {
  42. return 0;
  43. }
  44. #ifdef CONFIG_SPL_BUILD
  45. static void board_init_ddr(void)
  46. {
  47. struct emif_regs rut_ddr3_emif_reg_data = {
  48. .sdram_config = 0x61C04AB2,
  49. .sdram_tim1 = 0x0888A39B,
  50. .sdram_tim2 = 0x26337FDA,
  51. .sdram_tim3 = 0x501F830F,
  52. .emif_ddr_phy_ctlr_1 = 0x6,
  53. .zq_config = 0x50074BE4,
  54. .ref_ctrl = 0x93B,
  55. };
  56. struct ddr_data rut_ddr3_data = {
  57. .datardsratio0 = 0x3b,
  58. .datawdsratio0 = 0x85,
  59. .datafwsratio0 = 0x100,
  60. .datawrsratio0 = 0xc1,
  61. };
  62. struct cmd_control rut_ddr3_cmd_ctrl_data = {
  63. .cmd0csratio = 0x40,
  64. .cmd0iclkout = 1,
  65. .cmd1csratio = 0x40,
  66. .cmd1iclkout = 1,
  67. .cmd2csratio = 0x40,
  68. .cmd2iclkout = 1,
  69. };
  70. const struct ctrl_ioregs ioregs = {
  71. .cm0ioctl = RUT_IOCTRL_VAL,
  72. .cm1ioctl = RUT_IOCTRL_VAL,
  73. .cm2ioctl = RUT_IOCTRL_VAL,
  74. .dt0ioctl = RUT_IOCTRL_VAL,
  75. .dt1ioctl = RUT_IOCTRL_VAL,
  76. };
  77. config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
  78. &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
  79. }
  80. static int request_and_pulse_reset(int gpio, const char *name)
  81. {
  82. int ret;
  83. const int delay_us = 2000; /* 2ms */
  84. ret = gpio_request(gpio, name);
  85. if (ret < 0) {
  86. printf("%s: Unable to request %s\n", __func__, name);
  87. goto err;
  88. }
  89. ret = gpio_direction_output(gpio, 0);
  90. if (ret < 0) {
  91. printf("%s: Unable to set %s as output\n", __func__, name);
  92. goto err_free_gpio;
  93. }
  94. udelay(delay_us);
  95. gpio_set_value(gpio, 1);
  96. return 0;
  97. err_free_gpio:
  98. gpio_free(gpio);
  99. err:
  100. return ret;
  101. }
  102. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  103. #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
  104. #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
  105. #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
  106. #define REQUEST_AND_PULSE_RESET(N) \
  107. request_and_pulse_reset(N, #N);
  108. static void spl_siemens_board_init(void)
  109. {
  110. REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
  111. REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
  112. REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
  113. }
  114. #endif /* if def CONFIG_SPL_BUILD */
  115. #if defined(CONFIG_DRIVER_TI_CPSW)
  116. static void cpsw_control(int enabled)
  117. {
  118. /* VTP can be added here */
  119. return;
  120. }
  121. static struct cpsw_slave_data cpsw_slaves[] = {
  122. {
  123. .slave_reg_ofs = 0x208,
  124. .sliver_reg_ofs = 0xd80,
  125. .phy_addr = 1,
  126. .phy_if = PHY_INTERFACE_MODE_RMII,
  127. },
  128. {
  129. .slave_reg_ofs = 0x308,
  130. .sliver_reg_ofs = 0xdc0,
  131. .phy_addr = 0,
  132. .phy_if = PHY_INTERFACE_MODE_RMII,
  133. },
  134. };
  135. static struct cpsw_platform_data cpsw_data = {
  136. .mdio_base = CPSW_MDIO_BASE,
  137. .cpsw_base = CPSW_BASE,
  138. .mdio_div = 0xff,
  139. .channels = 8,
  140. .cpdma_reg_ofs = 0x800,
  141. .slaves = 1,
  142. .slave_data = cpsw_slaves,
  143. .ale_reg_ofs = 0xd00,
  144. .ale_entries = 1024,
  145. .host_port_reg_ofs = 0x108,
  146. .hw_stats_reg_ofs = 0x900,
  147. .bd_ram_ofs = 0x2000,
  148. .mac_control = (1 << 5),
  149. .control = cpsw_control,
  150. .host_port_num = 0,
  151. .version = CPSW_CTRL_VERSION_2,
  152. };
  153. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  154. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  155. int board_eth_init(bd_t *bis)
  156. {
  157. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  158. int n = 0;
  159. int rv;
  160. #ifndef CONFIG_SPL_BUILD
  161. factoryset_setenv();
  162. #endif
  163. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  164. writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
  165. rv = cpsw_register(&cpsw_data);
  166. if (rv < 0)
  167. printf("Error %d registering CPSW switch\n", rv);
  168. else
  169. n += rv;
  170. return n;
  171. }
  172. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  173. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  174. #if defined(CONFIG_HW_WATCHDOG)
  175. static bool hw_watchdog_init_done;
  176. static int hw_watchdog_trigger_level;
  177. void hw_watchdog_reset(void)
  178. {
  179. if (!hw_watchdog_init_done)
  180. return;
  181. hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
  182. gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  183. }
  184. void hw_watchdog_init(void)
  185. {
  186. gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
  187. gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  188. hw_watchdog_reset();
  189. hw_watchdog_init_done = 1;
  190. }
  191. #endif /* defined(CONFIG_HW_WATCHDOG) */
  192. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  193. static struct da8xx_panel lcd_panels[] = {
  194. /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
  195. [0] = {
  196. .name = "KWH043MC17-F01",
  197. .width = 480,
  198. .height = 800,
  199. .hfp = 50, /* no spec, "don't care" values */
  200. .hbp = 50,
  201. .hsw = 50,
  202. .vfp = 50,
  203. .vbp = 50,
  204. .vsw = 50,
  205. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  206. .invert_pxl_clk = 1,
  207. },
  208. /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
  209. [1] = {
  210. .name = "KWH043ST20-F01",
  211. .width = 480,
  212. .height = 800,
  213. .hfp = 50, /* no spec, "don't care" values */
  214. .hbp = 50,
  215. .hsw = 50,
  216. .vfp = 50,
  217. .vbp = 50,
  218. .vsw = 50,
  219. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  220. .invert_pxl_clk = 1,
  221. },
  222. /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
  223. [2] = {
  224. .name = "MI0430VT-1",
  225. .width = 480,
  226. .height = 800,
  227. .hfp = 50, /* no spec, "don't care" values */
  228. .hbp = 50,
  229. .hsw = 50,
  230. .vfp = 50,
  231. .vbp = 50,
  232. .vsw = 50,
  233. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  234. .invert_pxl_clk = 1,
  235. },
  236. };
  237. static const struct display_panel disp_panels[] = {
  238. [0] = {
  239. WVGA,
  240. 16, /* RGB 888 */
  241. 16,
  242. COLOR_ACTIVE,
  243. },
  244. [1] = {
  245. WVGA,
  246. 16, /* RGB 888 */
  247. 16,
  248. COLOR_ACTIVE,
  249. },
  250. [2] = {
  251. WVGA,
  252. 24, /* RGB 888 */
  253. 16,
  254. COLOR_ACTIVE,
  255. },
  256. };
  257. static const struct lcd_ctrl_config lcd_cfgs[] = {
  258. [0] = {
  259. &disp_panels[0],
  260. .ac_bias = 255,
  261. .ac_bias_intrpt = 0,
  262. .dma_burst_sz = 16,
  263. .bpp = 16,
  264. .fdd = 0x80,
  265. .tft_alt_mode = 0,
  266. .stn_565_mode = 0,
  267. .mono_8bit_mode = 0,
  268. .invert_line_clock = 1,
  269. .invert_frm_clock = 1,
  270. .sync_edge = 0,
  271. .sync_ctrl = 1,
  272. .raster_order = 0,
  273. },
  274. [1] = {
  275. &disp_panels[1],
  276. .ac_bias = 255,
  277. .ac_bias_intrpt = 0,
  278. .dma_burst_sz = 16,
  279. .bpp = 16,
  280. .fdd = 0x80,
  281. .tft_alt_mode = 0,
  282. .stn_565_mode = 0,
  283. .mono_8bit_mode = 0,
  284. .invert_line_clock = 1,
  285. .invert_frm_clock = 1,
  286. .sync_edge = 0,
  287. .sync_ctrl = 1,
  288. .raster_order = 0,
  289. },
  290. [2] = {
  291. &disp_panels[2],
  292. .ac_bias = 255,
  293. .ac_bias_intrpt = 0,
  294. .dma_burst_sz = 16,
  295. .bpp = 24,
  296. .fdd = 0x80,
  297. .tft_alt_mode = 0,
  298. .stn_565_mode = 0,
  299. .mono_8bit_mode = 0,
  300. .invert_line_clock = 1,
  301. .invert_frm_clock = 1,
  302. .sync_edge = 0,
  303. .sync_ctrl = 1,
  304. .raster_order = 0,
  305. },
  306. };
  307. /* no console on this board */
  308. int board_cfb_skip(void)
  309. {
  310. return 1;
  311. }
  312. #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
  313. #define PLL_GET_N(v) (v & 0x7f)
  314. static struct dpll_regs dpll_lcd_regs = {
  315. .cm_clkmode_dpll = CM_WKUP + 0x98,
  316. .cm_idlest_dpll = CM_WKUP + 0x48,
  317. .cm_clksel_dpll = CM_WKUP + 0x54,
  318. };
  319. static int get_clk(struct dpll_regs *dpll_regs)
  320. {
  321. unsigned int val;
  322. unsigned int m, n;
  323. int f = 0;
  324. val = readl(dpll_regs->cm_clksel_dpll);
  325. m = PLL_GET_M(val);
  326. n = PLL_GET_N(val);
  327. f = (m * V_OSCK) / n;
  328. return f;
  329. };
  330. int clk_get(int clk)
  331. {
  332. return get_clk(&dpll_lcd_regs);
  333. };
  334. static int conf_disp_pll(int m, int n)
  335. {
  336. struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  337. struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
  338. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  339. struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  340. #endif
  341. u32 *const clk_domains[] = {
  342. &cmper->lcdclkctrl,
  343. 0
  344. };
  345. u32 *const clk_modules_explicit_en[] = {
  346. &cmper->lcdclkctrl,
  347. &cmper->lcdcclkstctrl,
  348. &cmper->spi1clkctrl,
  349. 0
  350. };
  351. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  352. do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
  353. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  354. writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
  355. writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
  356. writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
  357. &cmwkup->clkmoddplldisp); /* 0x98 */
  358. #endif
  359. return 0;
  360. }
  361. static int set_gpio(int gpio, int state)
  362. {
  363. gpio_request(gpio, "temp");
  364. gpio_direction_output(gpio, state);
  365. gpio_set_value(gpio, state);
  366. gpio_free(gpio);
  367. return 0;
  368. }
  369. static int enable_lcd(void)
  370. {
  371. unsigned char buf[1];
  372. set_gpio(BOARD_LCD_RESET, 0);
  373. mdelay(1);
  374. set_gpio(BOARD_LCD_RESET, 1);
  375. mdelay(1);
  376. /* spi lcd init */
  377. kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
  378. /* backlight on */
  379. buf[0] = 0xf;
  380. i2c_write(0x24, 0x7, 1, buf, 1);
  381. buf[0] = 0x3f;
  382. i2c_write(0x24, 0x8, 1, buf, 1);
  383. return 0;
  384. }
  385. int arch_early_init_r(void)
  386. {
  387. enable_lcd();
  388. return 0;
  389. }
  390. static int board_video_init(void)
  391. {
  392. int i;
  393. int anzdisp = ARRAY_SIZE(lcd_panels);
  394. int display = 1;
  395. for (i = 0; i < anzdisp; i++) {
  396. if (strncmp((const char *)factory_dat.disp_name,
  397. lcd_panels[i].name,
  398. strlen((const char *)factory_dat.disp_name)) == 0) {
  399. printf("DISPLAY: %s\n", factory_dat.disp_name);
  400. break;
  401. }
  402. }
  403. if (i == anzdisp) {
  404. i = 1;
  405. printf("%s: %s not found, using default %s\n", __func__,
  406. factory_dat.disp_name, lcd_panels[i].name);
  407. }
  408. conf_disp_pll(24, 1);
  409. da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
  410. lcd_cfgs[display].bpp);
  411. return 0;
  412. }
  413. #endif /* ifdef CONFIG_VIDEO */
  414. #ifdef CONFIG_BOARD_LATE_INIT
  415. int board_late_init(void)
  416. {
  417. int ret;
  418. char tmp[2 * MAX_STRING_LENGTH + 2];
  419. omap_nand_switch_ecc(1, 8);
  420. if (factory_dat.asn[0] != 0)
  421. sprintf(tmp, "%s_%s", factory_dat.asn,
  422. factory_dat.comp_version);
  423. else
  424. strcpy(tmp, "QMX7.E38_4.0");
  425. ret = setenv("boardid", tmp);
  426. if (ret)
  427. printf("error setting board id\n");
  428. return 0;
  429. }
  430. #endif
  431. #include "../common/board.c"