eth.c 23 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <netdev.h>
  9. #include <asm/mmu.h>
  10. #include <asm/processor.h>
  11. #include <asm/cache.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_law.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <asm/fsl_portals.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <malloc.h>
  19. #include <fm_eth.h>
  20. #include <fsl_mdio.h>
  21. #include <miiphy.h>
  22. #include <phy.h>
  23. #include <fsl_dtsec.h>
  24. #include <asm/fsl_serdes.h>
  25. #include <hwconfig.h>
  26. #include "../common/qixis.h"
  27. #include "../common/fman.h"
  28. #include "t4240qds_qixis.h"
  29. #define EMI_NONE 0xFFFFFFFF
  30. #define EMI1_RGMII 0
  31. #define EMI1_SLOT1 1
  32. #define EMI1_SLOT2 2
  33. #define EMI1_SLOT3 3
  34. #define EMI1_SLOT4 4
  35. #define EMI1_SLOT5 5
  36. #define EMI1_SLOT7 7
  37. #define EMI2 8
  38. /* Slot6 and Slot8 do not have EMI connections */
  39. static int mdio_mux[NUM_FM_PORTS];
  40. static const char *mdio_names[] = {
  41. "T4240QDS_MDIO0",
  42. "T4240QDS_MDIO1",
  43. "T4240QDS_MDIO2",
  44. "T4240QDS_MDIO3",
  45. "T4240QDS_MDIO4",
  46. "T4240QDS_MDIO5",
  47. "NULL",
  48. "T4240QDS_MDIO7",
  49. "T4240QDS_10GC",
  50. };
  51. static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  52. static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  53. static u8 slot_qsgmii_phyaddr[5][4] = {
  54. {0, 0, 0, 0},/* not used, to make index match slot No. */
  55. {0, 1, 2, 3},
  56. {4, 5, 6, 7},
  57. {8, 9, 0xa, 0xb},
  58. {0xc, 0xd, 0xe, 0xf},
  59. };
  60. static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  61. static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  62. {
  63. return mdio_names[muxval];
  64. }
  65. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  66. {
  67. struct mii_dev *bus;
  68. const char *name = t4240qds_mdio_name_for_muxval(muxval);
  69. if (!name) {
  70. printf("No bus for muxval %x\n", muxval);
  71. return NULL;
  72. }
  73. bus = miiphy_get_dev_by_name(name);
  74. if (!bus) {
  75. printf("No bus by name %s\n", name);
  76. return NULL;
  77. }
  78. return bus;
  79. }
  80. struct t4240qds_mdio {
  81. u8 muxval;
  82. struct mii_dev *realbus;
  83. };
  84. static void t4240qds_mux_mdio(u8 muxval)
  85. {
  86. u8 brdcfg4;
  87. if ((muxval < 6) || (muxval == 7)) {
  88. brdcfg4 = QIXIS_READ(brdcfg[4]);
  89. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  90. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  91. QIXIS_WRITE(brdcfg[4], brdcfg4);
  92. }
  93. }
  94. static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  95. int regnum)
  96. {
  97. struct t4240qds_mdio *priv = bus->priv;
  98. t4240qds_mux_mdio(priv->muxval);
  99. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  100. }
  101. static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  102. int regnum, u16 value)
  103. {
  104. struct t4240qds_mdio *priv = bus->priv;
  105. t4240qds_mux_mdio(priv->muxval);
  106. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  107. }
  108. static int t4240qds_mdio_reset(struct mii_dev *bus)
  109. {
  110. struct t4240qds_mdio *priv = bus->priv;
  111. return priv->realbus->reset(priv->realbus);
  112. }
  113. static int t4240qds_mdio_init(char *realbusname, u8 muxval)
  114. {
  115. struct t4240qds_mdio *pmdio;
  116. struct mii_dev *bus = mdio_alloc();
  117. if (!bus) {
  118. printf("Failed to allocate T4240QDS MDIO bus\n");
  119. return -1;
  120. }
  121. pmdio = malloc(sizeof(*pmdio));
  122. if (!pmdio) {
  123. printf("Failed to allocate T4240QDS private data\n");
  124. free(bus);
  125. return -1;
  126. }
  127. bus->read = t4240qds_mdio_read;
  128. bus->write = t4240qds_mdio_write;
  129. bus->reset = t4240qds_mdio_reset;
  130. strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
  131. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  132. if (!pmdio->realbus) {
  133. printf("No bus with name %s\n", realbusname);
  134. free(bus);
  135. free(pmdio);
  136. return -1;
  137. }
  138. pmdio->muxval = muxval;
  139. bus->priv = pmdio;
  140. return mdio_register(bus);
  141. }
  142. void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
  143. enum fm_port port, int offset)
  144. {
  145. int interface = fm_info_get_enet_if(port);
  146. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  147. u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  148. prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  149. if (interface == PHY_INTERFACE_MODE_SGMII ||
  150. interface == PHY_INTERFACE_MODE_QSGMII) {
  151. switch (port) {
  152. case FM1_DTSEC1:
  153. if (qsgmiiphy_fix[port])
  154. fdt_set_phy_handle(blob, prop, pa,
  155. "sgmii_phy21");
  156. break;
  157. case FM1_DTSEC2:
  158. if (qsgmiiphy_fix[port])
  159. fdt_set_phy_handle(blob, prop, pa,
  160. "sgmii_phy22");
  161. break;
  162. case FM1_DTSEC3:
  163. if (qsgmiiphy_fix[port])
  164. fdt_set_phy_handle(blob, prop, pa,
  165. "sgmii_phy23");
  166. break;
  167. case FM1_DTSEC4:
  168. if (qsgmiiphy_fix[port])
  169. fdt_set_phy_handle(blob, prop, pa,
  170. "sgmii_phy24");
  171. break;
  172. case FM1_DTSEC6:
  173. if (qsgmiiphy_fix[port])
  174. fdt_set_phy_handle(blob, prop, pa,
  175. "sgmii_phy12");
  176. break;
  177. case FM1_DTSEC9:
  178. if (qsgmiiphy_fix[port])
  179. fdt_set_phy_handle(blob, prop, pa,
  180. "sgmii_phy14");
  181. else
  182. fdt_set_phy_handle(blob, prop, pa,
  183. "phy_sgmii4");
  184. break;
  185. case FM1_DTSEC10:
  186. if (qsgmiiphy_fix[port])
  187. fdt_set_phy_handle(blob, prop, pa,
  188. "sgmii_phy13");
  189. else
  190. fdt_set_phy_handle(blob, prop, pa,
  191. "phy_sgmii3");
  192. break;
  193. case FM2_DTSEC1:
  194. if (qsgmiiphy_fix[port])
  195. fdt_set_phy_handle(blob, prop, pa,
  196. "sgmii_phy41");
  197. break;
  198. case FM2_DTSEC2:
  199. if (qsgmiiphy_fix[port])
  200. fdt_set_phy_handle(blob, prop, pa,
  201. "sgmii_phy42");
  202. break;
  203. case FM2_DTSEC3:
  204. if (qsgmiiphy_fix[port])
  205. fdt_set_phy_handle(blob, prop, pa,
  206. "sgmii_phy43");
  207. break;
  208. case FM2_DTSEC4:
  209. if (qsgmiiphy_fix[port])
  210. fdt_set_phy_handle(blob, prop, pa,
  211. "sgmii_phy44");
  212. break;
  213. case FM2_DTSEC6:
  214. if (qsgmiiphy_fix[port])
  215. fdt_set_phy_handle(blob, prop, pa,
  216. "sgmii_phy32");
  217. break;
  218. case FM2_DTSEC9:
  219. if (qsgmiiphy_fix[port])
  220. fdt_set_phy_handle(blob, prop, pa,
  221. "sgmii_phy34");
  222. else
  223. fdt_set_phy_handle(blob, prop, pa,
  224. "phy_sgmii12");
  225. break;
  226. case FM2_DTSEC10:
  227. if (qsgmiiphy_fix[port])
  228. fdt_set_phy_handle(blob, prop, pa,
  229. "sgmii_phy33");
  230. else
  231. fdt_set_phy_handle(blob, prop, pa,
  232. "phy_sgmii11");
  233. break;
  234. default:
  235. break;
  236. }
  237. } else if (interface == PHY_INTERFACE_MODE_XGMII &&
  238. ((prtcl2 == 55) || (prtcl2 == 57))) {
  239. /*
  240. * if the 10G is XFI, check hwconfig to see what is the
  241. * media type, there are two types, fiber or copper,
  242. * fix the dtb accordingly.
  243. */
  244. int media_type = 0;
  245. struct fixed_link f_link;
  246. char lane_mode[20] = {"10GBASE-KR"};
  247. char buf[32] = "serdes-2,";
  248. int off;
  249. switch (port) {
  250. case FM1_10GEC1:
  251. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
  252. media_type = 1;
  253. fdt_set_phy_handle(blob, prop, pa,
  254. "phy_xfi1");
  255. sprintf(buf, "%s%s%s", buf, "lane-a,",
  256. (char *)lane_mode);
  257. }
  258. break;
  259. case FM1_10GEC2:
  260. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
  261. media_type = 1;
  262. fdt_set_phy_handle(blob, prop, pa,
  263. "phy_xfi2");
  264. sprintf(buf, "%s%s%s", buf, "lane-b,",
  265. (char *)lane_mode);
  266. }
  267. break;
  268. case FM2_10GEC1:
  269. if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
  270. media_type = 1;
  271. fdt_set_phy_handle(blob, prop, pa,
  272. "phy_xfi3");
  273. sprintf(buf, "%s%s%s", buf, "lane-d,",
  274. (char *)lane_mode);
  275. }
  276. break;
  277. case FM2_10GEC2:
  278. if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
  279. media_type = 1;
  280. fdt_set_phy_handle(blob, prop, pa,
  281. "phy_xfi4");
  282. sprintf(buf, "%s%s%s", buf, "lane-c,",
  283. (char *)lane_mode);
  284. }
  285. break;
  286. default:
  287. return;
  288. }
  289. if (!media_type) {
  290. /* fixed-link is used for XFI fiber cable */
  291. fdt_delprop(blob, offset, "phy-handle");
  292. f_link.phy_id = port;
  293. f_link.duplex = 1;
  294. f_link.link_speed = 10000;
  295. f_link.pause = 0;
  296. f_link.asym_pause = 0;
  297. fdt_setprop(blob, offset, "fixed-link", &f_link,
  298. sizeof(f_link));
  299. } else {
  300. /* set property for copper cable */
  301. off = fdt_node_offset_by_compat_reg(blob,
  302. "fsl,fman-memac-mdio", pa + 0x1000);
  303. fdt_setprop_string(blob, off, "lane-instance", buf);
  304. }
  305. }
  306. }
  307. void fdt_fixup_board_enet(void *fdt)
  308. {
  309. int i;
  310. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  311. u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  312. prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  313. for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
  314. switch (fm_info_get_enet_if(i)) {
  315. case PHY_INTERFACE_MODE_SGMII:
  316. case PHY_INTERFACE_MODE_QSGMII:
  317. switch (mdio_mux[i]) {
  318. case EMI1_SLOT1:
  319. fdt_status_okay_by_alias(fdt, "emi1_slot1");
  320. break;
  321. case EMI1_SLOT2:
  322. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  323. break;
  324. case EMI1_SLOT3:
  325. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  326. break;
  327. case EMI1_SLOT4:
  328. fdt_status_okay_by_alias(fdt, "emi1_slot4");
  329. break;
  330. default:
  331. break;
  332. }
  333. break;
  334. case PHY_INTERFACE_MODE_XGMII:
  335. /* check if it's XFI interface for 10g */
  336. if ((prtcl2 == 55) || (prtcl2 == 57)) {
  337. if (i == FM1_10GEC1 && hwconfig_sub(
  338. "fsl_10gkr_copper", "fm1_10g1"))
  339. fdt_status_okay_by_alias(
  340. fdt, "xfi_pcs_mdio1");
  341. if (i == FM1_10GEC2 && hwconfig_sub(
  342. "fsl_10gkr_copper", "fm1_10g2"))
  343. fdt_status_okay_by_alias(
  344. fdt, "xfi_pcs_mdio2");
  345. if (i == FM2_10GEC1 && hwconfig_sub(
  346. "fsl_10gkr_copper", "fm2_10g1"))
  347. fdt_status_okay_by_alias(
  348. fdt, "xfi_pcs_mdio3");
  349. if (i == FM2_10GEC2 && hwconfig_sub(
  350. "fsl_10gkr_copper", "fm2_10g2"))
  351. fdt_status_okay_by_alias(
  352. fdt, "xfi_pcs_mdio4");
  353. break;
  354. }
  355. switch (i) {
  356. case FM1_10GEC1:
  357. fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
  358. break;
  359. case FM1_10GEC2:
  360. fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
  361. break;
  362. case FM2_10GEC1:
  363. fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
  364. break;
  365. case FM2_10GEC2:
  366. fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
  367. break;
  368. default:
  369. break;
  370. }
  371. break;
  372. default:
  373. break;
  374. }
  375. }
  376. }
  377. static void initialize_qsgmiiphy_fix(void)
  378. {
  379. int i;
  380. unsigned short reg;
  381. for (i = 1; i <= 4; i++) {
  382. /*
  383. * Try to read if a SGMII card is used, we do it slot by slot.
  384. * if a SGMII PHY address is valid on a slot, then we mark
  385. * all ports on the slot, then fix the PHY address for the
  386. * marked port when doing dtb fixup.
  387. */
  388. if (miiphy_read(mdio_names[i],
  389. SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
  390. debug("Slot%d PHY ID register 2 read failed\n", i);
  391. continue;
  392. }
  393. debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
  394. if (reg == 0xFFFF) {
  395. /* No physical device present at this address */
  396. continue;
  397. }
  398. switch (i) {
  399. case 1:
  400. qsgmiiphy_fix[FM1_DTSEC5] = 1;
  401. qsgmiiphy_fix[FM1_DTSEC6] = 1;
  402. qsgmiiphy_fix[FM1_DTSEC9] = 1;
  403. qsgmiiphy_fix[FM1_DTSEC10] = 1;
  404. slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
  405. slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
  406. slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
  407. slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
  408. break;
  409. case 2:
  410. qsgmiiphy_fix[FM1_DTSEC1] = 1;
  411. qsgmiiphy_fix[FM1_DTSEC2] = 1;
  412. qsgmiiphy_fix[FM1_DTSEC3] = 1;
  413. qsgmiiphy_fix[FM1_DTSEC4] = 1;
  414. slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
  415. slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
  416. slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
  417. slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
  418. break;
  419. case 3:
  420. qsgmiiphy_fix[FM2_DTSEC5] = 1;
  421. qsgmiiphy_fix[FM2_DTSEC6] = 1;
  422. qsgmiiphy_fix[FM2_DTSEC9] = 1;
  423. qsgmiiphy_fix[FM2_DTSEC10] = 1;
  424. slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
  425. slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
  426. slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
  427. slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
  428. break;
  429. case 4:
  430. qsgmiiphy_fix[FM2_DTSEC1] = 1;
  431. qsgmiiphy_fix[FM2_DTSEC2] = 1;
  432. qsgmiiphy_fix[FM2_DTSEC3] = 1;
  433. qsgmiiphy_fix[FM2_DTSEC4] = 1;
  434. slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
  435. slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
  436. slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
  437. slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
  438. break;
  439. default:
  440. break;
  441. }
  442. }
  443. }
  444. int board_eth_init(bd_t *bis)
  445. {
  446. #if defined(CONFIG_FMAN_ENET)
  447. int i, idx, lane, slot, interface;
  448. struct memac_mdio_info dtsec_mdio_info;
  449. struct memac_mdio_info tgec_mdio_info;
  450. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  451. u32 srds_prtcl_s1, srds_prtcl_s2;
  452. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  453. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  454. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  455. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  456. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  457. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  458. /* Initialize the mdio_mux array so we can recognize empty elements */
  459. for (i = 0; i < NUM_FM_PORTS; i++)
  460. mdio_mux[i] = EMI_NONE;
  461. dtsec_mdio_info.regs =
  462. (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
  463. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  464. /* Register the 1G MDIO bus */
  465. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  466. tgec_mdio_info.regs =
  467. (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
  468. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  469. /* Register the 10G MDIO bus */
  470. fm_memac_mdio_init(bis, &tgec_mdio_info);
  471. /* Register the muxing front-ends to the MDIO buses */
  472. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
  473. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  474. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  475. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  476. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  477. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  478. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  479. t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  480. initialize_qsgmiiphy_fix();
  481. switch (srds_prtcl_s1) {
  482. case 1:
  483. case 2:
  484. case 4:
  485. /* XAUI/HiGig in Slot1 and Slot2 */
  486. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  487. fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
  488. break;
  489. case 27:
  490. case 28:
  491. case 35:
  492. case 36:
  493. /* SGMII in Slot1 and Slot2 */
  494. fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
  495. fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
  496. fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
  497. fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
  498. fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
  499. fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
  500. if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
  501. fm_info_set_phy_address(FM1_DTSEC9,
  502. slot_qsgmii_phyaddr[1][3]);
  503. fm_info_set_phy_address(FM1_DTSEC10,
  504. slot_qsgmii_phyaddr[1][2]);
  505. }
  506. break;
  507. case 37:
  508. case 38:
  509. fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
  510. fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
  511. fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
  512. fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
  513. fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
  514. fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
  515. if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
  516. fm_info_set_phy_address(FM1_DTSEC9,
  517. slot_qsgmii_phyaddr[1][2]);
  518. fm_info_set_phy_address(FM1_DTSEC10,
  519. slot_qsgmii_phyaddr[1][3]);
  520. }
  521. break;
  522. case 39:
  523. case 40:
  524. case 45:
  525. case 46:
  526. case 47:
  527. case 48:
  528. fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
  529. fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
  530. if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
  531. fm_info_set_phy_address(FM1_DTSEC10,
  532. slot_qsgmii_phyaddr[1][2]);
  533. fm_info_set_phy_address(FM1_DTSEC9,
  534. slot_qsgmii_phyaddr[1][3]);
  535. }
  536. fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
  537. fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
  538. fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
  539. fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
  540. break;
  541. default:
  542. puts("Invalid SerDes1 protocol for T4240QDS\n");
  543. break;
  544. }
  545. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  546. idx = i - FM1_DTSEC1;
  547. interface = fm_info_get_enet_if(i);
  548. switch (interface) {
  549. case PHY_INTERFACE_MODE_SGMII:
  550. case PHY_INTERFACE_MODE_QSGMII:
  551. if (interface == PHY_INTERFACE_MODE_QSGMII) {
  552. if (idx <= 3)
  553. lane = serdes_get_first_lane(FSL_SRDS_1,
  554. QSGMII_FM1_A);
  555. else
  556. lane = serdes_get_first_lane(FSL_SRDS_1,
  557. QSGMII_FM1_B);
  558. if (lane < 0)
  559. break;
  560. slot = lane_to_slot_fsm1[lane];
  561. debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
  562. idx + 1, slot);
  563. } else {
  564. lane = serdes_get_first_lane(FSL_SRDS_1,
  565. SGMII_FM1_DTSEC1 + idx);
  566. if (lane < 0)
  567. break;
  568. slot = lane_to_slot_fsm1[lane];
  569. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  570. idx + 1, slot);
  571. }
  572. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  573. fm_disable_port(i);
  574. switch (slot) {
  575. case 1:
  576. mdio_mux[i] = EMI1_SLOT1;
  577. fm_info_set_mdio(i,
  578. mii_dev_for_muxval(mdio_mux[i]));
  579. break;
  580. case 2:
  581. mdio_mux[i] = EMI1_SLOT2;
  582. fm_info_set_mdio(i,
  583. mii_dev_for_muxval(mdio_mux[i]));
  584. break;
  585. };
  586. break;
  587. case PHY_INTERFACE_MODE_RGMII:
  588. /* FM1 DTSEC5 routes to RGMII with EC2 */
  589. debug("FM1@DTSEC%u is RGMII at address %u\n",
  590. idx + 1, 2);
  591. if (i == FM1_DTSEC5)
  592. fm_info_set_phy_address(i, 2);
  593. mdio_mux[i] = EMI1_RGMII;
  594. fm_info_set_mdio(i,
  595. mii_dev_for_muxval(mdio_mux[i]));
  596. break;
  597. default:
  598. break;
  599. }
  600. }
  601. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  602. idx = i - FM1_10GEC1;
  603. switch (fm_info_get_enet_if(i)) {
  604. case PHY_INTERFACE_MODE_XGMII:
  605. if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
  606. /* A fake PHY address to make U-boot happy */
  607. fm_info_set_phy_address(i, i);
  608. } else {
  609. lane = serdes_get_first_lane(FSL_SRDS_1,
  610. XAUI_FM1_MAC9 + idx);
  611. if (lane < 0)
  612. break;
  613. slot = lane_to_slot_fsm1[lane];
  614. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  615. fm_disable_port(i);
  616. }
  617. mdio_mux[i] = EMI2;
  618. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  619. break;
  620. default:
  621. break;
  622. }
  623. }
  624. #if (CONFIG_SYS_NUM_FMAN == 2)
  625. switch (srds_prtcl_s2) {
  626. case 1:
  627. case 2:
  628. case 4:
  629. /* XAUI/HiGig in Slot3 and Slot4 */
  630. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  631. fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
  632. break;
  633. case 6:
  634. case 7:
  635. case 12:
  636. case 13:
  637. case 14:
  638. case 15:
  639. case 16:
  640. case 21:
  641. case 22:
  642. case 23:
  643. case 24:
  644. case 25:
  645. case 26:
  646. /* XAUI/HiGig in Slot3, SGMII in Slot4 */
  647. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  648. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  649. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  650. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  651. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  652. break;
  653. case 27:
  654. case 28:
  655. case 35:
  656. case 36:
  657. /* SGMII in Slot3 and Slot4 */
  658. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  659. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  660. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  661. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  662. fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
  663. fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
  664. fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
  665. fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
  666. break;
  667. case 37:
  668. case 38:
  669. /* QSGMII in Slot3 and Slot4 */
  670. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  671. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  672. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  673. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  674. fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
  675. fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
  676. fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
  677. fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
  678. break;
  679. case 39:
  680. case 40:
  681. case 45:
  682. case 46:
  683. case 47:
  684. case 48:
  685. /* SGMII in Slot3 */
  686. fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
  687. fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
  688. fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
  689. fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
  690. /* QSGMII in Slot4 */
  691. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  692. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  693. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  694. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  695. break;
  696. case 49:
  697. case 50:
  698. case 51:
  699. case 52:
  700. case 53:
  701. case 54:
  702. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  703. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  704. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  705. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  706. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  707. break;
  708. case 55:
  709. case 57:
  710. /* XFI in Slot3, SGMII in Slot4 */
  711. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  712. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  713. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  714. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  715. break;
  716. default:
  717. puts("Invalid SerDes2 protocol for T4240QDS\n");
  718. break;
  719. }
  720. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  721. idx = i - FM2_DTSEC1;
  722. interface = fm_info_get_enet_if(i);
  723. switch (interface) {
  724. case PHY_INTERFACE_MODE_SGMII:
  725. case PHY_INTERFACE_MODE_QSGMII:
  726. if (interface == PHY_INTERFACE_MODE_QSGMII) {
  727. if (idx <= 3)
  728. lane = serdes_get_first_lane(FSL_SRDS_2,
  729. QSGMII_FM2_A);
  730. else
  731. lane = serdes_get_first_lane(FSL_SRDS_2,
  732. QSGMII_FM2_B);
  733. if (lane < 0)
  734. break;
  735. slot = lane_to_slot_fsm2[lane];
  736. debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
  737. idx + 1, slot);
  738. } else {
  739. lane = serdes_get_first_lane(FSL_SRDS_2,
  740. SGMII_FM2_DTSEC1 + idx);
  741. if (lane < 0)
  742. break;
  743. slot = lane_to_slot_fsm2[lane];
  744. debug("FM2@DTSEC%u expects SGMII in slot %u\n",
  745. idx + 1, slot);
  746. }
  747. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  748. fm_disable_port(i);
  749. switch (slot) {
  750. case 3:
  751. mdio_mux[i] = EMI1_SLOT3;
  752. fm_info_set_mdio(i,
  753. mii_dev_for_muxval(mdio_mux[i]));
  754. break;
  755. case 4:
  756. mdio_mux[i] = EMI1_SLOT4;
  757. fm_info_set_mdio(i,
  758. mii_dev_for_muxval(mdio_mux[i]));
  759. break;
  760. };
  761. break;
  762. case PHY_INTERFACE_MODE_RGMII:
  763. /*
  764. * If DTSEC5 is RGMII, then it's routed via via EC1 to
  765. * the first on-board RGMII port. If DTSEC6 is RGMII,
  766. * then it's routed via via EC2 to the second on-board
  767. * RGMII port.
  768. */
  769. debug("FM2@DTSEC%u is RGMII at address %u\n",
  770. idx + 1, i == FM2_DTSEC5 ? 1 : 2);
  771. fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
  772. mdio_mux[i] = EMI1_RGMII;
  773. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  774. break;
  775. default:
  776. break;
  777. }
  778. }
  779. for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
  780. idx = i - FM2_10GEC1;
  781. switch (fm_info_get_enet_if(i)) {
  782. case PHY_INTERFACE_MODE_XGMII:
  783. if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
  784. /* A fake PHY address to make U-boot happy */
  785. fm_info_set_phy_address(i, i);
  786. } else {
  787. lane = serdes_get_first_lane(FSL_SRDS_2,
  788. XAUI_FM2_MAC9 + idx);
  789. if (lane < 0)
  790. break;
  791. slot = lane_to_slot_fsm2[lane];
  792. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  793. fm_disable_port(i);
  794. }
  795. mdio_mux[i] = EMI2;
  796. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  797. break;
  798. default:
  799. break;
  800. }
  801. }
  802. #endif /* CONFIG_SYS_NUM_FMAN */
  803. cpu_eth_init(bis);
  804. #endif /* CONFIG_FMAN_ENET */
  805. return pci_eth_init(bis);
  806. }