eth_t208xqds.c 22 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <netdev.h>
  11. #include <asm/mmu.h>
  12. #include <asm/processor.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_law.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <asm/fsl_portals.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <malloc.h>
  19. #include <fm_eth.h>
  20. #include <fsl_mdio.h>
  21. #include <miiphy.h>
  22. #include <phy.h>
  23. #include <fsl_dtsec.h>
  24. #include <asm/fsl_serdes.h>
  25. #include <hwconfig.h>
  26. #include "../common/qixis.h"
  27. #include "../common/fman.h"
  28. #include "t208xqds_qixis.h"
  29. #define EMI_NONE 0xFFFFFFFF
  30. #define EMI1_RGMII1 0
  31. #define EMI1_RGMII2 1
  32. #define EMI1_SLOT1 2
  33. #if defined(CONFIG_T2080QDS)
  34. #define EMI1_SLOT2 6
  35. #define EMI1_SLOT3 3
  36. #define EMI1_SLOT4 4
  37. #define EMI1_SLOT5 5
  38. #define EMI2 7
  39. #elif defined(CONFIG_T2081QDS)
  40. #define EMI1_SLOT2 3
  41. #define EMI1_SLOT3 4
  42. #define EMI1_SLOT5 5
  43. #define EMI1_SLOT6 6
  44. #define EMI1_SLOT7 7
  45. #define EMI2 8
  46. #endif
  47. #define PCCR1_SGMIIA_KX_MASK 0x00008000
  48. #define PCCR1_SGMIIB_KX_MASK 0x00004000
  49. #define PCCR1_SGMIIC_KX_MASK 0x00002000
  50. #define PCCR1_SGMIID_KX_MASK 0x00001000
  51. #define PCCR1_SGMIIE_KX_MASK 0x00000800
  52. #define PCCR1_SGMIIF_KX_MASK 0x00000400
  53. #define PCCR1_SGMIIG_KX_MASK 0x00000200
  54. #define PCCR1_SGMIIH_KX_MASK 0x00000100
  55. static int mdio_mux[NUM_FM_PORTS];
  56. static const char * const mdio_names[] = {
  57. #if defined(CONFIG_T2080QDS)
  58. "T2080QDS_MDIO_RGMII1",
  59. "T2080QDS_MDIO_RGMII2",
  60. "T2080QDS_MDIO_SLOT1",
  61. "T2080QDS_MDIO_SLOT3",
  62. "T2080QDS_MDIO_SLOT4",
  63. "T2080QDS_MDIO_SLOT5",
  64. "T2080QDS_MDIO_SLOT2",
  65. "T2080QDS_MDIO_10GC",
  66. #elif defined(CONFIG_T2081QDS)
  67. "T2081QDS_MDIO_RGMII1",
  68. "T2081QDS_MDIO_RGMII2",
  69. "T2081QDS_MDIO_SLOT1",
  70. "T2081QDS_MDIO_SLOT2",
  71. "T2081QDS_MDIO_SLOT3",
  72. "T2081QDS_MDIO_SLOT5",
  73. "T2081QDS_MDIO_SLOT6",
  74. "T2081QDS_MDIO_SLOT7",
  75. "T2081QDS_MDIO_10GC",
  76. #endif
  77. };
  78. /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  79. #if defined(CONFIG_T2080QDS)
  80. static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  81. #elif defined(CONFIG_T2081QDS)
  82. static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  83. #endif
  84. static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  85. {
  86. return mdio_names[muxval];
  87. }
  88. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  89. {
  90. struct mii_dev *bus;
  91. const char *name = t208xqds_mdio_name_for_muxval(muxval);
  92. if (!name) {
  93. printf("No bus for muxval %x\n", muxval);
  94. return NULL;
  95. }
  96. bus = miiphy_get_dev_by_name(name);
  97. if (!bus) {
  98. printf("No bus by name %s\n", name);
  99. return NULL;
  100. }
  101. return bus;
  102. }
  103. struct t208xqds_mdio {
  104. u8 muxval;
  105. struct mii_dev *realbus;
  106. };
  107. static void t208xqds_mux_mdio(u8 muxval)
  108. {
  109. u8 brdcfg4;
  110. if (muxval < 8) {
  111. brdcfg4 = QIXIS_READ(brdcfg[4]);
  112. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  113. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  114. QIXIS_WRITE(brdcfg[4], brdcfg4);
  115. }
  116. }
  117. static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  118. int regnum)
  119. {
  120. struct t208xqds_mdio *priv = bus->priv;
  121. t208xqds_mux_mdio(priv->muxval);
  122. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  123. }
  124. static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  125. int regnum, u16 value)
  126. {
  127. struct t208xqds_mdio *priv = bus->priv;
  128. t208xqds_mux_mdio(priv->muxval);
  129. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  130. }
  131. static int t208xqds_mdio_reset(struct mii_dev *bus)
  132. {
  133. struct t208xqds_mdio *priv = bus->priv;
  134. return priv->realbus->reset(priv->realbus);
  135. }
  136. static int t208xqds_mdio_init(char *realbusname, u8 muxval)
  137. {
  138. struct t208xqds_mdio *pmdio;
  139. struct mii_dev *bus = mdio_alloc();
  140. if (!bus) {
  141. printf("Failed to allocate t208xqds MDIO bus\n");
  142. return -1;
  143. }
  144. pmdio = malloc(sizeof(*pmdio));
  145. if (!pmdio) {
  146. printf("Failed to allocate t208xqds private data\n");
  147. free(bus);
  148. return -1;
  149. }
  150. bus->read = t208xqds_mdio_read;
  151. bus->write = t208xqds_mdio_write;
  152. bus->reset = t208xqds_mdio_reset;
  153. strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
  154. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  155. if (!pmdio->realbus) {
  156. printf("No bus with name %s\n", realbusname);
  157. free(bus);
  158. free(pmdio);
  159. return -1;
  160. }
  161. pmdio->muxval = muxval;
  162. bus->priv = pmdio;
  163. return mdio_register(bus);
  164. }
  165. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  166. enum fm_port port, int offset)
  167. {
  168. int phy;
  169. char alias[20];
  170. char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
  171. char buf[32] = "serdes-1,";
  172. struct fixed_link f_link;
  173. int media_type = 0;
  174. int off;
  175. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  176. #ifdef CONFIG_T2080QDS
  177. serdes_corenet_t *srds_regs =
  178. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  179. u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
  180. #endif
  181. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  182. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  183. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  184. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  185. phy = fm_info_get_phy_address(port);
  186. switch (port) {
  187. #if defined(CONFIG_T2080QDS)
  188. case FM1_DTSEC1:
  189. if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
  190. media_type = 1;
  191. fdt_set_phy_handle(fdt, compat, addr,
  192. "phy_1gkx1");
  193. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
  194. sprintf(buf, "%s%s%s", buf, "lane-c,",
  195. (char *)lane_mode[0]);
  196. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  197. PCCR1_SGMIIH_KX_MASK);
  198. break;
  199. }
  200. case FM1_DTSEC2:
  201. if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
  202. media_type = 1;
  203. fdt_set_phy_handle(fdt, compat, addr,
  204. "phy_1gkx2");
  205. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
  206. sprintf(buf, "%s%s%s", buf, "lane-d,",
  207. (char *)lane_mode[0]);
  208. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  209. PCCR1_SGMIIG_KX_MASK);
  210. break;
  211. }
  212. case FM1_DTSEC9:
  213. if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
  214. media_type = 1;
  215. fdt_set_phy_handle(fdt, compat, addr,
  216. "phy_1gkx9");
  217. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
  218. sprintf(buf, "%s%s%s", buf, "lane-a,",
  219. (char *)lane_mode[0]);
  220. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  221. PCCR1_SGMIIE_KX_MASK);
  222. break;
  223. }
  224. case FM1_DTSEC10:
  225. if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
  226. media_type = 1;
  227. fdt_set_phy_handle(fdt, compat, addr,
  228. "phy_1gkx10");
  229. fdt_status_okay_by_alias(fdt,
  230. "1gkx_pcs_mdio10");
  231. sprintf(buf, "%s%s%s", buf, "lane-b,",
  232. (char *)lane_mode[0]);
  233. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  234. PCCR1_SGMIIF_KX_MASK);
  235. break;
  236. }
  237. if (mdio_mux[port] == EMI1_SLOT2) {
  238. sprintf(alias, "phy_sgmii_s2_%x", phy);
  239. fdt_set_phy_handle(fdt, compat, addr, alias);
  240. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  241. } else if (mdio_mux[port] == EMI1_SLOT3) {
  242. sprintf(alias, "phy_sgmii_s3_%x", phy);
  243. fdt_set_phy_handle(fdt, compat, addr, alias);
  244. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  245. }
  246. break;
  247. case FM1_DTSEC5:
  248. if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
  249. media_type = 1;
  250. fdt_set_phy_handle(fdt, compat, addr,
  251. "phy_1gkx5");
  252. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
  253. sprintf(buf, "%s%s%s", buf, "lane-g,",
  254. (char *)lane_mode[0]);
  255. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  256. PCCR1_SGMIIC_KX_MASK);
  257. break;
  258. }
  259. case FM1_DTSEC6:
  260. if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
  261. media_type = 1;
  262. fdt_set_phy_handle(fdt, compat, addr,
  263. "phy_1gkx6");
  264. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
  265. sprintf(buf, "%s%s%s", buf, "lane-h,",
  266. (char *)lane_mode[0]);
  267. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  268. PCCR1_SGMIID_KX_MASK);
  269. break;
  270. }
  271. if (mdio_mux[port] == EMI1_SLOT1) {
  272. sprintf(alias, "phy_sgmii_s1_%x", phy);
  273. fdt_set_phy_handle(fdt, compat, addr, alias);
  274. fdt_status_okay_by_alias(fdt, "emi1_slot1");
  275. } else if (mdio_mux[port] == EMI1_SLOT2) {
  276. sprintf(alias, "phy_sgmii_s2_%x", phy);
  277. fdt_set_phy_handle(fdt, compat, addr, alias);
  278. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  279. }
  280. break;
  281. #elif defined(CONFIG_T2081QDS)
  282. case FM1_DTSEC1:
  283. case FM1_DTSEC2:
  284. case FM1_DTSEC5:
  285. case FM1_DTSEC6:
  286. case FM1_DTSEC9:
  287. case FM1_DTSEC10:
  288. if (mdio_mux[port] == EMI1_SLOT2) {
  289. sprintf(alias, "phy_sgmii_s2_%x", phy);
  290. fdt_set_phy_handle(fdt, compat, addr, alias);
  291. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  292. } else if (mdio_mux[port] == EMI1_SLOT3) {
  293. sprintf(alias, "phy_sgmii_s3_%x", phy);
  294. fdt_set_phy_handle(fdt, compat, addr, alias);
  295. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  296. } else if (mdio_mux[port] == EMI1_SLOT5) {
  297. sprintf(alias, "phy_sgmii_s5_%x", phy);
  298. fdt_set_phy_handle(fdt, compat, addr, alias);
  299. fdt_status_okay_by_alias(fdt, "emi1_slot5");
  300. } else if (mdio_mux[port] == EMI1_SLOT6) {
  301. sprintf(alias, "phy_sgmii_s6_%x", phy);
  302. fdt_set_phy_handle(fdt, compat, addr, alias);
  303. fdt_status_okay_by_alias(fdt, "emi1_slot6");
  304. } else if (mdio_mux[port] == EMI1_SLOT7) {
  305. sprintf(alias, "phy_sgmii_s7_%x", phy);
  306. fdt_set_phy_handle(fdt, compat, addr, alias);
  307. fdt_status_okay_by_alias(fdt, "emi1_slot7");
  308. }
  309. break;
  310. #endif
  311. default:
  312. break;
  313. }
  314. if (media_type) {
  315. /* set property for 1000BASE-KX in dtb */
  316. off = fdt_node_offset_by_compat_reg(fdt,
  317. "fsl,fman-memac-mdio", addr + 0x1000);
  318. fdt_setprop_string(fdt, off, "lane-instance", buf);
  319. }
  320. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  321. switch (srds_s1) {
  322. case 0x66: /* XFI interface */
  323. case 0x6b:
  324. case 0x6c:
  325. case 0x6d:
  326. case 0x71:
  327. /*
  328. * if the 10G is XFI, check hwconfig to see what is the
  329. * media type, there are two types, fiber or copper,
  330. * fix the dtb accordingly.
  331. */
  332. switch (port) {
  333. case FM1_10GEC1:
  334. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
  335. /* it's MAC9 */
  336. media_type = 1;
  337. fdt_set_phy_handle(fdt, compat, addr,
  338. "phy_xfi9");
  339. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
  340. sprintf(buf, "%s%s%s", buf, "lane-a,",
  341. (char *)lane_mode[1]);
  342. }
  343. break;
  344. case FM1_10GEC2:
  345. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
  346. /* it's MAC10 */
  347. media_type = 1;
  348. fdt_set_phy_handle(fdt, compat, addr,
  349. "phy_xfi10");
  350. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
  351. sprintf(buf, "%s%s%s", buf, "lane-b,",
  352. (char *)lane_mode[1]);
  353. }
  354. break;
  355. case FM1_10GEC3:
  356. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
  357. /* it's MAC1 */
  358. media_type = 1;
  359. fdt_set_phy_handle(fdt, compat, addr,
  360. "phy_xfi1");
  361. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
  362. sprintf(buf, "%s%s%s", buf, "lane-c,",
  363. (char *)lane_mode[1]);
  364. }
  365. break;
  366. case FM1_10GEC4:
  367. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
  368. /* it's MAC2 */
  369. media_type = 1;
  370. fdt_set_phy_handle(fdt, compat, addr,
  371. "phy_xfi2");
  372. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
  373. sprintf(buf, "%s%s%s", buf, "lane-d,",
  374. (char *)lane_mode[1]);
  375. }
  376. break;
  377. default:
  378. return;
  379. }
  380. if (!media_type) {
  381. /* fixed-link is used for XFI fiber cable */
  382. f_link.phy_id = port;
  383. f_link.duplex = 1;
  384. f_link.link_speed = 10000;
  385. f_link.pause = 0;
  386. f_link.asym_pause = 0;
  387. fdt_delprop(fdt, offset, "phy-handle");
  388. fdt_setprop(fdt, offset, "fixed-link", &f_link,
  389. sizeof(f_link));
  390. } else {
  391. /* set property for copper cable */
  392. off = fdt_node_offset_by_compat_reg(fdt,
  393. "fsl,fman-memac-mdio", addr + 0x1000);
  394. fdt_setprop_string(fdt, off,
  395. "lane-instance", buf);
  396. }
  397. break;
  398. default:
  399. break;
  400. }
  401. }
  402. }
  403. void fdt_fixup_board_enet(void *fdt)
  404. {
  405. return;
  406. }
  407. /*
  408. * This function reads RCW to check if Serdes1{A:H} is configured
  409. * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
  410. */
  411. static void initialize_lane_to_slot(void)
  412. {
  413. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  414. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  415. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  416. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  417. switch (srds_s1) {
  418. #if defined(CONFIG_T2080QDS)
  419. case 0x51:
  420. case 0x5f:
  421. case 0x65:
  422. case 0x6b:
  423. case 0x71:
  424. lane_to_slot[5] = 2;
  425. lane_to_slot[6] = 2;
  426. lane_to_slot[7] = 2;
  427. break;
  428. case 0xa6:
  429. case 0x8e:
  430. case 0x8f:
  431. case 0x82:
  432. case 0x83:
  433. case 0xd3:
  434. case 0xd9:
  435. case 0xcb:
  436. lane_to_slot[6] = 2;
  437. lane_to_slot[7] = 2;
  438. break;
  439. case 0xda:
  440. lane_to_slot[4] = 3;
  441. lane_to_slot[5] = 3;
  442. lane_to_slot[6] = 3;
  443. lane_to_slot[7] = 3;
  444. break;
  445. #elif defined(CONFIG_T2081QDS)
  446. case 0x6b:
  447. lane_to_slot[4] = 1;
  448. lane_to_slot[5] = 3;
  449. lane_to_slot[6] = 3;
  450. lane_to_slot[7] = 3;
  451. break;
  452. case 0xca:
  453. case 0xcb:
  454. lane_to_slot[1] = 7;
  455. lane_to_slot[2] = 6;
  456. lane_to_slot[3] = 5;
  457. lane_to_slot[5] = 3;
  458. lane_to_slot[6] = 3;
  459. lane_to_slot[7] = 3;
  460. break;
  461. case 0xf2:
  462. lane_to_slot[1] = 7;
  463. lane_to_slot[2] = 7;
  464. lane_to_slot[3] = 7;
  465. lane_to_slot[5] = 4;
  466. lane_to_slot[6] = 3;
  467. lane_to_slot[7] = 7;
  468. break;
  469. #endif
  470. default:
  471. break;
  472. }
  473. }
  474. int board_eth_init(bd_t *bis)
  475. {
  476. #if defined(CONFIG_FMAN_ENET)
  477. int i, idx, lane, slot, interface;
  478. struct memac_mdio_info dtsec_mdio_info;
  479. struct memac_mdio_info tgec_mdio_info;
  480. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  481. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  482. u32 srds_s1;
  483. srds_s1 = in_be32(&gur->rcwsr[4]) &
  484. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  485. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  486. initialize_lane_to_slot();
  487. /* Initialize the mdio_mux array so we can recognize empty elements */
  488. for (i = 0; i < NUM_FM_PORTS; i++)
  489. mdio_mux[i] = EMI_NONE;
  490. dtsec_mdio_info.regs =
  491. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  492. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  493. /* Register the 1G MDIO bus */
  494. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  495. tgec_mdio_info.regs =
  496. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  497. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  498. /* Register the 10G MDIO bus */
  499. fm_memac_mdio_init(bis, &tgec_mdio_info);
  500. /* Register the muxing front-ends to the MDIO buses */
  501. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  502. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  503. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  504. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  505. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  506. #if defined(CONFIG_T2080QDS)
  507. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  508. #endif
  509. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  510. #if defined(CONFIG_T2081QDS)
  511. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
  512. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  513. #endif
  514. t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  515. /* Set the two on-board RGMII PHY address */
  516. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  517. if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  518. FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
  519. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  520. else
  521. fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
  522. switch (srds_s1) {
  523. case 0x1b:
  524. case 0x1c:
  525. case 0x95:
  526. case 0xa2:
  527. case 0x94:
  528. /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
  529. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  530. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  531. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  532. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  533. /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
  534. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  535. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  536. break;
  537. case 0x50:
  538. case 0x51:
  539. case 0x5e:
  540. case 0x5f:
  541. case 0x64:
  542. case 0x65:
  543. /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
  544. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  545. /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  546. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  547. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  548. break;
  549. case 0x66:
  550. case 0x67:
  551. /*
  552. * XFI does not need a PHY to work, but to avoid U-boot use
  553. * default PHY address which is zero to a MAC when it found
  554. * a MAC has no PHY address, we give a PHY address to XFI
  555. * MAC, and should not use a real XAUI PHY address, since
  556. * MDIO can access it successfully, and then MDIO thinks
  557. * the XAUI card is used for the XFI MAC, which will cause
  558. * error.
  559. */
  560. fm_info_set_phy_address(FM1_10GEC1, 4);
  561. fm_info_set_phy_address(FM1_10GEC2, 5);
  562. fm_info_set_phy_address(FM1_10GEC3, 6);
  563. fm_info_set_phy_address(FM1_10GEC4, 7);
  564. break;
  565. case 0x6a:
  566. case 0x6b:
  567. fm_info_set_phy_address(FM1_10GEC1, 4);
  568. fm_info_set_phy_address(FM1_10GEC2, 5);
  569. fm_info_set_phy_address(FM1_10GEC3, 6);
  570. fm_info_set_phy_address(FM1_10GEC4, 7);
  571. /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  572. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  573. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  574. break;
  575. case 0x6c:
  576. case 0x6d:
  577. fm_info_set_phy_address(FM1_10GEC1, 4);
  578. fm_info_set_phy_address(FM1_10GEC2, 5);
  579. /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
  580. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  581. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  582. break;
  583. case 0x70:
  584. case 0x71:
  585. /* SGMII in Slot3 */
  586. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  587. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  588. /* SGMII in Slot2 */
  589. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  590. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  591. break;
  592. case 0xa6:
  593. case 0x8e:
  594. case 0x8f:
  595. case 0x82:
  596. case 0x83:
  597. /* SGMII in Slot3 */
  598. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  599. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  600. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  601. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  602. /* SGMII in Slot2 */
  603. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  604. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  605. break;
  606. case 0xa4:
  607. case 0x96:
  608. case 0x8a:
  609. /* SGMII in Slot3 */
  610. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  611. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  612. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  613. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  614. break;
  615. #if defined(CONFIG_T2080QDS)
  616. case 0xd9:
  617. case 0xd3:
  618. case 0xcb:
  619. /* SGMII in Slot3 */
  620. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  621. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  622. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  623. /* SGMII in Slot2 */
  624. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  625. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  626. break;
  627. #elif defined(CONFIG_T2081QDS)
  628. case 0xca:
  629. case 0xcb:
  630. /* SGMII in Slot3 */
  631. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  632. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  633. /* SGMII in Slot5 */
  634. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  635. /* SGMII in Slot6 */
  636. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  637. /* SGMII in Slot7 */
  638. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  639. break;
  640. #endif
  641. case 0xf2:
  642. /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
  643. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  644. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  645. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  646. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  647. break;
  648. default:
  649. break;
  650. }
  651. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  652. idx = i - FM1_DTSEC1;
  653. interface = fm_info_get_enet_if(i);
  654. switch (interface) {
  655. case PHY_INTERFACE_MODE_SGMII:
  656. lane = serdes_get_first_lane(FSL_SRDS_1,
  657. SGMII_FM1_DTSEC1 + idx);
  658. if (lane < 0)
  659. break;
  660. slot = lane_to_slot[lane];
  661. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  662. idx + 1, slot);
  663. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  664. fm_disable_port(i);
  665. switch (slot) {
  666. case 1:
  667. mdio_mux[i] = EMI1_SLOT1;
  668. fm_info_set_mdio(i, mii_dev_for_muxval(
  669. mdio_mux[i]));
  670. break;
  671. case 2:
  672. mdio_mux[i] = EMI1_SLOT2;
  673. fm_info_set_mdio(i, mii_dev_for_muxval(
  674. mdio_mux[i]));
  675. break;
  676. case 3:
  677. mdio_mux[i] = EMI1_SLOT3;
  678. fm_info_set_mdio(i, mii_dev_for_muxval(
  679. mdio_mux[i]));
  680. break;
  681. #if defined(CONFIG_T2081QDS)
  682. case 5:
  683. mdio_mux[i] = EMI1_SLOT5;
  684. fm_info_set_mdio(i, mii_dev_for_muxval(
  685. mdio_mux[i]));
  686. break;
  687. case 6:
  688. mdio_mux[i] = EMI1_SLOT6;
  689. fm_info_set_mdio(i, mii_dev_for_muxval(
  690. mdio_mux[i]));
  691. break;
  692. case 7:
  693. mdio_mux[i] = EMI1_SLOT7;
  694. fm_info_set_mdio(i, mii_dev_for_muxval(
  695. mdio_mux[i]));
  696. break;
  697. #endif
  698. }
  699. break;
  700. case PHY_INTERFACE_MODE_RGMII:
  701. if (i == FM1_DTSEC3)
  702. mdio_mux[i] = EMI1_RGMII1;
  703. else if (i == FM1_DTSEC4 || FM1_DTSEC10)
  704. mdio_mux[i] = EMI1_RGMII2;
  705. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  706. break;
  707. default:
  708. break;
  709. }
  710. }
  711. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  712. idx = i - FM1_10GEC1;
  713. switch (fm_info_get_enet_if(i)) {
  714. case PHY_INTERFACE_MODE_XGMII:
  715. if (srds_s1 == 0x51) {
  716. lane = serdes_get_first_lane(FSL_SRDS_1,
  717. XAUI_FM1_MAC9 + idx);
  718. } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
  719. lane = serdes_get_first_lane(FSL_SRDS_1,
  720. HIGIG_FM1_MAC9 + idx);
  721. } else {
  722. if (i == FM1_10GEC1 || i == FM1_10GEC2)
  723. lane = serdes_get_first_lane(FSL_SRDS_1,
  724. XFI_FM1_MAC9 + idx);
  725. else
  726. lane = serdes_get_first_lane(FSL_SRDS_1,
  727. XFI_FM1_MAC1 + idx);
  728. }
  729. if (lane < 0)
  730. break;
  731. mdio_mux[i] = EMI2;
  732. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  733. if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
  734. (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
  735. (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
  736. (srds_s1 == 0x71)) {
  737. /* As XFI is in cage intead of a slot, so
  738. * ensure doesn't disable the corresponding port
  739. */
  740. break;
  741. }
  742. slot = lane_to_slot[lane];
  743. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  744. fm_disable_port(i);
  745. break;
  746. default:
  747. break;
  748. }
  749. }
  750. cpu_eth_init(bis);
  751. #endif /* CONFIG_FMAN_ENET */
  752. return pci_eth_init(bis);
  753. }