eth.c 14 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * The RGMII PHYs are provided by the two on-board PHY connected to
  8. * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
  9. * PHY or by the standard four-port SGMII riser card (VSC).
  10. */
  11. #include <common.h>
  12. #include <netdev.h>
  13. #include <asm/fsl_serdes.h>
  14. #include <asm/immap_85xx.h>
  15. #include <fm_eth.h>
  16. #include <fsl_mdio.h>
  17. #include <malloc.h>
  18. #include <fsl_dtsec.h>
  19. #include <vsc9953.h>
  20. #include "../common/fman.h"
  21. #include "../common/qixis.h"
  22. #include "t1040qds_qixis.h"
  23. #ifdef CONFIG_FMAN_ENET
  24. /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
  25. * Bank 1 -> Lanes A, B, C, D
  26. * Bank 2 -> Lanes E, F, G, H
  27. */
  28. /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
  29. * means that the mapping must be determined dynamically, or that the lane
  30. * maps to something other than a board slot.
  31. */
  32. static u8 lane_to_slot[] = {
  33. 0, 0, 0, 0, 0, 0, 0, 0
  34. };
  35. /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  36. * housed.
  37. */
  38. static int riser_phy_addr[] = {
  39. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
  40. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
  41. CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
  42. CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
  43. };
  44. /* Slot2 does not have EMI connections */
  45. #define EMI_NONE 0xFFFFFFFF
  46. #define EMI1_RGMII0 0
  47. #define EMI1_RGMII1 1
  48. #define EMI1_SLOT1 2
  49. #define EMI1_SLOT3 3
  50. #define EMI1_SLOT4 4
  51. #define EMI1_SLOT5 5
  52. #define EMI1_SLOT6 6
  53. #define EMI1_SLOT7 7
  54. #define EMI2 8
  55. static int mdio_mux[NUM_FM_PORTS];
  56. static const char * const mdio_names[] = {
  57. "T1040_QDS_MDIO0",
  58. "T1040_QDS_MDIO1",
  59. "T1040_QDS_MDIO2",
  60. "T1040_QDS_MDIO3",
  61. "T1040_QDS_MDIO4",
  62. "T1040_QDS_MDIO5",
  63. "T1040_QDS_MDIO6",
  64. "T1040_QDS_MDIO7",
  65. };
  66. struct t1040_qds_mdio {
  67. u8 muxval;
  68. struct mii_dev *realbus;
  69. };
  70. static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
  71. {
  72. return mdio_names[muxval];
  73. }
  74. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  75. {
  76. struct mii_dev *bus;
  77. const char *name = t1040_qds_mdio_name_for_muxval(muxval);
  78. if (!name) {
  79. printf("No bus for muxval %x\n", muxval);
  80. return NULL;
  81. }
  82. bus = miiphy_get_dev_by_name(name);
  83. if (!bus) {
  84. printf("No bus by name %s\n", name);
  85. return NULL;
  86. }
  87. return bus;
  88. }
  89. static void t1040_qds_mux_mdio(u8 muxval)
  90. {
  91. u8 brdcfg4;
  92. if (muxval <= 7) {
  93. brdcfg4 = QIXIS_READ(brdcfg[4]);
  94. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  95. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  96. QIXIS_WRITE(brdcfg[4], brdcfg4);
  97. }
  98. }
  99. static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  100. int regnum)
  101. {
  102. struct t1040_qds_mdio *priv = bus->priv;
  103. t1040_qds_mux_mdio(priv->muxval);
  104. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  105. }
  106. static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  107. int regnum, u16 value)
  108. {
  109. struct t1040_qds_mdio *priv = bus->priv;
  110. t1040_qds_mux_mdio(priv->muxval);
  111. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  112. }
  113. static int t1040_qds_mdio_reset(struct mii_dev *bus)
  114. {
  115. struct t1040_qds_mdio *priv = bus->priv;
  116. return priv->realbus->reset(priv->realbus);
  117. }
  118. static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
  119. {
  120. struct t1040_qds_mdio *pmdio;
  121. struct mii_dev *bus = mdio_alloc();
  122. if (!bus) {
  123. printf("Failed to allocate t1040_qds MDIO bus\n");
  124. return -1;
  125. }
  126. pmdio = malloc(sizeof(*pmdio));
  127. if (!pmdio) {
  128. printf("Failed to allocate t1040_qds private data\n");
  129. free(bus);
  130. return -1;
  131. }
  132. bus->read = t1040_qds_mdio_read;
  133. bus->write = t1040_qds_mdio_write;
  134. bus->reset = t1040_qds_mdio_reset;
  135. strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
  136. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  137. if (!pmdio->realbus) {
  138. printf("No bus with name %s\n", realbusname);
  139. free(bus);
  140. free(pmdio);
  141. return -1;
  142. }
  143. pmdio->muxval = muxval;
  144. bus->priv = pmdio;
  145. return mdio_register(bus);
  146. }
  147. /*
  148. * Initialize the lane_to_slot[] array.
  149. *
  150. * On the T1040QDS board the mapping is controlled by ?? register.
  151. */
  152. static void initialize_lane_to_slot(void)
  153. {
  154. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  155. int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
  156. FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
  157. >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  158. QIXIS_WRITE(cms[0], 0x07);
  159. switch (serdes1_prtcl) {
  160. case 0x60:
  161. case 0x66:
  162. case 0x67:
  163. case 0x69:
  164. lane_to_slot[1] = 7;
  165. lane_to_slot[2] = 6;
  166. lane_to_slot[3] = 5;
  167. break;
  168. case 0x86:
  169. lane_to_slot[1] = 7;
  170. lane_to_slot[2] = 7;
  171. lane_to_slot[3] = 7;
  172. break;
  173. case 0x87:
  174. lane_to_slot[1] = 7;
  175. lane_to_slot[2] = 7;
  176. lane_to_slot[3] = 7;
  177. lane_to_slot[7] = 7;
  178. break;
  179. case 0x89:
  180. lane_to_slot[1] = 7;
  181. lane_to_slot[2] = 7;
  182. lane_to_slot[3] = 7;
  183. lane_to_slot[6] = 7;
  184. lane_to_slot[7] = 7;
  185. break;
  186. case 0x8d:
  187. lane_to_slot[1] = 7;
  188. lane_to_slot[2] = 7;
  189. lane_to_slot[3] = 7;
  190. lane_to_slot[5] = 3;
  191. lane_to_slot[6] = 3;
  192. lane_to_slot[7] = 3;
  193. break;
  194. case 0x8F:
  195. case 0x85:
  196. lane_to_slot[1] = 7;
  197. lane_to_slot[2] = 6;
  198. lane_to_slot[3] = 5;
  199. lane_to_slot[6] = 3;
  200. lane_to_slot[7] = 3;
  201. break;
  202. case 0xA5:
  203. lane_to_slot[1] = 7;
  204. lane_to_slot[6] = 3;
  205. lane_to_slot[7] = 3;
  206. break;
  207. case 0xA7:
  208. lane_to_slot[1] = 7;
  209. lane_to_slot[2] = 6;
  210. lane_to_slot[3] = 5;
  211. lane_to_slot[7] = 7;
  212. break;
  213. case 0xAA:
  214. lane_to_slot[1] = 7;
  215. lane_to_slot[6] = 7;
  216. lane_to_slot[7] = 7;
  217. break;
  218. case 0x40:
  219. lane_to_slot[2] = 7;
  220. lane_to_slot[3] = 7;
  221. break;
  222. default:
  223. printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
  224. serdes1_prtcl);
  225. break;
  226. }
  227. }
  228. /*
  229. * Given the following ...
  230. *
  231. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  232. * compatible string and 'addr' physical address)
  233. *
  234. * 2) An Fman port
  235. *
  236. * ... update the phy-handle property of the Ethernet node to point to the
  237. * right PHY. This assumes that we already know the PHY for each port.
  238. *
  239. * The offset of the Fman Ethernet node is also passed in for convenience, but
  240. * it is not used, and we recalculate the offset anyway.
  241. *
  242. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  243. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  244. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  245. * and ports are the same thing.
  246. *
  247. */
  248. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  249. enum fm_port port, int offset)
  250. {
  251. phy_interface_t intf = fm_info_get_enet_if(port);
  252. char phy[16];
  253. /* The RGMII PHY is identified by the MAC connected to it */
  254. if (intf == PHY_INTERFACE_MODE_RGMII) {
  255. sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
  256. fdt_set_phy_handle(fdt, compat, addr, phy);
  257. }
  258. /* The SGMII PHY is identified by the MAC connected to it */
  259. if (intf == PHY_INTERFACE_MODE_SGMII) {
  260. int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
  261. + port);
  262. u8 slot;
  263. if (lane < 0)
  264. return;
  265. slot = lane_to_slot[lane];
  266. if (slot) {
  267. /* Slot housing a SGMII riser card */
  268. sprintf(phy, "phy_s%x_%02x", slot,
  269. (fm_info_get_phy_address(port - FM1_DTSEC1)-
  270. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
  271. fdt_set_phy_handle(fdt, compat, addr, phy);
  272. }
  273. }
  274. }
  275. void fdt_fixup_board_enet(void *fdt)
  276. {
  277. int i, lane, idx;
  278. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  279. idx = i - FM1_DTSEC1;
  280. switch (fm_info_get_enet_if(i)) {
  281. case PHY_INTERFACE_MODE_SGMII:
  282. lane = serdes_get_first_lane(FSL_SRDS_1,
  283. SGMII_FM1_DTSEC1 + idx);
  284. if (lane < 0)
  285. break;
  286. switch (mdio_mux[i]) {
  287. case EMI1_SLOT3:
  288. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  289. break;
  290. case EMI1_SLOT5:
  291. fdt_status_okay_by_alias(fdt, "emi1_slot5");
  292. break;
  293. case EMI1_SLOT6:
  294. fdt_status_okay_by_alias(fdt, "emi1_slot6");
  295. break;
  296. case EMI1_SLOT7:
  297. fdt_status_okay_by_alias(fdt, "emi1_slot7");
  298. break;
  299. }
  300. break;
  301. case PHY_INTERFACE_MODE_RGMII:
  302. if (i == FM1_DTSEC4)
  303. fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
  304. if (i == FM1_DTSEC5)
  305. fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
  306. break;
  307. default:
  308. break;
  309. }
  310. }
  311. }
  312. #endif /* #ifdef CONFIG_FMAN_ENET */
  313. static void set_brdcfg9_for_gtx_clk(void)
  314. {
  315. u8 brdcfg9;
  316. brdcfg9 = QIXIS_READ(brdcfg[9]);
  317. /* Initializing EPHY2 clock to RGMII mode */
  318. brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
  319. brdcfg9 |= (BRDCFG9_EPHY2_VAL);
  320. QIXIS_WRITE(brdcfg[9], brdcfg9);
  321. }
  322. void t1040_handle_phy_interface_sgmii(int i)
  323. {
  324. int lane, idx, slot;
  325. idx = i - FM1_DTSEC1;
  326. lane = serdes_get_first_lane(FSL_SRDS_1,
  327. SGMII_FM1_DTSEC1 + idx);
  328. if (lane < 0)
  329. return;
  330. slot = lane_to_slot[lane];
  331. switch (slot) {
  332. case 1:
  333. mdio_mux[i] = EMI1_SLOT1;
  334. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  335. break;
  336. case 3:
  337. if (FM1_DTSEC4 == i)
  338. fm_info_set_phy_address(i, riser_phy_addr[0]);
  339. if (FM1_DTSEC5 == i)
  340. fm_info_set_phy_address(i, riser_phy_addr[1]);
  341. mdio_mux[i] = EMI1_SLOT3;
  342. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  343. break;
  344. case 4:
  345. mdio_mux[i] = EMI1_SLOT4;
  346. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  347. break;
  348. case 5:
  349. /* Slot housing a SGMII riser card? */
  350. fm_info_set_phy_address(i, riser_phy_addr[0]);
  351. mdio_mux[i] = EMI1_SLOT5;
  352. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  353. break;
  354. case 6:
  355. /* Slot housing a SGMII riser card? */
  356. fm_info_set_phy_address(i, riser_phy_addr[0]);
  357. mdio_mux[i] = EMI1_SLOT6;
  358. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  359. break;
  360. case 7:
  361. if (FM1_DTSEC1 == i)
  362. fm_info_set_phy_address(i, riser_phy_addr[0]);
  363. if (FM1_DTSEC2 == i)
  364. fm_info_set_phy_address(i, riser_phy_addr[1]);
  365. if (FM1_DTSEC3 == i)
  366. fm_info_set_phy_address(i, riser_phy_addr[2]);
  367. if (FM1_DTSEC5 == i)
  368. fm_info_set_phy_address(i, riser_phy_addr[3]);
  369. mdio_mux[i] = EMI1_SLOT7;
  370. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  371. break;
  372. default:
  373. break;
  374. }
  375. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  376. }
  377. void t1040_handle_phy_interface_rgmii(int i)
  378. {
  379. fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
  380. CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
  381. CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  382. mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
  383. EMI1_RGMII0;
  384. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  385. }
  386. int board_eth_init(bd_t *bis)
  387. {
  388. #ifdef CONFIG_FMAN_ENET
  389. struct memac_mdio_info memac_mdio_info;
  390. unsigned int i;
  391. #ifdef CONFIG_VSC9953
  392. int lane;
  393. int phy_addr;
  394. phy_interface_t phy_int;
  395. struct mii_dev *bus;
  396. #endif
  397. printf("Initializing Fman\n");
  398. set_brdcfg9_for_gtx_clk();
  399. initialize_lane_to_slot();
  400. /* Initialize the mdio_mux array so we can recognize empty elements */
  401. for (i = 0; i < NUM_FM_PORTS; i++)
  402. mdio_mux[i] = EMI_NONE;
  403. memac_mdio_info.regs =
  404. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  405. memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  406. /* Register the real 1G MDIO bus */
  407. fm_memac_mdio_init(bis, &memac_mdio_info);
  408. /* Register the muxing front-ends to the MDIO buses */
  409. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
  410. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  411. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  412. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  413. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  414. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  415. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
  416. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  417. /*
  418. * Program on board RGMII PHY addresses. If the SGMII Riser
  419. * card used, we'll override the PHY address later. For any DTSEC that
  420. * is RGMII, we'll also override its PHY address later. We assume that
  421. * DTSEC4 and DTSEC5 are used for RGMII.
  422. */
  423. fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  424. fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
  425. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  426. switch (fm_info_get_enet_if(i)) {
  427. case PHY_INTERFACE_MODE_QSGMII:
  428. fm_info_set_mdio(i, NULL);
  429. break;
  430. case PHY_INTERFACE_MODE_SGMII:
  431. t1040_handle_phy_interface_sgmii(i);
  432. break;
  433. case PHY_INTERFACE_MODE_RGMII:
  434. /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
  435. t1040_handle_phy_interface_rgmii(i);
  436. break;
  437. default:
  438. break;
  439. }
  440. }
  441. #ifdef CONFIG_VSC9953
  442. for (i = 0; i < VSC9953_MAX_PORTS; i++) {
  443. lane = -1;
  444. phy_addr = 0;
  445. phy_int = PHY_INTERFACE_MODE_NONE;
  446. switch (i) {
  447. case 0:
  448. case 1:
  449. case 2:
  450. case 3:
  451. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
  452. /* PHYs connected over QSGMII */
  453. if (lane >= 0) {
  454. phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
  455. i;
  456. phy_int = PHY_INTERFACE_MODE_QSGMII;
  457. break;
  458. }
  459. lane = serdes_get_first_lane(FSL_SRDS_1,
  460. SGMII_SW1_MAC1 + i);
  461. if (lane < 0)
  462. break;
  463. /* PHYs connected over QSGMII */
  464. if (i != 3 || lane_to_slot[lane] == 7)
  465. phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
  466. + i;
  467. else
  468. phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
  469. phy_int = PHY_INTERFACE_MODE_SGMII;
  470. break;
  471. case 4:
  472. case 5:
  473. case 6:
  474. case 7:
  475. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
  476. /* PHYs connected over QSGMII */
  477. if (lane >= 0) {
  478. phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
  479. i - 4;
  480. phy_int = PHY_INTERFACE_MODE_QSGMII;
  481. break;
  482. }
  483. lane = serdes_get_first_lane(FSL_SRDS_1,
  484. SGMII_SW1_MAC1 + i);
  485. /* PHYs connected over SGMII */
  486. if (lane >= 0) {
  487. phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
  488. + i - 3;
  489. phy_int = PHY_INTERFACE_MODE_SGMII;
  490. }
  491. break;
  492. case 8:
  493. if (serdes_get_first_lane(FSL_SRDS_1,
  494. SGMII_FM1_DTSEC1) < 0)
  495. /* FM1@DTSEC1 is connected to SW1@PORT8 */
  496. vsc9953_port_enable(i);
  497. break;
  498. case 9:
  499. if (serdes_get_first_lane(FSL_SRDS_1,
  500. SGMII_FM1_DTSEC2) < 0) {
  501. /* Enable L2 On MAC2 using SCFG */
  502. struct ccsr_scfg *scfg = (struct ccsr_scfg *)
  503. CONFIG_SYS_MPC85xx_SCFG;
  504. out_be32(&scfg->esgmiiselcr,
  505. in_be32(&scfg->esgmiiselcr) |
  506. (0x80000000));
  507. vsc9953_port_enable(i);
  508. }
  509. break;
  510. }
  511. if (lane >= 0) {
  512. bus = mii_dev_for_muxval(lane_to_slot[lane]);
  513. vsc9953_port_info_set_mdio(i, bus);
  514. vsc9953_port_enable(i);
  515. }
  516. vsc9953_port_info_set_phy_address(i, phy_addr);
  517. vsc9953_port_info_set_phy_int(i, phy_int);
  518. }
  519. #endif
  520. cpu_eth_init(bis);
  521. #endif
  522. return pci_eth_init(bis);
  523. }