eth_t102xqds.c 11 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <netdev.h>
  11. #include <asm/mmu.h>
  12. #include <asm/processor.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_law.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <asm/fsl_portals.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <malloc.h>
  19. #include <fm_eth.h>
  20. #include <fsl_mdio.h>
  21. #include <miiphy.h>
  22. #include <phy.h>
  23. #include <fsl_dtsec.h>
  24. #include <asm/fsl_serdes.h>
  25. #include "../common/qixis.h"
  26. #include "../common/fman.h"
  27. #include "t102xqds_qixis.h"
  28. #define EMI_NONE 0xFFFFFFFF
  29. #define EMI1_RGMII1 0
  30. #define EMI1_RGMII2 1
  31. #define EMI1_SLOT1 2
  32. #define EMI1_SLOT2 3
  33. #define EMI1_SLOT3 4
  34. #define EMI1_SLOT4 5
  35. #define EMI1_SLOT5 6
  36. #define EMI2 7
  37. static int mdio_mux[NUM_FM_PORTS];
  38. static const char * const mdio_names[] = {
  39. "T1024QDS_MDIO_RGMII1",
  40. "T1024QDS_MDIO_RGMII2",
  41. "T1024QDS_MDIO_SLOT1",
  42. "T1024QDS_MDIO_SLOT2",
  43. "T1024QDS_MDIO_SLOT3",
  44. "T1024QDS_MDIO_SLOT4",
  45. "T1024QDS_MDIO_SLOT5",
  46. "T1024QDS_MDIO_10GC",
  47. "NULL",
  48. };
  49. /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
  50. static u8 lane_to_slot[] = {2, 3, 4, 5};
  51. static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
  52. {
  53. return mdio_names[muxval];
  54. }
  55. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  56. {
  57. struct mii_dev *bus;
  58. const char *name;
  59. if (muxval > EMI2)
  60. return NULL;
  61. name = t1024qds_mdio_name_for_muxval(muxval);
  62. if (!name) {
  63. printf("No bus for muxval %x\n", muxval);
  64. return NULL;
  65. }
  66. bus = miiphy_get_dev_by_name(name);
  67. if (!bus) {
  68. printf("No bus by name %s\n", name);
  69. return NULL;
  70. }
  71. return bus;
  72. }
  73. struct t1024qds_mdio {
  74. u8 muxval;
  75. struct mii_dev *realbus;
  76. };
  77. static void t1024qds_mux_mdio(u8 muxval)
  78. {
  79. u8 brdcfg4;
  80. if (muxval < 7) {
  81. brdcfg4 = QIXIS_READ(brdcfg[4]);
  82. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  83. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  84. QIXIS_WRITE(brdcfg[4], brdcfg4);
  85. }
  86. }
  87. static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  88. int regnum)
  89. {
  90. struct t1024qds_mdio *priv = bus->priv;
  91. t1024qds_mux_mdio(priv->muxval);
  92. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  93. }
  94. static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  95. int regnum, u16 value)
  96. {
  97. struct t1024qds_mdio *priv = bus->priv;
  98. t1024qds_mux_mdio(priv->muxval);
  99. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  100. }
  101. static int t1024qds_mdio_reset(struct mii_dev *bus)
  102. {
  103. struct t1024qds_mdio *priv = bus->priv;
  104. return priv->realbus->reset(priv->realbus);
  105. }
  106. static int t1024qds_mdio_init(char *realbusname, u8 muxval)
  107. {
  108. struct t1024qds_mdio *pmdio;
  109. struct mii_dev *bus = mdio_alloc();
  110. if (!bus) {
  111. printf("Failed to allocate t1024qds MDIO bus\n");
  112. return -1;
  113. }
  114. pmdio = malloc(sizeof(*pmdio));
  115. if (!pmdio) {
  116. printf("Failed to allocate t1024qds private data\n");
  117. free(bus);
  118. return -1;
  119. }
  120. bus->read = t1024qds_mdio_read;
  121. bus->write = t1024qds_mdio_write;
  122. bus->reset = t1024qds_mdio_reset;
  123. strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
  124. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  125. if (!pmdio->realbus) {
  126. printf("No bus with name %s\n", realbusname);
  127. free(bus);
  128. free(pmdio);
  129. return -1;
  130. }
  131. pmdio->muxval = muxval;
  132. bus->priv = pmdio;
  133. return mdio_register(bus);
  134. }
  135. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  136. enum fm_port port, int offset)
  137. {
  138. struct fixed_link f_link;
  139. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
  140. if (port == FM1_DTSEC3) {
  141. fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
  142. fdt_setprop_string(fdt, offset, "phy-connection-type",
  143. "rgmii");
  144. fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
  145. }
  146. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  147. if (port == FM1_DTSEC1) {
  148. fdt_set_phy_handle(fdt, compat, addr,
  149. "sgmii_vsc8234_phy_s5");
  150. } else if (port == FM1_DTSEC2) {
  151. fdt_set_phy_handle(fdt, compat, addr,
  152. "sgmii_vsc8234_phy_s4");
  153. }
  154. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
  155. if (port == FM1_DTSEC3) {
  156. fdt_set_phy_handle(fdt, compat, addr,
  157. "sgmii_aqr105_phy_s3");
  158. }
  159. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
  160. switch (port) {
  161. case FM1_DTSEC1:
  162. fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
  163. break;
  164. case FM1_DTSEC2:
  165. fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
  166. break;
  167. case FM1_DTSEC3:
  168. fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
  169. break;
  170. case FM1_DTSEC4:
  171. fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
  172. break;
  173. default:
  174. break;
  175. }
  176. fdt_delprop(fdt, offset, "phy-connection-type");
  177. fdt_setprop_string(fdt, offset, "phy-connection-type",
  178. "qsgmii");
  179. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  180. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  181. /* XFI interface */
  182. f_link.phy_id = port;
  183. f_link.duplex = 1;
  184. f_link.link_speed = 10000;
  185. f_link.pause = 0;
  186. f_link.asym_pause = 0;
  187. /* no PHY for XFI */
  188. fdt_delprop(fdt, offset, "phy-handle");
  189. fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
  190. fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
  191. }
  192. }
  193. void fdt_fixup_board_enet(void *fdt)
  194. {
  195. }
  196. /*
  197. * This function reads RCW to check if Serdes1{A:D} is configured
  198. * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
  199. */
  200. static void initialize_lane_to_slot(void)
  201. {
  202. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  203. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  204. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  205. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  206. switch (srds_s1) {
  207. case 0x46:
  208. case 0x47:
  209. lane_to_slot[1] = 2;
  210. break;
  211. default:
  212. break;
  213. }
  214. }
  215. int board_eth_init(bd_t *bis)
  216. {
  217. #if defined(CONFIG_FMAN_ENET)
  218. int i, idx, lane, slot, interface;
  219. struct memac_mdio_info dtsec_mdio_info;
  220. struct memac_mdio_info tgec_mdio_info;
  221. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  222. u32 srds_s1;
  223. srds_s1 = in_be32(&gur->rcwsr[4]) &
  224. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  225. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  226. initialize_lane_to_slot();
  227. /* Initialize the mdio_mux array so we can recognize empty elements */
  228. for (i = 0; i < NUM_FM_PORTS; i++)
  229. mdio_mux[i] = EMI_NONE;
  230. dtsec_mdio_info.regs =
  231. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  232. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  233. /* Register the 1G MDIO bus */
  234. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  235. tgec_mdio_info.regs =
  236. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  237. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  238. /* Register the 10G MDIO bus */
  239. fm_memac_mdio_init(bis, &tgec_mdio_info);
  240. /* Register the muxing front-ends to the MDIO buses */
  241. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  242. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  243. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  244. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  245. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  246. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  247. t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  248. t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  249. /* Set the two on-board RGMII PHY address */
  250. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
  251. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
  252. switch (srds_s1) {
  253. case 0xd5:
  254. case 0xd6:
  255. /* QSGMII in Slot2 */
  256. fm_info_set_phy_address(FM1_DTSEC1, 0x8);
  257. fm_info_set_phy_address(FM1_DTSEC2, 0x9);
  258. fm_info_set_phy_address(FM1_DTSEC3, 0xa);
  259. fm_info_set_phy_address(FM1_DTSEC4, 0xb);
  260. break;
  261. case 0x95:
  262. case 0x99:
  263. /*
  264. * XFI does not need a PHY to work, but to avoid U-boot use
  265. * default PHY address which is zero to a MAC when it found
  266. * a MAC has no PHY address, we give a PHY address to XFI
  267. * MAC, and should not use a real XAUI PHY address, since
  268. * MDIO can access it successfully, and then MDIO thinks the
  269. * XAUI card is used for the XFI MAC, which will cause error.
  270. */
  271. fm_info_set_phy_address(FM1_10GEC1, 4);
  272. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  273. break;
  274. case 0x6f:
  275. /* SGMII in Slot3, Slot4, Slot5 */
  276. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
  277. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
  278. fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
  279. break;
  280. case 0x7f:
  281. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
  282. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
  283. fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
  284. break;
  285. case 0x47:
  286. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  287. break;
  288. case 0x77:
  289. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  290. fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
  291. break;
  292. case 0x5a:
  293. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  294. break;
  295. case 0x6a:
  296. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  297. fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
  298. break;
  299. case 0x5b:
  300. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  301. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  302. break;
  303. case 0x6b:
  304. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  305. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  306. fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
  307. break;
  308. default:
  309. break;
  310. }
  311. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  312. idx = i - FM1_DTSEC1;
  313. interface = fm_info_get_enet_if(i);
  314. switch (interface) {
  315. case PHY_INTERFACE_MODE_SGMII:
  316. case PHY_INTERFACE_MODE_SGMII_2500:
  317. case PHY_INTERFACE_MODE_QSGMII:
  318. if (interface == PHY_INTERFACE_MODE_SGMII) {
  319. lane = serdes_get_first_lane(FSL_SRDS_1,
  320. SGMII_FM1_DTSEC1 + idx);
  321. } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
  322. lane = serdes_get_first_lane(FSL_SRDS_1,
  323. SGMII_2500_FM1_DTSEC1 + idx);
  324. } else {
  325. lane = serdes_get_first_lane(FSL_SRDS_1,
  326. QSGMII_FM1_A);
  327. }
  328. if (lane < 0)
  329. break;
  330. slot = lane_to_slot[lane];
  331. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  332. idx + 1, slot);
  333. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  334. fm_disable_port(i);
  335. switch (slot) {
  336. case 2:
  337. mdio_mux[i] = EMI1_SLOT2;
  338. fm_info_set_mdio(i, mii_dev_for_muxval(
  339. mdio_mux[i]));
  340. break;
  341. case 3:
  342. mdio_mux[i] = EMI1_SLOT3;
  343. fm_info_set_mdio(i, mii_dev_for_muxval(
  344. mdio_mux[i]));
  345. break;
  346. case 4:
  347. mdio_mux[i] = EMI1_SLOT4;
  348. fm_info_set_mdio(i, mii_dev_for_muxval(
  349. mdio_mux[i]));
  350. break;
  351. case 5:
  352. mdio_mux[i] = EMI1_SLOT5;
  353. fm_info_set_mdio(i, mii_dev_for_muxval(
  354. mdio_mux[i]));
  355. break;
  356. }
  357. break;
  358. case PHY_INTERFACE_MODE_RGMII:
  359. if (i == FM1_DTSEC3)
  360. mdio_mux[i] = EMI1_RGMII2;
  361. else if (i == FM1_DTSEC4)
  362. mdio_mux[i] = EMI1_RGMII1;
  363. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  364. break;
  365. default:
  366. break;
  367. }
  368. }
  369. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  370. idx = i - FM1_10GEC1;
  371. switch (fm_info_get_enet_if(i)) {
  372. case PHY_INTERFACE_MODE_XGMII:
  373. lane = serdes_get_first_lane(FSL_SRDS_1,
  374. XFI_FM1_MAC1 + idx);
  375. if (lane < 0)
  376. break;
  377. mdio_mux[i] = EMI2;
  378. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  379. break;
  380. default:
  381. break;
  382. }
  383. }
  384. cpu_eth_init(bis);
  385. #endif /* CONFIG_FMAN_ENET */
  386. return pci_eth_init(bis);
  387. }