eth.c 12 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <netdev.h>
  9. #include <fm_eth.h>
  10. #include <fsl_mdio.h>
  11. #include <fsl_dtsec.h>
  12. #include <malloc.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include "../common/qixis.h"
  15. #include "../common/fman.h"
  16. #include "ls1043aqds_qixis.h"
  17. #define EMI_NONE 0xFF
  18. #define EMI1_RGMII1 0
  19. #define EMI1_RGMII2 1
  20. #define EMI1_SLOT1 2
  21. #define EMI1_SLOT2 3
  22. #define EMI1_SLOT3 4
  23. #define EMI1_SLOT4 5
  24. #define EMI2 6
  25. static int mdio_mux[NUM_FM_PORTS];
  26. static const char * const mdio_names[] = {
  27. "LS1043AQDS_MDIO_RGMII1",
  28. "LS1043AQDS_MDIO_RGMII2",
  29. "LS1043AQDS_MDIO_SLOT1",
  30. "LS1043AQDS_MDIO_SLOT2",
  31. "LS1043AQDS_MDIO_SLOT3",
  32. "LS1043AQDS_MDIO_SLOT4",
  33. "NULL",
  34. };
  35. /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
  36. static u8 lane_to_slot[] = {1, 2, 3, 4};
  37. static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
  38. {
  39. return mdio_names[muxval];
  40. }
  41. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  42. {
  43. struct mii_dev *bus;
  44. const char *name;
  45. if (muxval > EMI2)
  46. return NULL;
  47. name = ls1043aqds_mdio_name_for_muxval(muxval);
  48. if (!name) {
  49. printf("No bus for muxval %x\n", muxval);
  50. return NULL;
  51. }
  52. bus = miiphy_get_dev_by_name(name);
  53. if (!bus) {
  54. printf("No bus by name %s\n", name);
  55. return NULL;
  56. }
  57. return bus;
  58. }
  59. struct ls1043aqds_mdio {
  60. u8 muxval;
  61. struct mii_dev *realbus;
  62. };
  63. static void ls1043aqds_mux_mdio(u8 muxval)
  64. {
  65. u8 brdcfg4;
  66. if (muxval < 7) {
  67. brdcfg4 = QIXIS_READ(brdcfg[4]);
  68. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  69. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  70. QIXIS_WRITE(brdcfg[4], brdcfg4);
  71. }
  72. }
  73. static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  74. int regnum)
  75. {
  76. struct ls1043aqds_mdio *priv = bus->priv;
  77. ls1043aqds_mux_mdio(priv->muxval);
  78. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  79. }
  80. static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  81. int regnum, u16 value)
  82. {
  83. struct ls1043aqds_mdio *priv = bus->priv;
  84. ls1043aqds_mux_mdio(priv->muxval);
  85. return priv->realbus->write(priv->realbus, addr, devad,
  86. regnum, value);
  87. }
  88. static int ls1043aqds_mdio_reset(struct mii_dev *bus)
  89. {
  90. struct ls1043aqds_mdio *priv = bus->priv;
  91. return priv->realbus->reset(priv->realbus);
  92. }
  93. static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
  94. {
  95. struct ls1043aqds_mdio *pmdio;
  96. struct mii_dev *bus = mdio_alloc();
  97. if (!bus) {
  98. printf("Failed to allocate ls1043aqds MDIO bus\n");
  99. return -1;
  100. }
  101. pmdio = malloc(sizeof(*pmdio));
  102. if (!pmdio) {
  103. printf("Failed to allocate ls1043aqds private data\n");
  104. free(bus);
  105. return -1;
  106. }
  107. bus->read = ls1043aqds_mdio_read;
  108. bus->write = ls1043aqds_mdio_write;
  109. bus->reset = ls1043aqds_mdio_reset;
  110. strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
  111. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  112. if (!pmdio->realbus) {
  113. printf("No bus with name %s\n", realbusname);
  114. free(bus);
  115. free(pmdio);
  116. return -1;
  117. }
  118. pmdio->muxval = muxval;
  119. bus->priv = pmdio;
  120. return mdio_register(bus);
  121. }
  122. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  123. enum fm_port port, int offset)
  124. {
  125. struct fixed_link f_link;
  126. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  127. if (port == FM1_DTSEC9) {
  128. fdt_set_phy_handle(fdt, compat, addr,
  129. "sgmii_riser_s1_p1");
  130. } else if (port == FM1_DTSEC2) {
  131. fdt_set_phy_handle(fdt, compat, addr,
  132. "sgmii_riser_s2_p1");
  133. } else if (port == FM1_DTSEC5) {
  134. fdt_set_phy_handle(fdt, compat, addr,
  135. "sgmii_riser_s3_p1");
  136. } else if (port == FM1_DTSEC6) {
  137. fdt_set_phy_handle(fdt, compat, addr,
  138. "sgmii_riser_s4_p1");
  139. }
  140. } else if (fm_info_get_enet_if(port) ==
  141. PHY_INTERFACE_MODE_SGMII_2500) {
  142. /* 2.5G SGMII interface */
  143. f_link.phy_id = port;
  144. f_link.duplex = 1;
  145. f_link.link_speed = 1000;
  146. f_link.pause = 0;
  147. f_link.asym_pause = 0;
  148. /* no PHY for 2.5G SGMII */
  149. fdt_delprop(fdt, offset, "phy-handle");
  150. fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
  151. fdt_setprop_string(fdt, offset, "phy-connection-type",
  152. "sgmii-2500");
  153. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
  154. switch (mdio_mux[port]) {
  155. case EMI1_SLOT1:
  156. switch (port) {
  157. case FM1_DTSEC1:
  158. fdt_set_phy_handle(fdt, compat, addr,
  159. "qsgmii_s1_p1");
  160. break;
  161. case FM1_DTSEC2:
  162. fdt_set_phy_handle(fdt, compat, addr,
  163. "qsgmii_s1_p2");
  164. break;
  165. case FM1_DTSEC5:
  166. fdt_set_phy_handle(fdt, compat, addr,
  167. "qsgmii_s1_p3");
  168. break;
  169. case FM1_DTSEC6:
  170. fdt_set_phy_handle(fdt, compat, addr,
  171. "qsgmii_s1_p4");
  172. break;
  173. default:
  174. break;
  175. }
  176. break;
  177. case EMI1_SLOT2:
  178. switch (port) {
  179. case FM1_DTSEC1:
  180. fdt_set_phy_handle(fdt, compat, addr,
  181. "qsgmii_s2_p1");
  182. break;
  183. case FM1_DTSEC2:
  184. fdt_set_phy_handle(fdt, compat, addr,
  185. "qsgmii_s2_p2");
  186. break;
  187. case FM1_DTSEC5:
  188. fdt_set_phy_handle(fdt, compat, addr,
  189. "qsgmii_s2_p3");
  190. break;
  191. case FM1_DTSEC6:
  192. fdt_set_phy_handle(fdt, compat, addr,
  193. "qsgmii_s2_p4");
  194. break;
  195. default:
  196. break;
  197. }
  198. break;
  199. default:
  200. break;
  201. }
  202. fdt_delprop(fdt, offset, "phy-connection-type");
  203. fdt_setprop_string(fdt, offset, "phy-connection-type",
  204. "qsgmii");
  205. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
  206. port == FM1_10GEC1) {
  207. /* XFI interface */
  208. f_link.phy_id = port;
  209. f_link.duplex = 1;
  210. f_link.link_speed = 10000;
  211. f_link.pause = 0;
  212. f_link.asym_pause = 0;
  213. /* no PHY for XFI */
  214. fdt_delprop(fdt, offset, "phy-handle");
  215. fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
  216. fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
  217. }
  218. }
  219. void fdt_fixup_board_enet(void *fdt)
  220. {
  221. int i;
  222. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  223. u32 srds_s1;
  224. srds_s1 = in_be32(&gur->rcwsr[4]) &
  225. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  226. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  227. for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
  228. switch (fm_info_get_enet_if(i)) {
  229. case PHY_INTERFACE_MODE_SGMII:
  230. case PHY_INTERFACE_MODE_QSGMII:
  231. switch (mdio_mux[i]) {
  232. case EMI1_SLOT1:
  233. fdt_status_okay_by_alias(fdt, "emi1_slot1");
  234. break;
  235. case EMI1_SLOT2:
  236. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  237. break;
  238. case EMI1_SLOT3:
  239. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  240. break;
  241. case EMI1_SLOT4:
  242. fdt_status_okay_by_alias(fdt, "emi1_slot4");
  243. break;
  244. default:
  245. break;
  246. }
  247. break;
  248. case PHY_INTERFACE_MODE_XGMII:
  249. break;
  250. default:
  251. break;
  252. }
  253. }
  254. }
  255. int board_eth_init(bd_t *bis)
  256. {
  257. #ifdef CONFIG_FMAN_ENET
  258. int i, idx, lane, slot, interface;
  259. struct memac_mdio_info dtsec_mdio_info;
  260. struct memac_mdio_info tgec_mdio_info;
  261. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  262. u32 srds_s1;
  263. srds_s1 = in_be32(&gur->rcwsr[4]) &
  264. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  265. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  266. /* Initialize the mdio_mux array so we can recognize empty elements */
  267. for (i = 0; i < NUM_FM_PORTS; i++)
  268. mdio_mux[i] = EMI_NONE;
  269. dtsec_mdio_info.regs =
  270. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  271. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  272. /* Register the 1G MDIO bus */
  273. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  274. tgec_mdio_info.regs =
  275. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  276. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  277. /* Register the 10G MDIO bus */
  278. fm_memac_mdio_init(bis, &tgec_mdio_info);
  279. /* Register the muxing front-ends to the MDIO buses */
  280. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  281. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  282. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  283. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  284. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  285. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  286. ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  287. /* Set the two on-board RGMII PHY address */
  288. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  289. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  290. switch (srds_s1) {
  291. case 0x2555:
  292. /* 2.5G SGMII on lane A, MAC 9 */
  293. fm_info_set_phy_address(FM1_DTSEC9, 9);
  294. break;
  295. case 0x4555:
  296. case 0x4558:
  297. /* QSGMII on lane A, MAC 1/2/5/6 */
  298. fm_info_set_phy_address(FM1_DTSEC1,
  299. QSGMII_CARD_PORT1_PHY_ADDR_S1);
  300. fm_info_set_phy_address(FM1_DTSEC2,
  301. QSGMII_CARD_PORT2_PHY_ADDR_S1);
  302. fm_info_set_phy_address(FM1_DTSEC5,
  303. QSGMII_CARD_PORT3_PHY_ADDR_S1);
  304. fm_info_set_phy_address(FM1_DTSEC6,
  305. QSGMII_CARD_PORT4_PHY_ADDR_S1);
  306. break;
  307. case 0x1355:
  308. /* SGMII on lane B, MAC 2*/
  309. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  310. break;
  311. case 0x2355:
  312. /* 2.5G SGMII on lane A, MAC 9 */
  313. fm_info_set_phy_address(FM1_DTSEC9, 9);
  314. /* SGMII on lane B, MAC 2*/
  315. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  316. break;
  317. case 0x3335:
  318. /* SGMII on lane C, MAC 5 */
  319. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  320. case 0x3355:
  321. case 0x3358:
  322. /* SGMII on lane B, MAC 2 */
  323. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  324. case 0x3555:
  325. case 0x3558:
  326. /* SGMII on lane A, MAC 9 */
  327. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  328. break;
  329. case 0x1455:
  330. /* QSGMII on lane B, MAC 1/2/5/6 */
  331. fm_info_set_phy_address(FM1_DTSEC1,
  332. QSGMII_CARD_PORT1_PHY_ADDR_S2);
  333. fm_info_set_phy_address(FM1_DTSEC2,
  334. QSGMII_CARD_PORT2_PHY_ADDR_S2);
  335. fm_info_set_phy_address(FM1_DTSEC5,
  336. QSGMII_CARD_PORT3_PHY_ADDR_S2);
  337. fm_info_set_phy_address(FM1_DTSEC6,
  338. QSGMII_CARD_PORT4_PHY_ADDR_S2);
  339. break;
  340. case 0x2455:
  341. /* 2.5G SGMII on lane A, MAC 9 */
  342. fm_info_set_phy_address(FM1_DTSEC9, 9);
  343. /* QSGMII on lane B, MAC 1/2/5/6 */
  344. fm_info_set_phy_address(FM1_DTSEC1,
  345. QSGMII_CARD_PORT1_PHY_ADDR_S2);
  346. fm_info_set_phy_address(FM1_DTSEC2,
  347. QSGMII_CARD_PORT2_PHY_ADDR_S2);
  348. fm_info_set_phy_address(FM1_DTSEC5,
  349. QSGMII_CARD_PORT3_PHY_ADDR_S2);
  350. fm_info_set_phy_address(FM1_DTSEC6,
  351. QSGMII_CARD_PORT4_PHY_ADDR_S2);
  352. break;
  353. case 0x2255:
  354. /* 2.5G SGMII on lane A, MAC 9 */
  355. fm_info_set_phy_address(FM1_DTSEC9, 9);
  356. /* 2.5G SGMII on lane B, MAC 2 */
  357. fm_info_set_phy_address(FM1_DTSEC2, 2);
  358. break;
  359. case 0x3333:
  360. /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
  361. fm_info_set_phy_address(FM1_DTSEC9,
  362. SGMII_CARD_PORT1_PHY_ADDR);
  363. fm_info_set_phy_address(FM1_DTSEC2,
  364. SGMII_CARD_PORT1_PHY_ADDR);
  365. fm_info_set_phy_address(FM1_DTSEC5,
  366. SGMII_CARD_PORT1_PHY_ADDR);
  367. fm_info_set_phy_address(FM1_DTSEC6,
  368. SGMII_CARD_PORT1_PHY_ADDR);
  369. break;
  370. default:
  371. printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
  372. srds_s1);
  373. break;
  374. }
  375. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  376. idx = i - FM1_DTSEC1;
  377. interface = fm_info_get_enet_if(i);
  378. switch (interface) {
  379. case PHY_INTERFACE_MODE_SGMII:
  380. case PHY_INTERFACE_MODE_SGMII_2500:
  381. case PHY_INTERFACE_MODE_QSGMII:
  382. if (interface == PHY_INTERFACE_MODE_SGMII) {
  383. lane = serdes_get_first_lane(FSL_SRDS_1,
  384. SGMII_FM1_DTSEC1 + idx);
  385. } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
  386. lane = serdes_get_first_lane(FSL_SRDS_1,
  387. SGMII_2500_FM1_DTSEC1 + idx);
  388. } else {
  389. lane = serdes_get_first_lane(FSL_SRDS_1,
  390. QSGMII_FM1_A);
  391. }
  392. if (lane < 0)
  393. break;
  394. slot = lane_to_slot[lane];
  395. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  396. idx + 1, slot);
  397. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  398. fm_disable_port(i);
  399. switch (slot) {
  400. case 1:
  401. mdio_mux[i] = EMI1_SLOT1;
  402. fm_info_set_mdio(i, mii_dev_for_muxval(
  403. mdio_mux[i]));
  404. break;
  405. case 2:
  406. mdio_mux[i] = EMI1_SLOT2;
  407. fm_info_set_mdio(i, mii_dev_for_muxval(
  408. mdio_mux[i]));
  409. break;
  410. case 3:
  411. mdio_mux[i] = EMI1_SLOT3;
  412. fm_info_set_mdio(i, mii_dev_for_muxval(
  413. mdio_mux[i]));
  414. break;
  415. case 4:
  416. mdio_mux[i] = EMI1_SLOT4;
  417. fm_info_set_mdio(i, mii_dev_for_muxval(
  418. mdio_mux[i]));
  419. break;
  420. default:
  421. break;
  422. }
  423. break;
  424. case PHY_INTERFACE_MODE_RGMII:
  425. if (i == FM1_DTSEC3)
  426. mdio_mux[i] = EMI1_RGMII1;
  427. else if (i == FM1_DTSEC4)
  428. mdio_mux[i] = EMI1_RGMII2;
  429. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  430. break;
  431. default:
  432. break;
  433. }
  434. }
  435. cpu_eth_init(bis);
  436. #endif /* CONFIG_FMAN_ENET */
  437. return pci_eth_init(bis);
  438. }