eth_superhydra.c 23 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * This file handles the board muxing between the Fman Ethernet MACs and
  9. * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
  10. * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
  11. * provided by the standard Freescale four-port SGMII riser card. The 10Gb
  12. * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
  13. * and 5 1G interfaces and 10G interface per FMan. Based on the options in
  14. * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
  15. *
  16. * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
  17. * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
  18. * always the same (0). The value for SGMII depends on which slot the riser is
  19. * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
  20. * the value is based on which slot the XAUI is inserted in.
  21. *
  22. * The SERDES configuration is used to determine where the SGMII and XAUI cards
  23. * exist, and also which Fman's MACs are routed to which PHYs. So for a given
  24. * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
  25. * to PHYs dynamically.
  26. *
  27. *
  28. * This file also updates the device tree in three ways:
  29. *
  30. * 1) The status of each virtual MDIO node that is referenced by an Ethernet
  31. * node is set to "okay".
  32. *
  33. * 2) The phy-handle property of each active Ethernet MAC node is set to the
  34. * appropriate PHY node.
  35. *
  36. * 3) The "mux value" for each virtual MDIO node is set to the correct value,
  37. * if necessary. Some virtual MDIO nodes do not have configurable mux
  38. * values, so those values are hard-coded in the DTS. On the HYDRA board,
  39. * the virtual MDIO node for the SGMII card needs to be updated.
  40. *
  41. * For all this to work, the device tree needs to have the following:
  42. *
  43. * 1) An alias for each PHY node that an Ethernet node could be routed to.
  44. *
  45. * 2) An alias for each real and virtual MDIO node that is disabled by default
  46. * and might need to be enabled, and also might need to have its mux-value
  47. * updated.
  48. */
  49. #include <common.h>
  50. #include <netdev.h>
  51. #include <asm/fsl_serdes.h>
  52. #include <fm_eth.h>
  53. #include <fsl_mdio.h>
  54. #include <malloc.h>
  55. #include <fdt_support.h>
  56. #include <fsl_dtsec.h>
  57. #include "../common/ngpixis.h"
  58. #include "../common/fman.h"
  59. #ifdef CONFIG_FMAN_ENET
  60. #define BRDCFG1_EMI1_SEL_MASK 0x70
  61. #define BRDCFG1_EMI1_SEL_SLOT1 0x10
  62. #define BRDCFG1_EMI1_SEL_SLOT2 0x20
  63. #define BRDCFG1_EMI1_SEL_SLOT5 0x30
  64. #define BRDCFG1_EMI1_SEL_SLOT6 0x40
  65. #define BRDCFG1_EMI1_SEL_SLOT7 0x50
  66. #define BRDCFG1_EMI1_SEL_SLOT3 0x60
  67. #define BRDCFG1_EMI1_SEL_RGMII 0x00
  68. #define BRDCFG1_EMI1_EN 0x08
  69. #define BRDCFG1_EMI2_SEL_MASK 0x06
  70. #define BRDCFG1_EMI2_SEL_SLOT1 0x00
  71. #define BRDCFG1_EMI2_SEL_SLOT2 0x02
  72. #define BRDCFG2_REG_GPIO_SEL 0x20
  73. /* SGMII */
  74. #define PHY_BASE_ADDR 0x00
  75. #define REGNUM 0x00
  76. #define PORT_NUM_FM1 0x04
  77. #define PORT_NUM_FM2 0x02
  78. /*
  79. * BRDCFG1 mask and value for each MAC
  80. *
  81. * This array contains the BRDCFG1 values (in mask/val format) that route the
  82. * MDIO bus to a particular RGMII or SGMII PHY.
  83. */
  84. static struct {
  85. u8 mask;
  86. u8 val;
  87. } mdio_mux[NUM_FM_PORTS];
  88. /*
  89. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  90. * that the mapping must be determined dynamically, or that the lane maps to
  91. * something other than a board slot
  92. */
  93. static u8 lane_to_slot[] = {
  94. 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
  95. };
  96. /*
  97. * Set the board muxing for a given MAC
  98. *
  99. * The MDIO layer calls this function every time it wants to talk to a PHY.
  100. */
  101. void super_hydra_mux_mdio(u8 mask, u8 val)
  102. {
  103. clrsetbits_8(&pixis->brdcfg1, mask, val);
  104. }
  105. struct super_hydra_mdio {
  106. u8 mask;
  107. u8 val;
  108. struct mii_dev *realbus;
  109. };
  110. static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
  111. int regnum)
  112. {
  113. struct super_hydra_mdio *priv = bus->priv;
  114. super_hydra_mux_mdio(priv->mask, priv->val);
  115. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  116. }
  117. static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
  118. int regnum, u16 value)
  119. {
  120. struct super_hydra_mdio *priv = bus->priv;
  121. super_hydra_mux_mdio(priv->mask, priv->val);
  122. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  123. }
  124. static int super_hydra_mdio_reset(struct mii_dev *bus)
  125. {
  126. struct super_hydra_mdio *priv = bus->priv;
  127. return priv->realbus->reset(priv->realbus);
  128. }
  129. static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
  130. {
  131. struct mii_dev *bus = miiphy_get_dev_by_name(name);
  132. struct super_hydra_mdio *priv = bus->priv;
  133. priv->mask = mask;
  134. priv->val = val;
  135. }
  136. static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
  137. {
  138. struct super_hydra_mdio *hmdio;
  139. struct mii_dev *bus = mdio_alloc();
  140. if (!bus) {
  141. printf("Failed to allocate Hydra MDIO bus\n");
  142. return -1;
  143. }
  144. hmdio = malloc(sizeof(*hmdio));
  145. if (!hmdio) {
  146. printf("Failed to allocate Hydra private data\n");
  147. free(bus);
  148. return -1;
  149. }
  150. bus->read = super_hydra_mdio_read;
  151. bus->write = super_hydra_mdio_write;
  152. bus->reset = super_hydra_mdio_reset;
  153. strcpy(bus->name, fakebusname);
  154. hmdio->realbus = miiphy_get_dev_by_name(realbusname);
  155. if (!hmdio->realbus) {
  156. printf("No bus with name %s\n", realbusname);
  157. free(bus);
  158. free(hmdio);
  159. return -1;
  160. }
  161. bus->priv = hmdio;
  162. return mdio_register(bus);
  163. }
  164. /*
  165. * Given the following ...
  166. *
  167. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  168. * compatible string and 'addr' physical address)
  169. *
  170. * 2) An Fman port
  171. *
  172. * ... update the phy-handle property of the Ethernet node to point to the
  173. * right PHY. This assumes that we already know the PHY for each port. That
  174. * information is stored in mdio_mux[].
  175. *
  176. * The offset of the Fman Ethernet node is also passed in for convenience, but
  177. * it is not used.
  178. *
  179. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  180. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  181. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  182. * and ports are the same thing.
  183. */
  184. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  185. enum fm_port port, int offset)
  186. {
  187. enum srds_prtcl device;
  188. int lane, slot, phy;
  189. char alias[32];
  190. /* RGMII and XGMII are already mapped correctly in the DTS */
  191. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  192. device = serdes_device_from_fm_port(port);
  193. lane = serdes_get_first_lane(device);
  194. slot = lane_to_slot[lane];
  195. phy = fm_info_get_phy_address(port);
  196. sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
  197. fdt_set_phy_handle(fdt, compat, addr, alias);
  198. }
  199. }
  200. #define PIXIS_SW2_LANE_23_SEL 0x80
  201. #define PIXIS_SW2_LANE_45_SEL 0x40
  202. #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
  203. #define PIXIS_SW2_LANE_67_SEL_5 0x00
  204. #define PIXIS_SW2_LANE_67_SEL_6 0x20
  205. #define PIXIS_SW2_LANE_67_SEL_7 0x10
  206. #define PIXIS_SW2_LANE_8_SEL 0x08
  207. #define PIXIS_SW2_LANE_1617_SEL 0x04
  208. #define PIXIS_SW11_LANE_9_SEL 0x04
  209. /*
  210. * Initialize the lane_to_slot[] array.
  211. *
  212. * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
  213. * slots is hard-coded. On the Hydra board, however, the mapping is controlled
  214. * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
  215. * initialized.
  216. */
  217. static void initialize_lane_to_slot(void)
  218. {
  219. u8 sw2 = in_8(&PIXIS_SW(2));
  220. /* SW11 appears in the programming model as SW9 */
  221. u8 sw11 = in_8(&PIXIS_SW(9));
  222. lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
  223. lane_to_slot[3] = lane_to_slot[2];
  224. lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
  225. lane_to_slot[5] = lane_to_slot[4];
  226. switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
  227. case PIXIS_SW2_LANE_67_SEL_5:
  228. lane_to_slot[6] = 5;
  229. break;
  230. case PIXIS_SW2_LANE_67_SEL_6:
  231. lane_to_slot[6] = 6;
  232. break;
  233. case PIXIS_SW2_LANE_67_SEL_7:
  234. lane_to_slot[6] = 7;
  235. break;
  236. }
  237. lane_to_slot[7] = lane_to_slot[6];
  238. lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
  239. lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
  240. lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
  241. lane_to_slot[17] = lane_to_slot[16];
  242. }
  243. #endif /* #ifdef CONFIG_FMAN_ENET */
  244. /*
  245. * Configure the status for the virtual MDIO nodes
  246. *
  247. * Rather than create the virtual MDIO nodes from scratch for each active
  248. * virtual MDIO, we expect the DTS to have the nodes defined already, and we
  249. * only enable the ones that are actually active.
  250. *
  251. * We assume that the DTS already hard-codes the status for all the
  252. * virtual MDIO nodes to "disabled", so all we need to do is enable the
  253. * active ones.
  254. */
  255. void fdt_fixup_board_enet(void *fdt)
  256. {
  257. #ifdef CONFIG_FMAN_ENET
  258. enum fm_port i;
  259. int lane, slot;
  260. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  261. int idx = i - FM1_DTSEC1;
  262. switch (fm_info_get_enet_if(i)) {
  263. case PHY_INTERFACE_MODE_SGMII:
  264. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  265. if (lane >= 0) {
  266. char alias[32];
  267. slot = lane_to_slot[lane];
  268. sprintf(alias, "hydra_sg_slot%u", slot);
  269. fdt_status_okay_by_alias(fdt, alias);
  270. debug("Enabled MDIO node %s (slot %i)\n",
  271. alias, slot);
  272. }
  273. break;
  274. case PHY_INTERFACE_MODE_RGMII:
  275. fdt_status_okay_by_alias(fdt, "hydra_rg");
  276. debug("Enabled MDIO node hydra_rg\n");
  277. break;
  278. default:
  279. break;
  280. }
  281. }
  282. lane = serdes_get_first_lane(XAUI_FM1);
  283. if (lane >= 0) {
  284. char alias[32];
  285. slot = lane_to_slot[lane];
  286. sprintf(alias, "hydra_xg_slot%u", slot);
  287. fdt_status_okay_by_alias(fdt, alias);
  288. debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
  289. }
  290. #if CONFIG_SYS_NUM_FMAN == 2
  291. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  292. int idx = i - FM2_DTSEC1;
  293. switch (fm_info_get_enet_if(i)) {
  294. case PHY_INTERFACE_MODE_SGMII:
  295. lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
  296. if (lane >= 0) {
  297. char alias[32];
  298. slot = lane_to_slot[lane];
  299. sprintf(alias, "hydra_sg_slot%u", slot);
  300. fdt_status_okay_by_alias(fdt, alias);
  301. debug("Enabled MDIO node %s (slot %i)\n",
  302. alias, slot);
  303. }
  304. break;
  305. case PHY_INTERFACE_MODE_RGMII:
  306. fdt_status_okay_by_alias(fdt, "hydra_rg");
  307. debug("Enabled MDIO node hydra_rg\n");
  308. break;
  309. default:
  310. break;
  311. }
  312. }
  313. lane = serdes_get_first_lane(XAUI_FM2);
  314. if (lane >= 0) {
  315. char alias[32];
  316. slot = lane_to_slot[lane];
  317. sprintf(alias, "hydra_xg_slot%u", slot);
  318. fdt_status_okay_by_alias(fdt, alias);
  319. debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
  320. }
  321. #endif /* CONFIG_SYS_NUM_FMAN == 2 */
  322. #endif /* CONFIG_FMAN_ENET */
  323. }
  324. /*
  325. * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
  326. *
  327. * Fman 1:
  328. * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
  329. * Mux Phy | Mux Phy | Mux Phy | Mux Phy
  330. * Value Addr | Value Addr | Value Addr | Value Addr
  331. * 0x00 2 1c | 2 1d | 2 1e | 2 1f
  332. * 0x01 | | 6 1c |
  333. * 0x02 | | 3 1c | 3 1d
  334. * 0x03 2 1c | 2 1d | 2 1e | 2 1f
  335. * 0x04 2 1c | 2 1d | 2 1e | 2 1f
  336. * 0x05 | | 3 1c | 3 1d
  337. * 0x06 2 1c | 2 1d | 2 1e | 2 1f
  338. * 0x07 | | 6 1c |
  339. * 0x11 2 1c | 2 1d | 2 1e | 2 1f
  340. * 0x2a 2 | | 2 1e | 2 1f
  341. * 0x34 6 1c | 6 1d | 4 1e | 4 1f
  342. * 0x35 | | 3 1c | 3 1d
  343. * 0x36 6 1c | 6 1d | 4 1e | 4 1f
  344. * | | |
  345. * Fman 2: | | |
  346. * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
  347. * EMI1 | EMI1 | EMI1 | EMI1
  348. * Mux Phy | Mux Phy | Mux Phy | Mux Phy
  349. * Value Addr | Value Addr | Value Addr | Value Addr
  350. * 0x00 | | 6 1c | 6 1d
  351. * 0x01 | | |
  352. * 0x02 | | 6 1c | 6 1d
  353. * 0x03 3 1c | 3 1d | 6 1c | 6 1d
  354. * 0x04 3 1c | 3 1d | 6 1c | 6 1d
  355. * 0x05 | | 6 1c | 6 1d
  356. * 0x06 | | 6 1c | 6 1d
  357. * 0x07 | | |
  358. * 0x11 | | |
  359. * 0x2a | | |
  360. * 0x34 | | |
  361. * 0x35 | | |
  362. * 0x36 | | |
  363. */
  364. int board_eth_init(bd_t *bis)
  365. {
  366. #ifdef CONFIG_FMAN_ENET
  367. struct fsl_pq_mdio_info dtsec_mdio_info;
  368. struct tgec_mdio_info tgec_mdio_info;
  369. unsigned int i, slot;
  370. int lane;
  371. struct mii_dev *bus;
  372. int qsgmii;
  373. int phy_real_addr;
  374. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  375. int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  376. FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  377. printf("Initializing Fman\n");
  378. initialize_lane_to_slot();
  379. /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
  380. setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
  381. memset(mdio_mux, 0, sizeof(mdio_mux));
  382. dtsec_mdio_info.regs =
  383. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  384. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  385. /* Register the real 1G MDIO bus */
  386. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  387. tgec_mdio_info.regs =
  388. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  389. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  390. /* Register the real 10G MDIO bus */
  391. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  392. /* Register the three virtual MDIO front-ends */
  393. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  394. "SUPER_HYDRA_RGMII_MDIO");
  395. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  396. "SUPER_HYDRA_FM1_SGMII_MDIO");
  397. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  398. "SUPER_HYDRA_FM2_SGMII_MDIO");
  399. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  400. "SUPER_HYDRA_FM3_SGMII_MDIO");
  401. super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
  402. "SUPER_HYDRA_FM1_TGEC_MDIO");
  403. super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
  404. "SUPER_HYDRA_FM2_TGEC_MDIO");
  405. /*
  406. * Program the DTSEC PHY addresses assuming that they are all SGMII.
  407. * For any DTSEC that's RGMII, we'll override its PHY address later.
  408. * We assume that DTSEC5 is only used for RGMII.
  409. */
  410. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  411. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  412. fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
  413. #if (CONFIG_SYS_NUM_FMAN == 2)
  414. fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
  415. fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
  416. fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
  417. fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
  418. fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  419. #endif
  420. switch (srds_prtcl) {
  421. case 0:
  422. case 3:
  423. case 4:
  424. case 6:
  425. case 0x11:
  426. case 0x2a:
  427. case 0x34:
  428. case 0x36:
  429. fm_info_set_phy_address(FM1_DTSEC3,
  430. CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  431. fm_info_set_phy_address(FM1_DTSEC4,
  432. CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  433. break;
  434. case 1:
  435. case 2:
  436. case 5:
  437. case 7:
  438. case 0x35:
  439. fm_info_set_phy_address(FM1_DTSEC3,
  440. CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  441. fm_info_set_phy_address(FM1_DTSEC4,
  442. CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  443. break;
  444. default:
  445. printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
  446. break;
  447. }
  448. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  449. int idx = i - FM1_DTSEC1;
  450. switch (fm_info_get_enet_if(i)) {
  451. case PHY_INTERFACE_MODE_SGMII:
  452. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  453. if (lane < 0)
  454. break;
  455. slot = lane_to_slot[lane];
  456. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  457. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  458. idx + 1, slot);
  459. switch (slot) {
  460. case 1:
  461. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
  462. BRDCFG1_EMI1_EN;
  463. break;
  464. case 2:
  465. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
  466. BRDCFG1_EMI1_EN;
  467. break;
  468. case 3:
  469. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
  470. BRDCFG1_EMI1_EN;
  471. break;
  472. case 5:
  473. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
  474. BRDCFG1_EMI1_EN;
  475. break;
  476. case 6:
  477. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
  478. BRDCFG1_EMI1_EN;
  479. break;
  480. case 7:
  481. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
  482. BRDCFG1_EMI1_EN;
  483. break;
  484. };
  485. super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
  486. mdio_mux[i].mask, mdio_mux[i].val);
  487. fm_info_set_mdio(i,
  488. miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
  489. break;
  490. case PHY_INTERFACE_MODE_RGMII:
  491. /*
  492. * FM1 DTSEC5 is routed via EC1 to the first on-board
  493. * RGMII port. FM2 DTSEC5 is routed via EC2 to the
  494. * second on-board RGMII port. The other DTSECs cannot
  495. * be routed to RGMII.
  496. */
  497. debug("FM1@DTSEC%u is RGMII at address %u\n",
  498. idx + 1, 0);
  499. fm_info_set_phy_address(i, 0);
  500. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  501. mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
  502. BRDCFG1_EMI1_EN;
  503. super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
  504. mdio_mux[i].mask, mdio_mux[i].val);
  505. fm_info_set_mdio(i,
  506. miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
  507. break;
  508. case PHY_INTERFACE_MODE_NONE:
  509. fm_info_set_phy_address(i, 0);
  510. break;
  511. default:
  512. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  513. idx + 1, fm_info_get_enet_if(i));
  514. fm_info_set_phy_address(i, 0);
  515. break;
  516. }
  517. }
  518. bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
  519. qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
  520. if (qsgmii) {
  521. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
  522. if (fm_info_get_enet_if(i) ==
  523. PHY_INTERFACE_MODE_SGMII) {
  524. phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
  525. fm_info_set_phy_address(i, phy_real_addr);
  526. }
  527. }
  528. switch (srds_prtcl) {
  529. case 0x00:
  530. case 0x03:
  531. case 0x04:
  532. case 0x06:
  533. case 0x11:
  534. case 0x2a:
  535. case 0x34:
  536. case 0x36:
  537. fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
  538. fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
  539. break;
  540. case 0x01:
  541. case 0x02:
  542. case 0x05:
  543. case 0x07:
  544. case 0x35:
  545. fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
  546. fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
  547. break;
  548. default:
  549. break;
  550. }
  551. }
  552. /*
  553. * For 10G, we only support one XAUI card per Fman. If present, then we
  554. * force its routing and never touch those bits again, which removes the
  555. * need for Linux to do any muxing. This works because of the way
  556. * BRDCFG1 is defined, but it's a bit hackish.
  557. *
  558. * The PHY address for the XAUI card depends on which slot it's in. The
  559. * macros we use imply that the PHY address is based on which FM, but
  560. * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
  561. * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
  562. * check the actual slot and just use the macros as-is, even though
  563. * the P3041 and P5020 only have one Fman.
  564. */
  565. lane = serdes_get_first_lane(XAUI_FM1);
  566. if (lane >= 0) {
  567. debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
  568. mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
  569. mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
  570. super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
  571. mdio_mux[i].mask, mdio_mux[i].val);
  572. }
  573. fm_info_set_mdio(FM1_10GEC1,
  574. miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
  575. #if (CONFIG_SYS_NUM_FMAN == 2)
  576. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  577. int idx = i - FM2_DTSEC1;
  578. switch (fm_info_get_enet_if(i)) {
  579. case PHY_INTERFACE_MODE_SGMII:
  580. lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
  581. if (lane < 0)
  582. break;
  583. slot = lane_to_slot[lane];
  584. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  585. debug("FM2@DTSEC%u expects SGMII in slot %u\n",
  586. idx + 1, slot);
  587. switch (slot) {
  588. case 1:
  589. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
  590. BRDCFG1_EMI1_EN;
  591. break;
  592. case 2:
  593. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
  594. BRDCFG1_EMI1_EN;
  595. break;
  596. case 3:
  597. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
  598. BRDCFG1_EMI1_EN;
  599. break;
  600. case 5:
  601. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
  602. BRDCFG1_EMI1_EN;
  603. break;
  604. case 6:
  605. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
  606. BRDCFG1_EMI1_EN;
  607. break;
  608. case 7:
  609. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
  610. BRDCFG1_EMI1_EN;
  611. break;
  612. };
  613. if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
  614. super_hydra_mdio_set_mux(
  615. "SUPER_HYDRA_FM3_SGMII_MDIO",
  616. mdio_mux[i].mask,
  617. mdio_mux[i].val);
  618. fm_info_set_mdio(i, miiphy_get_dev_by_name(
  619. "SUPER_HYDRA_FM3_SGMII_MDIO"));
  620. } else {
  621. super_hydra_mdio_set_mux(
  622. "SUPER_HYDRA_FM2_SGMII_MDIO",
  623. mdio_mux[i].mask,
  624. mdio_mux[i].val);
  625. fm_info_set_mdio(i, miiphy_get_dev_by_name(
  626. "SUPER_HYDRA_FM2_SGMII_MDIO"));
  627. }
  628. break;
  629. case PHY_INTERFACE_MODE_RGMII:
  630. /*
  631. * FM1 DTSEC5 is routed via EC1 to the first on-board
  632. * RGMII port. FM2 DTSEC5 is routed via EC2 to the
  633. * second on-board RGMII port. The other DTSECs cannot
  634. * be routed to RGMII.
  635. */
  636. debug("FM2@DTSEC%u is RGMII at address %u\n",
  637. idx + 1, 1);
  638. fm_info_set_phy_address(i, 1);
  639. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  640. mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
  641. BRDCFG1_EMI1_EN;
  642. super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
  643. mdio_mux[i].mask, mdio_mux[i].val);
  644. fm_info_set_mdio(i,
  645. miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
  646. break;
  647. case PHY_INTERFACE_MODE_NONE:
  648. fm_info_set_phy_address(i, 0);
  649. break;
  650. default:
  651. printf("Fman2: DTSEC%u set to unknown interface %i\n",
  652. idx + 1, fm_info_get_enet_if(i));
  653. fm_info_set_phy_address(i, 0);
  654. break;
  655. }
  656. }
  657. bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
  658. set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
  659. bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
  660. set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
  661. /*
  662. * For 10G, we only support one XAUI card per Fman. If present, then we
  663. * force its routing and never touch those bits again, which removes the
  664. * need for Linux to do any muxing. This works because of the way
  665. * BRDCFG1 is defined, but it's a bit hackish.
  666. *
  667. * The PHY address for the XAUI card depends on which slot it's in. The
  668. * macros we use imply that the PHY address is based on which FM, but
  669. * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
  670. * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
  671. * check the actual slot and just use the macros as-is, even though
  672. * the P3041 and P5020 only have one Fman.
  673. */
  674. lane = serdes_get_first_lane(XAUI_FM2);
  675. if (lane >= 0) {
  676. debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
  677. mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
  678. mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
  679. super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
  680. mdio_mux[i].mask, mdio_mux[i].val);
  681. }
  682. fm_info_set_mdio(FM2_10GEC1,
  683. miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
  684. #endif
  685. cpu_eth_init(bis);
  686. #endif
  687. return pci_eth_init(bis);
  688. }