eth_hydra.c 15 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. * Author: Timur Tabi <timur@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * This file handles the board muxing between the Fman Ethernet MACs and
  9. * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
  10. * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
  11. * provided by the standard Freescale four-port SGMII riser card. The 10Gb
  12. * XGMII PHY is provided via the XAUI riser card. Since there is only one
  13. * Fman device on a P3041 and P5020, we only support one SGMII card and one
  14. * RGMII card.
  15. *
  16. * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
  17. * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
  18. * always the same (0). The value for SGMII depends on which slot the riser is
  19. * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
  20. * the value is based on which slot the XAUI is inserted in.
  21. *
  22. * The SERDES configuration is used to determine where the SGMII and XAUI cards
  23. * exist, and also which Fman MACs are routed to which PHYs. So for a given
  24. * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
  25. * to PHYs dynamically.
  26. *
  27. *
  28. * This file also updates the device tree in three ways:
  29. *
  30. * 1) The status of each virtual MDIO node that is referenced by an Ethernet
  31. * node is set to "okay".
  32. *
  33. * 2) The phy-handle property of each active Ethernet MAC node is set to the
  34. * appropriate PHY node.
  35. *
  36. * 3) The "mux value" for each virtual MDIO node is set to the correct value,
  37. * if necessary. Some virtual MDIO nodes do not have configurable mux
  38. * values, so those values are hard-coded in the DTS. On the HYDRA board,
  39. * the virtual MDIO node for the SGMII card needs to be updated.
  40. *
  41. * For all this to work, the device tree needs to have the following:
  42. *
  43. * 1) An alias for each PHY node that an Ethernet node could be routed to.
  44. *
  45. * 2) An alias for each real and virtual MDIO node that is disabled by default
  46. * and might need to be enabled, and also might need to have its mux-value
  47. * updated.
  48. */
  49. #include <common.h>
  50. #include <netdev.h>
  51. #include <asm/fsl_serdes.h>
  52. #include <fm_eth.h>
  53. #include <fsl_mdio.h>
  54. #include <malloc.h>
  55. #include <fdt_support.h>
  56. #include <fsl_dtsec.h>
  57. #include "../common/ngpixis.h"
  58. #include "../common/fman.h"
  59. #ifdef CONFIG_FMAN_ENET
  60. #define BRDCFG1_EMI1_SEL_MASK 0x78
  61. #define BRDCFG1_EMI1_SEL_SLOT1 0x10
  62. #define BRDCFG1_EMI1_SEL_SLOT2 0x20
  63. #define BRDCFG1_EMI1_SEL_SLOT5 0x30
  64. #define BRDCFG1_EMI1_SEL_SLOT6 0x40
  65. #define BRDCFG1_EMI1_SEL_SLOT7 0x50
  66. #define BRDCFG1_EMI1_SEL_RGMII 0x00
  67. #define BRDCFG1_EMI1_EN 0x08
  68. #define BRDCFG1_EMI2_SEL_MASK 0x06
  69. #define BRDCFG1_EMI2_SEL_SLOT1 0x00
  70. #define BRDCFG1_EMI2_SEL_SLOT2 0x02
  71. #define BRDCFG2_REG_GPIO_SEL 0x20
  72. #define PHY_BASE_ADDR 0x00
  73. /*
  74. * BRDCFG1 mask and value for each MAC
  75. *
  76. * This array contains the BRDCFG1 values (in mask/val format) that route the
  77. * MDIO bus to a particular RGMII or SGMII PHY.
  78. */
  79. struct {
  80. u8 mask;
  81. u8 val;
  82. } mdio_mux[NUM_FM_PORTS];
  83. /*
  84. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  85. * that the mapping must be determined dynamically, or that the lane maps to
  86. * something other than a board slot
  87. */
  88. static u8 lane_to_slot[] = {
  89. 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
  90. };
  91. /*
  92. * Set the board muxing for a given MAC
  93. *
  94. * The MDIO layer calls this function every time it wants to talk to a PHY.
  95. */
  96. void hydra_mux_mdio(u8 mask, u8 val)
  97. {
  98. clrsetbits_8(&pixis->brdcfg1, mask, val);
  99. }
  100. struct hydra_mdio {
  101. u8 mask;
  102. u8 val;
  103. struct mii_dev *realbus;
  104. };
  105. static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
  106. int regnum)
  107. {
  108. struct hydra_mdio *priv = bus->priv;
  109. hydra_mux_mdio(priv->mask, priv->val);
  110. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  111. }
  112. static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
  113. int regnum, u16 value)
  114. {
  115. struct hydra_mdio *priv = bus->priv;
  116. hydra_mux_mdio(priv->mask, priv->val);
  117. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  118. }
  119. static int hydra_mdio_reset(struct mii_dev *bus)
  120. {
  121. struct hydra_mdio *priv = bus->priv;
  122. return priv->realbus->reset(priv->realbus);
  123. }
  124. static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
  125. {
  126. struct mii_dev *bus = miiphy_get_dev_by_name(name);
  127. struct hydra_mdio *priv = bus->priv;
  128. priv->mask = mask;
  129. priv->val = val;
  130. }
  131. static int hydra_mdio_init(char *realbusname, char *fakebusname)
  132. {
  133. struct hydra_mdio *hmdio;
  134. struct mii_dev *bus = mdio_alloc();
  135. if (!bus) {
  136. printf("Failed to allocate Hydra MDIO bus\n");
  137. return -1;
  138. }
  139. hmdio = malloc(sizeof(*hmdio));
  140. if (!hmdio) {
  141. printf("Failed to allocate Hydra private data\n");
  142. free(bus);
  143. return -1;
  144. }
  145. bus->read = hydra_mdio_read;
  146. bus->write = hydra_mdio_write;
  147. bus->reset = hydra_mdio_reset;
  148. strcpy(bus->name, fakebusname);
  149. hmdio->realbus = miiphy_get_dev_by_name(realbusname);
  150. if (!hmdio->realbus) {
  151. printf("No bus with name %s\n", realbusname);
  152. free(bus);
  153. free(hmdio);
  154. return -1;
  155. }
  156. bus->priv = hmdio;
  157. return mdio_register(bus);
  158. }
  159. /*
  160. * Given an alias or a path for a node, set the mux value of that node.
  161. *
  162. * If 'alias' is not a valid alias, then it is treated as a full path to the
  163. * node. No error checking is performed.
  164. *
  165. * This function is normally called to set the fsl,hydra-mdio-muxval property
  166. * of a virtual MDIO node.
  167. */
  168. static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
  169. {
  170. const char *path = fdt_get_alias(fdt, alias);
  171. if (!path)
  172. path = alias;
  173. do_fixup_by_path(fdt, path, "reg",
  174. &mux, sizeof(mux), 1);
  175. do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
  176. &mux, sizeof(mux), 1);
  177. }
  178. /*
  179. * Given the following ...
  180. *
  181. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  182. * compatible string and 'addr' physical address)
  183. *
  184. * 2) An Fman port
  185. *
  186. * ... update the phy-handle property of the Ethernet node to point to the
  187. * right PHY. This assumes that we already know the PHY for each port. That
  188. * information is stored in mdio_mux[].
  189. *
  190. * The offset of the Fman Ethernet node is also passed in for convenience, but
  191. * it is not used, and we recalculate the offset anyway.
  192. *
  193. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  194. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  195. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  196. * and ports are the same thing.
  197. *
  198. * Note that this code would be cleaner if had a function called
  199. * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
  200. * array. That's because all we're doing is figuring out the PHY address for
  201. * a given Fman MAC and writing it to the device tree. Well, we already did
  202. * the hard work to figure that out in board_eth_init(), so it's silly to
  203. * repeat that here.
  204. */
  205. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  206. enum fm_port port, int offset)
  207. {
  208. unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
  209. char phy[16];
  210. if (port == FM1_10GEC1) {
  211. /* XAUI */
  212. int lane = serdes_get_first_lane(XAUI_FM1);
  213. if (lane >= 0) {
  214. /* The XAUI PHY is identified by the slot */
  215. sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
  216. fdt_set_phy_handle(fdt, compat, addr, phy);
  217. }
  218. return;
  219. }
  220. if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
  221. /* RGMII */
  222. /* The RGMII PHY is identified by the MAC connected to it */
  223. sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
  224. fdt_set_phy_handle(fdt, compat, addr, phy);
  225. return;
  226. }
  227. /* If it's not RGMII or XGMII, it must be SGMII */
  228. if (mux) {
  229. /* The SGMII PHY is identified by the MAC connected to it */
  230. sprintf(phy, "phy_sgmii_%x",
  231. CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
  232. fdt_set_phy_handle(fdt, compat, addr, phy);
  233. }
  234. }
  235. #define PIXIS_SW2_LANE_23_SEL 0x80
  236. #define PIXIS_SW2_LANE_45_SEL 0x40
  237. #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
  238. #define PIXIS_SW2_LANE_67_SEL_5 0x00
  239. #define PIXIS_SW2_LANE_67_SEL_6 0x20
  240. #define PIXIS_SW2_LANE_67_SEL_7 0x10
  241. #define PIXIS_SW2_LANE_8_SEL 0x08
  242. #define PIXIS_SW2_LANE_1617_SEL 0x04
  243. /*
  244. * Initialize the lane_to_slot[] array.
  245. *
  246. * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
  247. * slots is hard-coded. On the Hydra board, however, the mapping is controlled
  248. * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
  249. * initialized.
  250. */
  251. static void initialize_lane_to_slot(void)
  252. {
  253. u8 sw2 = in_8(&PIXIS_SW(2));
  254. lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
  255. lane_to_slot[3] = lane_to_slot[2];
  256. lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
  257. lane_to_slot[5] = lane_to_slot[4];
  258. switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
  259. case PIXIS_SW2_LANE_67_SEL_5:
  260. lane_to_slot[6] = 5;
  261. break;
  262. case PIXIS_SW2_LANE_67_SEL_6:
  263. lane_to_slot[6] = 6;
  264. break;
  265. case PIXIS_SW2_LANE_67_SEL_7:
  266. lane_to_slot[6] = 7;
  267. break;
  268. }
  269. lane_to_slot[7] = lane_to_slot[6];
  270. lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
  271. lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
  272. lane_to_slot[17] = lane_to_slot[16];
  273. }
  274. #endif /* #ifdef CONFIG_FMAN_ENET */
  275. /*
  276. * Configure the status for the virtual MDIO nodes
  277. *
  278. * Rather than create the virtual MDIO nodes from scratch for each active
  279. * virtual MDIO, we expect the DTS to have the nodes defined already, and we
  280. * only enable the ones that are actually active.
  281. *
  282. * We assume that the DTS already hard-codes the status for all the
  283. * virtual MDIO nodes to "disabled", so all we need to do is enable the
  284. * active ones.
  285. *
  286. * For SGMII, we also need to set the mux value in the node.
  287. */
  288. void fdt_fixup_board_enet(void *fdt)
  289. {
  290. #ifdef CONFIG_FMAN_ENET
  291. unsigned int i;
  292. int lane;
  293. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  294. int idx = i - FM1_DTSEC1;
  295. switch (fm_info_get_enet_if(i)) {
  296. case PHY_INTERFACE_MODE_SGMII:
  297. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  298. if (lane >= 0) {
  299. fdt_status_okay_by_alias(fdt, "emi1_sgmii");
  300. /* Also set the MUX value */
  301. fdt_set_mdio_mux(fdt, "emi1_sgmii",
  302. mdio_mux[i].val);
  303. }
  304. break;
  305. case PHY_INTERFACE_MODE_RGMII:
  306. fdt_status_okay_by_alias(fdt, "emi1_rgmii");
  307. break;
  308. default:
  309. break;
  310. }
  311. }
  312. lane = serdes_get_first_lane(XAUI_FM1);
  313. if (lane >= 0)
  314. fdt_status_okay_by_alias(fdt, "emi2_xgmii");
  315. #endif
  316. }
  317. int board_eth_init(bd_t *bis)
  318. {
  319. #ifdef CONFIG_FMAN_ENET
  320. struct fsl_pq_mdio_info dtsec_mdio_info;
  321. struct tgec_mdio_info tgec_mdio_info;
  322. unsigned int i, slot;
  323. int lane;
  324. struct mii_dev *bus;
  325. printf("Initializing Fman\n");
  326. initialize_lane_to_slot();
  327. /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
  328. setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
  329. memset(mdio_mux, 0, sizeof(mdio_mux));
  330. dtsec_mdio_info.regs =
  331. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  332. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  333. /* Register the real 1G MDIO bus */
  334. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  335. tgec_mdio_info.regs =
  336. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  337. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  338. /* Register the real 10G MDIO bus */
  339. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  340. /* Register the three virtual MDIO front-ends */
  341. hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
  342. hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
  343. /*
  344. * Program the DTSEC PHY addresses assuming that they are all SGMII.
  345. * For any DTSEC that's RGMII, we'll override its PHY address later.
  346. * We assume that DTSEC5 is only used for RGMII.
  347. */
  348. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  349. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  350. fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  351. fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  352. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  353. int idx = i - FM1_DTSEC1;
  354. switch (fm_info_get_enet_if(i)) {
  355. case PHY_INTERFACE_MODE_SGMII:
  356. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  357. if (lane < 0)
  358. break;
  359. slot = lane_to_slot[lane];
  360. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  361. switch (slot) {
  362. case 1:
  363. /* Always DTSEC5 on Bank 3 */
  364. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
  365. BRDCFG1_EMI1_EN;
  366. break;
  367. case 2:
  368. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
  369. BRDCFG1_EMI1_EN;
  370. break;
  371. case 5:
  372. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
  373. BRDCFG1_EMI1_EN;
  374. break;
  375. case 6:
  376. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
  377. BRDCFG1_EMI1_EN;
  378. break;
  379. case 7:
  380. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
  381. BRDCFG1_EMI1_EN;
  382. break;
  383. };
  384. hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
  385. mdio_mux[i].mask, mdio_mux[i].val);
  386. fm_info_set_mdio(i,
  387. miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
  388. break;
  389. case PHY_INTERFACE_MODE_RGMII:
  390. /*
  391. * If DTSEC4 is RGMII, then it's routed via via EC1 to
  392. * the first on-board RGMII port. If DTSEC5 is RGMII,
  393. * then it's routed via via EC2 to the second on-board
  394. * RGMII port. The other DTSECs cannot be routed to
  395. * RGMII.
  396. */
  397. fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
  398. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  399. mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
  400. BRDCFG1_EMI1_EN;
  401. hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
  402. mdio_mux[i].mask, mdio_mux[i].val);
  403. fm_info_set_mdio(i,
  404. miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
  405. break;
  406. case PHY_INTERFACE_MODE_NONE:
  407. fm_info_set_phy_address(i, 0);
  408. break;
  409. default:
  410. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  411. idx + 1, fm_info_get_enet_if(i));
  412. fm_info_set_phy_address(i, 0);
  413. break;
  414. }
  415. }
  416. bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
  417. set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
  418. /*
  419. * For 10G, we only support one XAUI card per Fman. If present, then we
  420. * force its routing and never touch those bits again, which removes the
  421. * need for Linux to do any muxing. This works because of the way
  422. * BRDCFG1 is defined, but it's a bit hackish.
  423. *
  424. * The PHY address for the XAUI card depends on which slot it's in. The
  425. * macros we use imply that the PHY address is based on which FM, but
  426. * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
  427. * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
  428. * check the actual slot and just use the macros as-is, even though
  429. * the P3041 and P5020 only have one Fman.
  430. */
  431. lane = serdes_get_first_lane(XAUI_FM1);
  432. if (lane >= 0) {
  433. slot = lane_to_slot[lane];
  434. if (slot == 1) {
  435. /* XAUI card is in slot 1 */
  436. clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
  437. BRDCFG1_EMI2_SEL_SLOT1);
  438. fm_info_set_phy_address(FM1_10GEC1,
  439. CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  440. } else {
  441. /* XAUI card is in slot 2 */
  442. clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
  443. BRDCFG1_EMI2_SEL_SLOT2);
  444. fm_info_set_phy_address(FM1_10GEC1,
  445. CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
  446. }
  447. }
  448. fm_info_set_mdio(FM1_10GEC1,
  449. miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
  450. cpu_eth_init(bis);
  451. #endif
  452. return pci_eth_init(bis);
  453. }