fec.c 23 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <malloc.h>
  9. #include <commproc.h>
  10. #include <net.h>
  11. #include <command.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #undef ET_DEBUG
  14. #if defined(CONFIG_CMD_NET) && \
  15. (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
  16. /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
  17. #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
  18. #define CONFIG_ETHER_ON_FEC1 1
  19. #endif
  20. /* define WANT_MII when MII support is required */
  21. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
  22. #define WANT_MII
  23. #else
  24. #undef WANT_MII
  25. #endif
  26. #if defined(WANT_MII)
  27. #include <miiphy.h>
  28. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  29. #error "CONFIG_MII has to be defined!"
  30. #endif
  31. #endif
  32. #if defined(CONFIG_RMII) && !defined(WANT_MII)
  33. #error RMII support is unusable without a working PHY.
  34. #endif
  35. #ifdef CONFIG_SYS_DISCOVER_PHY
  36. static int mii_discover_phy(struct eth_device *dev);
  37. #endif
  38. int fec8xx_miiphy_read(const char *devname, unsigned char addr,
  39. unsigned char reg, unsigned short *value);
  40. int fec8xx_miiphy_write(const char *devname, unsigned char addr,
  41. unsigned char reg, unsigned short value);
  42. static struct ether_fcc_info_s
  43. {
  44. int ether_index;
  45. int fecp_offset;
  46. int phy_addr;
  47. int actual_phy_addr;
  48. int initialized;
  49. }
  50. ether_fcc_info[] = {
  51. #if defined(CONFIG_ETHER_ON_FEC1)
  52. {
  53. 0,
  54. offsetof(immap_t, im_cpm.cp_fec1),
  55. #if defined(CONFIG_FEC1_PHY)
  56. CONFIG_FEC1_PHY,
  57. #else
  58. -1, /* discover */
  59. #endif
  60. -1,
  61. 0,
  62. },
  63. #endif
  64. #if defined(CONFIG_ETHER_ON_FEC2)
  65. {
  66. 1,
  67. offsetof(immap_t, im_cpm.cp_fec2),
  68. #if defined(CONFIG_FEC2_PHY)
  69. CONFIG_FEC2_PHY,
  70. #else
  71. -1,
  72. #endif
  73. -1,
  74. 0,
  75. },
  76. #endif
  77. };
  78. /* Ethernet Transmit and Receive Buffers */
  79. #define DBUF_LENGTH 1520
  80. #define TX_BUF_CNT 2
  81. #define TOUT_LOOP 100
  82. #define PKT_MAXBUF_SIZE 1518
  83. #define PKT_MINBUF_SIZE 64
  84. #define PKT_MAXBLR_SIZE 1520
  85. #ifdef __GNUC__
  86. static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
  87. #else
  88. #error txbuf must be aligned.
  89. #endif
  90. static uint rxIdx; /* index of the current RX buffer */
  91. static uint txIdx; /* index of the current TX buffer */
  92. /*
  93. * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  94. * immr->udata_bd address on Dual-Port RAM
  95. * Provide for Double Buffering
  96. */
  97. typedef volatile struct CommonBufferDescriptor {
  98. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  99. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  100. } RTXBD;
  101. static RTXBD *rtx = NULL;
  102. static int fec_send(struct eth_device *dev, void *packet, int length);
  103. static int fec_recv(struct eth_device* dev);
  104. static int fec_init(struct eth_device* dev, bd_t * bd);
  105. static void fec_halt(struct eth_device* dev);
  106. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  107. static void __mii_init(void);
  108. #endif
  109. int fec_initialize(bd_t *bis)
  110. {
  111. struct eth_device* dev;
  112. struct ether_fcc_info_s *efis;
  113. int i;
  114. for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
  115. dev = malloc(sizeof(*dev));
  116. if (dev == NULL)
  117. hang();
  118. memset(dev, 0, sizeof(*dev));
  119. /* for FEC1 make sure that the name of the interface is the same
  120. as the old one for compatibility reasons */
  121. if (i == 0) {
  122. strcpy(dev->name, "FEC");
  123. } else {
  124. sprintf (dev->name, "FEC%d",
  125. ether_fcc_info[i].ether_index + 1);
  126. }
  127. efis = &ether_fcc_info[i];
  128. /*
  129. * reset actual phy addr
  130. */
  131. efis->actual_phy_addr = -1;
  132. dev->priv = efis;
  133. dev->init = fec_init;
  134. dev->halt = fec_halt;
  135. dev->send = fec_send;
  136. dev->recv = fec_recv;
  137. eth_register(dev);
  138. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  139. miiphy_register(dev->name,
  140. fec8xx_miiphy_read, fec8xx_miiphy_write);
  141. #endif
  142. }
  143. return 1;
  144. }
  145. static int fec_send(struct eth_device *dev, void *packet, int length)
  146. {
  147. int j, rc;
  148. struct ether_fcc_info_s *efis = dev->priv;
  149. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  150. /* section 16.9.23.3
  151. * Wait for ready
  152. */
  153. j = 0;
  154. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
  155. udelay(1);
  156. j++;
  157. }
  158. if (j>=TOUT_LOOP) {
  159. printf("TX not ready\n");
  160. }
  161. rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
  162. rtx->txbd[txIdx].cbd_datlen = length;
  163. rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
  164. __asm__ ("eieio");
  165. /* Activate transmit Buffer Descriptor polling */
  166. fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
  167. j = 0;
  168. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
  169. udelay(1);
  170. j++;
  171. }
  172. if (j>=TOUT_LOOP) {
  173. printf("TX timeout\n");
  174. }
  175. #ifdef ET_DEBUG
  176. printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
  177. __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
  178. (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
  179. #endif
  180. /* return only status bits */;
  181. rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
  182. txIdx = (txIdx + 1) % TX_BUF_CNT;
  183. return rc;
  184. }
  185. static int fec_recv (struct eth_device *dev)
  186. {
  187. struct ether_fcc_info_s *efis = dev->priv;
  188. volatile fec_t *fecp =
  189. (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
  190. int length;
  191. for (;;) {
  192. /* section 16.9.23.2 */
  193. if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  194. length = -1;
  195. break; /* nothing received - leave for() loop */
  196. }
  197. length = rtx->rxbd[rxIdx].cbd_datlen;
  198. if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
  199. #ifdef ET_DEBUG
  200. printf ("%s[%d] err: %x\n",
  201. __FUNCTION__, __LINE__,
  202. rtx->rxbd[rxIdx].cbd_sc);
  203. #endif
  204. } else {
  205. uchar *rx = net_rx_packets[rxIdx];
  206. length -= 4;
  207. #if defined(CONFIG_CMD_CDP)
  208. if ((rx[0] & 1) != 0 &&
  209. memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
  210. !is_cdp_packet((uchar *)rx))
  211. rx = NULL;
  212. #endif
  213. /*
  214. * Pass the packet up to the protocol layers.
  215. */
  216. if (rx != NULL)
  217. net_process_received_packet(rx, length);
  218. }
  219. /* Give the buffer back to the FEC. */
  220. rtx->rxbd[rxIdx].cbd_datlen = 0;
  221. /* wrap around buffer index when necessary */
  222. if ((rxIdx + 1) >= PKTBUFSRX) {
  223. rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
  224. (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  225. rxIdx = 0;
  226. } else {
  227. rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  228. rxIdx++;
  229. }
  230. __asm__ ("eieio");
  231. /* Try to fill Buffer Descriptors */
  232. fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
  233. }
  234. return length;
  235. }
  236. /**************************************************************
  237. *
  238. * FEC Ethernet Initialization Routine
  239. *
  240. *************************************************************/
  241. #define FEC_ECNTRL_PINMUX 0x00000004
  242. #define FEC_ECNTRL_ETHER_EN 0x00000002
  243. #define FEC_ECNTRL_RESET 0x00000001
  244. #define FEC_RCNTRL_BC_REJ 0x00000010
  245. #define FEC_RCNTRL_PROM 0x00000008
  246. #define FEC_RCNTRL_MII_MODE 0x00000004
  247. #define FEC_RCNTRL_DRT 0x00000002
  248. #define FEC_RCNTRL_LOOP 0x00000001
  249. #define FEC_TCNTRL_FDEN 0x00000004
  250. #define FEC_TCNTRL_HBC 0x00000002
  251. #define FEC_TCNTRL_GTS 0x00000001
  252. #define FEC_RESET_DELAY 50
  253. #if defined(CONFIG_RMII)
  254. static inline void fec_10Mbps(struct eth_device *dev)
  255. {
  256. struct ether_fcc_info_s *efis = dev->priv;
  257. int fecidx = efis->ether_index;
  258. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  259. if ((unsigned int)fecidx >= 2)
  260. hang();
  261. ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
  262. }
  263. static inline void fec_100Mbps(struct eth_device *dev)
  264. {
  265. struct ether_fcc_info_s *efis = dev->priv;
  266. int fecidx = efis->ether_index;
  267. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  268. if ((unsigned int)fecidx >= 2)
  269. hang();
  270. ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
  271. }
  272. #endif
  273. static inline void fec_full_duplex(struct eth_device *dev)
  274. {
  275. struct ether_fcc_info_s *efis = dev->priv;
  276. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  277. fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
  278. fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
  279. }
  280. static inline void fec_half_duplex(struct eth_device *dev)
  281. {
  282. struct ether_fcc_info_s *efis = dev->priv;
  283. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  284. fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
  285. fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
  286. }
  287. static void fec_pin_init(int fecidx)
  288. {
  289. bd_t *bd = gd->bd;
  290. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  291. /*
  292. * Set MII speed to 2.5 MHz or slightly below.
  293. *
  294. * According to the MPC860T (Rev. D) Fast ethernet controller user
  295. * manual (6.2.14),
  296. * the MII management interface clock must be less than or equal
  297. * to 2.5 MHz.
  298. * This MDC frequency is equal to system clock / (2 * MII_SPEED).
  299. * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
  300. *
  301. * All MII configuration is done via FEC1 registers:
  302. */
  303. immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
  304. #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
  305. /* use MDC for MII */
  306. immr->im_ioport.iop_pdpar |= 0x0080;
  307. immr->im_ioport.iop_pddir &= ~0x0080;
  308. #endif
  309. if (fecidx == 0) {
  310. #if defined(CONFIG_ETHER_ON_FEC1)
  311. #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
  312. #if !defined(CONFIG_RMII)
  313. immr->im_ioport.iop_papar |= 0xf830;
  314. immr->im_ioport.iop_padir |= 0x0830;
  315. immr->im_ioport.iop_padir &= ~0xf000;
  316. immr->im_cpm.cp_pbpar |= 0x00001001;
  317. immr->im_cpm.cp_pbdir &= ~0x00001001;
  318. immr->im_ioport.iop_pcpar |= 0x000c;
  319. immr->im_ioport.iop_pcdir &= ~0x000c;
  320. immr->im_cpm.cp_pepar |= 0x00000003;
  321. immr->im_cpm.cp_pedir |= 0x00000003;
  322. immr->im_cpm.cp_peso &= ~0x00000003;
  323. immr->im_cpm.cp_cptr &= ~0x00000100;
  324. #else
  325. #if !defined(CONFIG_FEC1_PHY_NORXERR)
  326. immr->im_ioport.iop_papar |= 0x1000;
  327. immr->im_ioport.iop_padir &= ~0x1000;
  328. #endif
  329. immr->im_ioport.iop_papar |= 0xe810;
  330. immr->im_ioport.iop_padir |= 0x0810;
  331. immr->im_ioport.iop_padir &= ~0xe000;
  332. immr->im_cpm.cp_pbpar |= 0x00000001;
  333. immr->im_cpm.cp_pbdir &= ~0x00000001;
  334. immr->im_cpm.cp_cptr |= 0x00000100;
  335. immr->im_cpm.cp_cptr &= ~0x00000050;
  336. #endif /* !CONFIG_RMII */
  337. #else
  338. /*
  339. * Configure all of port D for MII.
  340. */
  341. immr->im_ioport.iop_pdpar = 0x1fff;
  342. /*
  343. * Bits moved from Rev. D onward
  344. */
  345. if ((get_immr(0) & 0xffff) < 0x0501)
  346. immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
  347. else
  348. immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
  349. #endif
  350. #endif /* CONFIG_ETHER_ON_FEC1 */
  351. } else if (fecidx == 1) {
  352. #if defined(CONFIG_ETHER_ON_FEC2)
  353. #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
  354. #if !defined(CONFIG_RMII)
  355. immr->im_cpm.cp_pepar |= 0x0003fffc;
  356. immr->im_cpm.cp_pedir |= 0x0003fffc;
  357. immr->im_cpm.cp_peso &= ~0x000087fc;
  358. immr->im_cpm.cp_peso |= 0x00037800;
  359. immr->im_cpm.cp_cptr &= ~0x00000080;
  360. #else
  361. #if !defined(CONFIG_FEC2_PHY_NORXERR)
  362. immr->im_cpm.cp_pepar |= 0x00000010;
  363. immr->im_cpm.cp_pedir |= 0x00000010;
  364. immr->im_cpm.cp_peso &= ~0x00000010;
  365. #endif
  366. immr->im_cpm.cp_pepar |= 0x00039620;
  367. immr->im_cpm.cp_pedir |= 0x00039620;
  368. immr->im_cpm.cp_peso |= 0x00031000;
  369. immr->im_cpm.cp_peso &= ~0x00008620;
  370. immr->im_cpm.cp_cptr |= 0x00000080;
  371. immr->im_cpm.cp_cptr &= ~0x00000028;
  372. #endif /* CONFIG_RMII */
  373. #endif /* CONFIG_MPC885_FAMILY */
  374. #endif /* CONFIG_ETHER_ON_FEC2 */
  375. }
  376. }
  377. static int fec_reset(volatile fec_t *fecp)
  378. {
  379. int i;
  380. /* Whack a reset.
  381. * A delay is required between a reset of the FEC block and
  382. * initialization of other FEC registers because the reset takes
  383. * some time to complete. If you don't delay, subsequent writes
  384. * to FEC registers might get killed by the reset routine which is
  385. * still in progress.
  386. */
  387. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
  388. for (i = 0;
  389. (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
  390. ++i) {
  391. udelay (1);
  392. }
  393. if (i == FEC_RESET_DELAY)
  394. return -1;
  395. return 0;
  396. }
  397. static int fec_init (struct eth_device *dev, bd_t * bd)
  398. {
  399. struct ether_fcc_info_s *efis = dev->priv;
  400. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  401. volatile fec_t *fecp =
  402. (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
  403. int i;
  404. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  405. /* the MII interface is connected to FEC1
  406. * so for the miiphy_xxx function to work we must
  407. * call mii_init since fec_halt messes the thing up
  408. */
  409. if (efis->ether_index != 0)
  410. __mii_init();
  411. #endif
  412. if (fec_reset(fecp) < 0)
  413. printf ("FEC_RESET_DELAY timeout\n");
  414. /* We use strictly polling mode only
  415. */
  416. fecp->fec_imask = 0;
  417. /* Clear any pending interrupt
  418. */
  419. fecp->fec_ievent = 0xffc0;
  420. /* No need to set the IVEC register */
  421. /* Set station address
  422. */
  423. #define ea dev->enetaddr
  424. fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  425. fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
  426. #undef ea
  427. #if defined(CONFIG_CMD_CDP)
  428. /*
  429. * Turn on multicast address hash table
  430. */
  431. fecp->fec_hash_table_high = 0xffffffff;
  432. fecp->fec_hash_table_low = 0xffffffff;
  433. #else
  434. /* Clear multicast address hash table
  435. */
  436. fecp->fec_hash_table_high = 0;
  437. fecp->fec_hash_table_low = 0;
  438. #endif
  439. /* Set maximum receive buffer size.
  440. */
  441. fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
  442. /* Set maximum frame length
  443. */
  444. fecp->fec_r_hash = PKT_MAXBUF_SIZE;
  445. /*
  446. * Setup Buffers and Buffer Desriptors
  447. */
  448. rxIdx = 0;
  449. txIdx = 0;
  450. if (!rtx) {
  451. #ifdef CONFIG_SYS_ALLOC_DPRAM
  452. rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
  453. dpram_alloc_align (sizeof (RTXBD), 8));
  454. #else
  455. rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
  456. #endif
  457. }
  458. /*
  459. * Setup Receiver Buffer Descriptors (13.14.24.18)
  460. * Settings:
  461. * Empty, Wrap
  462. */
  463. for (i = 0; i < PKTBUFSRX; i++) {
  464. rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  465. rtx->rxbd[i].cbd_datlen = 0; /* Reset */
  466. rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  467. }
  468. rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  469. /*
  470. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  471. * Settings:
  472. * Last, Tx CRC
  473. */
  474. for (i = 0; i < TX_BUF_CNT; i++) {
  475. rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
  476. rtx->txbd[i].cbd_datlen = 0; /* Reset */
  477. rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
  478. }
  479. rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  480. /* Set receive and transmit descriptor base
  481. */
  482. fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
  483. fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
  484. /* Enable MII mode
  485. */
  486. #if 0 /* Full duplex mode */
  487. fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
  488. fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
  489. #else /* Half duplex mode */
  490. fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
  491. fecp->fec_x_cntrl = 0;
  492. #endif
  493. /* Enable big endian and don't care about SDMA FC.
  494. */
  495. fecp->fec_fun_code = 0x78000000;
  496. /*
  497. * Setup the pin configuration of the FEC
  498. */
  499. fec_pin_init (efis->ether_index);
  500. rxIdx = 0;
  501. txIdx = 0;
  502. /*
  503. * Now enable the transmit and receive processing
  504. */
  505. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
  506. if (efis->phy_addr == -1) {
  507. #ifdef CONFIG_SYS_DISCOVER_PHY
  508. /*
  509. * wait for the PHY to wake up after reset
  510. */
  511. efis->actual_phy_addr = mii_discover_phy (dev);
  512. if (efis->actual_phy_addr == -1) {
  513. printf ("Unable to discover phy!\n");
  514. return -1;
  515. }
  516. #else
  517. efis->actual_phy_addr = -1;
  518. #endif
  519. } else {
  520. efis->actual_phy_addr = efis->phy_addr;
  521. }
  522. #if defined(CONFIG_MII) && defined(CONFIG_RMII)
  523. /*
  524. * adapt the RMII speed to the speed of the phy
  525. */
  526. if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
  527. fec_100Mbps (dev);
  528. } else {
  529. fec_10Mbps (dev);
  530. }
  531. #endif
  532. #if defined(CONFIG_MII)
  533. /*
  534. * adapt to the half/full speed settings
  535. */
  536. if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
  537. fec_full_duplex (dev);
  538. } else {
  539. fec_half_duplex (dev);
  540. }
  541. #endif
  542. /* And last, try to fill Rx Buffer Descriptors */
  543. fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
  544. efis->initialized = 1;
  545. return 0;
  546. }
  547. static void fec_halt(struct eth_device* dev)
  548. {
  549. struct ether_fcc_info_s *efis = dev->priv;
  550. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  551. int i;
  552. /* avoid halt if initialized; mii gets stuck otherwise */
  553. if (!efis->initialized)
  554. return;
  555. /* Whack a reset.
  556. * A delay is required between a reset of the FEC block and
  557. * initialization of other FEC registers because the reset takes
  558. * some time to complete. If you don't delay, subsequent writes
  559. * to FEC registers might get killed by the reset routine which is
  560. * still in progress.
  561. */
  562. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
  563. for (i = 0;
  564. (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
  565. ++i) {
  566. udelay (1);
  567. }
  568. if (i == FEC_RESET_DELAY) {
  569. printf ("FEC_RESET_DELAY timeout\n");
  570. return;
  571. }
  572. efis->initialized = 0;
  573. }
  574. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  575. /* Make MII read/write commands for the FEC.
  576. */
  577. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  578. (REG & 0x1f) << 18))
  579. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  580. (REG & 0x1f) << 18) | \
  581. (VAL & 0xffff))
  582. /* Interrupt events/masks.
  583. */
  584. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  585. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  586. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  587. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  588. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  589. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  590. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  591. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  592. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  593. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  594. /* PHY identification
  595. */
  596. #define PHY_ID_LXT970 0x78100000 /* LXT970 */
  597. #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
  598. #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
  599. #define PHY_ID_QS6612 0x01814400 /* QS6612 */
  600. #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
  601. #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
  602. #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
  603. #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
  604. #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
  605. /* send command to phy using mii, wait for result */
  606. static uint
  607. mii_send(uint mii_cmd)
  608. {
  609. uint mii_reply;
  610. volatile fec_t *ep;
  611. int cnt;
  612. ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
  613. ep->fec_mii_data = mii_cmd; /* command to phy */
  614. /* wait for mii complete */
  615. cnt = 0;
  616. while (!(ep->fec_ievent & FEC_ENET_MII)) {
  617. if (++cnt > 1000) {
  618. printf("mii_send STUCK!\n");
  619. break;
  620. }
  621. }
  622. mii_reply = ep->fec_mii_data; /* result from phy */
  623. ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
  624. #if 0
  625. printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
  626. __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
  627. #endif
  628. return (mii_reply & 0xffff); /* data read from phy */
  629. }
  630. #endif
  631. #if defined(CONFIG_SYS_DISCOVER_PHY)
  632. static int mii_discover_phy(struct eth_device *dev)
  633. {
  634. #define MAX_PHY_PASSES 11
  635. uint phyno;
  636. int pass;
  637. uint phytype;
  638. int phyaddr;
  639. phyaddr = -1; /* didn't find a PHY yet */
  640. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  641. if (pass > 1) {
  642. /* PHY may need more time to recover from reset.
  643. * The LXT970 needs 50ms typical, no maximum is
  644. * specified, so wait 10ms before try again.
  645. * With 11 passes this gives it 100ms to wake up.
  646. */
  647. udelay(10000); /* wait 10ms */
  648. }
  649. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  650. phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
  651. #ifdef ET_DEBUG
  652. printf("PHY type 0x%x pass %d type ", phytype, pass);
  653. #endif
  654. if (phytype != 0xffff) {
  655. phyaddr = phyno;
  656. phytype |= mii_send(mk_mii_read(phyno,
  657. MII_PHYSID1)) << 16;
  658. #ifdef ET_DEBUG
  659. printf("PHY @ 0x%x pass %d type ",phyno,pass);
  660. switch (phytype & 0xfffffff0) {
  661. case PHY_ID_LXT970:
  662. printf("LXT970\n");
  663. break;
  664. case PHY_ID_LXT971:
  665. printf("LXT971\n");
  666. break;
  667. case PHY_ID_82555:
  668. printf("82555\n");
  669. break;
  670. case PHY_ID_QS6612:
  671. printf("QS6612\n");
  672. break;
  673. case PHY_ID_AMD79C784:
  674. printf("AMD79C784\n");
  675. break;
  676. case PHY_ID_LSI80225B:
  677. printf("LSI L80225/B\n");
  678. break;
  679. case PHY_ID_DM9161:
  680. printf("Davicom DM9161\n");
  681. break;
  682. case PHY_ID_KSM8995M:
  683. printf("MICREL KS8995M\n");
  684. break;
  685. default:
  686. printf("0x%08x\n", phytype);
  687. break;
  688. }
  689. #endif
  690. }
  691. }
  692. }
  693. if (phyaddr < 0) {
  694. printf("No PHY device found.\n");
  695. }
  696. return phyaddr;
  697. }
  698. #endif /* CONFIG_SYS_DISCOVER_PHY */
  699. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
  700. /****************************************************************************
  701. * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
  702. * This function is a subset of eth_init
  703. ****************************************************************************
  704. */
  705. static void __mii_init(void)
  706. {
  707. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  708. volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
  709. if (fec_reset(fecp) < 0)
  710. printf ("FEC_RESET_DELAY timeout\n");
  711. /* We use strictly polling mode only
  712. */
  713. fecp->fec_imask = 0;
  714. /* Clear any pending interrupt
  715. */
  716. fecp->fec_ievent = 0xffc0;
  717. /* Now enable the transmit and receive processing
  718. */
  719. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
  720. }
  721. void mii_init (void)
  722. {
  723. int i;
  724. __mii_init();
  725. /* Setup the pin configuration of the FEC(s)
  726. */
  727. for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
  728. fec_pin_init(ether_fcc_info[i].ether_index);
  729. }
  730. /*****************************************************************************
  731. * Read and write a MII PHY register, routines used by MII Utilities
  732. *
  733. * FIXME: These routines are expected to return 0 on success, but mii_send
  734. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  735. * no PHY connected...
  736. * For now always return 0.
  737. * FIXME: These routines only work after calling eth_init() at least once!
  738. * Otherwise they hang in mii_send() !!! Sorry!
  739. *****************************************************************************/
  740. int fec8xx_miiphy_read(const char *devname, unsigned char addr,
  741. unsigned char reg, unsigned short *value)
  742. {
  743. short rdreg; /* register working value */
  744. #ifdef MII_DEBUG
  745. printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
  746. #endif
  747. rdreg = mii_send(mk_mii_read(addr, reg));
  748. *value = rdreg;
  749. #ifdef MII_DEBUG
  750. printf ("0x%04x\n", *value);
  751. #endif
  752. return 0;
  753. }
  754. int fec8xx_miiphy_write(const char *devname, unsigned char addr,
  755. unsigned char reg, unsigned short value)
  756. {
  757. #ifdef MII_DEBUG
  758. printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
  759. #endif
  760. (void)mii_send(mk_mii_write(addr, reg, value));
  761. #ifdef MII_DEBUG
  762. printf ("0x%04x\n", value);
  763. #endif
  764. return 0;
  765. }
  766. #endif
  767. #endif