pcie_layerscape_gen4.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2018-2019 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <pci.h>
  11. #include <asm/io.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <dm.h>
  15. #include <linux/sizes.h>
  16. #include "pcie_layerscape_gen4.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. LIST_HEAD(ls_pcie_g4_list);
  19. static u64 bar_size[4] = {
  20. PCIE_BAR0_SIZE,
  21. PCIE_BAR1_SIZE,
  22. PCIE_BAR2_SIZE,
  23. PCIE_BAR4_SIZE
  24. };
  25. static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
  26. {
  27. u32 state;
  28. state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
  29. return state;
  30. }
  31. static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
  32. {
  33. int ltssm;
  34. ltssm = ls_pcie_g4_ltssm(pcie);
  35. if (ltssm != LTSSM_PCIE_L0)
  36. return 0;
  37. return 1;
  38. }
  39. static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
  40. {
  41. ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
  42. }
  43. static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
  44. {
  45. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
  46. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
  47. }
  48. static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
  49. int type, u64 phys, u64 bus_addr,
  50. pci_size_t size)
  51. {
  52. u32 val;
  53. u32 size_h, size_l;
  54. if (idx >= PAB_WINS_NUM)
  55. return -EINVAL;
  56. size_h = upper_32_bits(~(size - 1));
  57. size_l = lower_32_bits(~(size - 1));
  58. val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
  59. val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
  60. (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
  61. AXI_AMAP_CTRL_EN);
  62. val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
  63. ((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
  64. AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
  65. ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
  66. ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
  67. ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
  68. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
  69. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
  70. ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
  71. return 0;
  72. }
  73. static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
  74. int type, u64 phys, u64 bus_addr,
  75. pci_size_t size)
  76. {
  77. u32 val;
  78. pci_size_t win_size = ~(size - 1);
  79. val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
  80. val &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);
  81. val &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);
  82. val = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));
  83. val = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));
  84. ccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),
  85. val | lower_32_bits(win_size));
  86. ccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));
  87. ccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));
  88. ccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));
  89. ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
  90. ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
  91. return 0;
  92. }
  93. static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)
  94. {
  95. int i;
  96. for (i = 0; i < wins; i++) {
  97. debug("APIO Win%d:\n", i);
  98. debug("\tLOWER PHYS: 0x%08x\n",
  99. ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));
  100. debug("\tUPPER PHYS: 0x%08x\n",
  101. ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));
  102. debug("\tLOWER BUS: 0x%08x\n",
  103. ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));
  104. debug("\tUPPER BUS: 0x%08x\n",
  105. ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));
  106. debug("\tSIZE: 0x%08x\n",
  107. ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &
  108. (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));
  109. debug("\tEXT_SIZE: 0x%08x\n",
  110. ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));
  111. debug("\tPARAM: 0x%08x\n",
  112. ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));
  113. debug("\tCTRL: 0x%08x\n",
  114. ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));
  115. }
  116. }
  117. static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)
  118. {
  119. struct pci_region *io, *mem, *pref;
  120. int idx = 1;
  121. /* INBOUND WIN */
  122. ls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);
  123. /* OUTBOUND WIN 0: CFG */
  124. ls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,
  125. pcie->cfg_res.start, 0,
  126. fdt_resource_size(&pcie->cfg_res));
  127. pci_get_regions(pcie->bus, &io, &mem, &pref);
  128. if (io)
  129. /* OUTBOUND WIN: IO */
  130. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,
  131. io->phys_start, io->bus_start,
  132. io->size);
  133. if (mem)
  134. /* OUTBOUND WIN: MEM */
  135. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
  136. mem->phys_start, mem->bus_start,
  137. mem->size);
  138. if (pref)
  139. /* OUTBOUND WIN: perf MEM */
  140. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
  141. pref->phys_start, pref->bus_start,
  142. pref->size);
  143. ls_pcie_g4_dump_wins(pcie, idx);
  144. }
  145. /* Return 0 if the address is valid, -errno if not valid */
  146. static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)
  147. {
  148. struct udevice *bus = pcie->bus;
  149. if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
  150. return -ENODEV;
  151. if (!pcie->enabled)
  152. return -ENXIO;
  153. if (PCI_BUS(bdf) < bus->seq)
  154. return -EINVAL;
  155. if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_g4_link_up(pcie)))
  156. return -EINVAL;
  157. if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
  158. return -EINVAL;
  159. return 0;
  160. }
  161. void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,
  162. int offset)
  163. {
  164. struct udevice *bus = pcie->bus;
  165. u32 target;
  166. if (PCI_BUS(bdf) == bus->seq) {
  167. if (offset < INDIRECT_ADDR_BNDRY) {
  168. ccsr_set_page(pcie, 0);
  169. return pcie->ccsr + offset;
  170. }
  171. ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
  172. return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);
  173. }
  174. target = PAB_TARGET_BUS(PCI_BUS(bdf) - bus->seq) |
  175. PAB_TARGET_DEV(PCI_DEV(bdf)) |
  176. PAB_TARGET_FUNC(PCI_FUNC(bdf));
  177. ls_pcie_g4_cfg_set_target(pcie, target);
  178. return pcie->cfg + offset;
  179. }
  180. static int ls_pcie_g4_read_config(const struct udevice *bus, pci_dev_t bdf,
  181. uint offset, ulong *valuep,
  182. enum pci_size_t size)
  183. {
  184. struct ls_pcie_g4 *pcie = dev_get_priv(bus);
  185. void *address;
  186. int ret = 0;
  187. if (ls_pcie_g4_addr_valid(pcie, bdf)) {
  188. *valuep = pci_get_ff(size);
  189. return 0;
  190. }
  191. address = ls_pcie_g4_conf_address(pcie, bdf, offset);
  192. switch (size) {
  193. case PCI_SIZE_8:
  194. *valuep = readb(address);
  195. break;
  196. case PCI_SIZE_16:
  197. *valuep = readw(address);
  198. break;
  199. case PCI_SIZE_32:
  200. *valuep = readl(address);
  201. break;
  202. default:
  203. ret = -EINVAL;
  204. break;
  205. }
  206. return ret;
  207. }
  208. static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,
  209. uint offset, ulong value,
  210. enum pci_size_t size)
  211. {
  212. struct ls_pcie_g4 *pcie = dev_get_priv(bus);
  213. void *address;
  214. if (ls_pcie_g4_addr_valid(pcie, bdf))
  215. return 0;
  216. address = ls_pcie_g4_conf_address(pcie, bdf, offset);
  217. switch (size) {
  218. case PCI_SIZE_8:
  219. writeb(value, address);
  220. return 0;
  221. case PCI_SIZE_16:
  222. writew(value, address);
  223. return 0;
  224. case PCI_SIZE_32:
  225. writel(value, address);
  226. return 0;
  227. default:
  228. return -EINVAL;
  229. }
  230. }
  231. static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
  232. {
  233. u32 val;
  234. /* Fix class code */
  235. val = ccsr_readl(pcie, GPEX_CLASSCODE);
  236. val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
  237. val |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;
  238. ccsr_writel(pcie, GPEX_CLASSCODE, val);
  239. /* Enable APIO and Memory/IO/CFG Wins */
  240. val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
  241. val |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;
  242. ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
  243. ls_pcie_g4_setup_wins(pcie);
  244. pcie->stream_id_cur = 0;
  245. }
  246. static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
  247. int bar, u64 phys)
  248. {
  249. u32 val;
  250. /* PF BAR1 is for MSI-X and only need to enable */
  251. if (bar == 1) {
  252. ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
  253. return;
  254. }
  255. val = upper_32_bits(phys);
  256. ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
  257. val = lower_32_bits(phys) | BAR_AMAP_EN;
  258. ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
  259. }
  260. static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
  261. {
  262. u64 phys;
  263. int bar;
  264. u32 val;
  265. if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
  266. return;
  267. phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
  268. for (bar = 0; bar < PF_BAR_NUM; bar++) {
  269. ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
  270. phys += PCIE_BAR_SIZE;
  271. }
  272. /* OUTBOUND: map MEM */
  273. ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
  274. pcie->cfg_res.start +
  275. CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
  276. CONFIG_SYS_PCI_MEMORY_SIZE);
  277. val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
  278. val &= ~FUNC_NUM_PCIE_MASK;
  279. val |= pf;
  280. ccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);
  281. }
  282. static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,
  283. int bar, bool vf_bar, bool enable)
  284. {
  285. u32 val;
  286. u32 bar_pos = BAR_POS(bar, pf, vf_bar);
  287. val = ccsr_readl(pcie, GPEX_BAR_ENABLE);
  288. if (enable)
  289. val |= 1 << bar_pos;
  290. else
  291. val &= ~(1 << bar_pos);
  292. ccsr_writel(pcie, GPEX_BAR_ENABLE, val);
  293. }
  294. static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
  295. int bar, bool vf_bar, u64 size)
  296. {
  297. u32 bar_pos = BAR_POS(bar, pf, vf_bar);
  298. u32 mask_l = lower_32_bits(~(size - 1));
  299. u32 mask_h = upper_32_bits(~(size - 1));
  300. ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
  301. ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
  302. ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
  303. }
  304. static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,
  305. int bar, bool vf_bar, u64 size)
  306. {
  307. bool en = size ? true : false;
  308. ls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);
  309. ls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);
  310. }
  311. static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)
  312. {
  313. int bar;
  314. /* Setup PF BARs */
  315. for (bar = 0; bar < PF_BAR_NUM; bar++)
  316. ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);
  317. if (!pcie->sriov_support)
  318. return;
  319. /* Setup VF BARs */
  320. for (bar = 0; bar < VF_BAR_NUM; bar++)
  321. ls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);
  322. }
  323. static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)
  324. {
  325. unsigned int val;
  326. val = ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));
  327. val &= ~(TTL_VF_MASK << TTL_VF_SHIFT);
  328. val |= PCIE_VF_NUM << TTL_VF_SHIFT;
  329. val &= ~(INI_VF_MASK << INI_VF_SHIFT);
  330. val |= PCIE_VF_NUM << INI_VF_SHIFT;
  331. ccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);
  332. val = ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);
  333. val += PCIE_VF_NUM * pf - pf;
  334. ccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);
  335. }
  336. static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)
  337. {
  338. u32 pf, sriov;
  339. u32 val;
  340. int i;
  341. /* Enable APIO and Memory Win */
  342. val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
  343. val |= APIO_EN | MEM_WIN_EN;
  344. ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
  345. sriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);
  346. if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
  347. pcie->sriov_support = 1;
  348. pf = pcie->sriov_support ? PCIE_PF_NUM : 1;
  349. for (i = 0; i < pf; i++) {
  350. ls_pcie_g4_ep_setup_bars(pcie, i);
  351. ls_pcie_g4_ep_setup_wins(pcie, i);
  352. if (pcie->sriov_support)
  353. ls_pcie_g4_set_sriov(pcie, i);
  354. }
  355. ls_pcie_g4_ep_enable_cfg(pcie);
  356. ls_pcie_g4_dump_wins(pcie, pf);
  357. }
  358. static int ls_pcie_g4_probe(struct udevice *dev)
  359. {
  360. struct ls_pcie_g4 *pcie = dev_get_priv(dev);
  361. const void *fdt = gd->fdt_blob;
  362. int node = dev_of_offset(dev);
  363. u32 link_ctrl_sta;
  364. u32 val;
  365. int ret;
  366. pcie->bus = dev;
  367. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  368. "ccsr", &pcie->ccsr_res);
  369. if (ret) {
  370. printf("ls-pcie-g4: resource \"ccsr\" not found\n");
  371. return ret;
  372. }
  373. pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /
  374. PCIE_CCSR_SIZE;
  375. list_add(&pcie->list, &ls_pcie_g4_list);
  376. pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
  377. if (!pcie->enabled) {
  378. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  379. return 0;
  380. }
  381. pcie->ccsr = map_physmem(pcie->ccsr_res.start,
  382. fdt_resource_size(&pcie->ccsr_res),
  383. MAP_NOCACHE);
  384. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  385. "config", &pcie->cfg_res);
  386. if (ret) {
  387. printf("%s: resource \"config\" not found\n", dev->name);
  388. return ret;
  389. }
  390. pcie->cfg = map_physmem(pcie->cfg_res.start,
  391. fdt_resource_size(&pcie->cfg_res),
  392. MAP_NOCACHE);
  393. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  394. "lut", &pcie->lut_res);
  395. if (ret) {
  396. printf("ls-pcie-g4: resource \"lut\" not found\n");
  397. return ret;
  398. }
  399. pcie->lut = map_physmem(pcie->lut_res.start,
  400. fdt_resource_size(&pcie->lut_res),
  401. MAP_NOCACHE);
  402. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  403. "pf_ctrl", &pcie->pf_ctrl_res);
  404. if (ret) {
  405. printf("ls-pcie-g4: resource \"pf_ctrl\" not found\n");
  406. return ret;
  407. }
  408. pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,
  409. fdt_resource_size(&pcie->pf_ctrl_res),
  410. MAP_NOCACHE);
  411. pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
  412. debug("%s ccsr:%lx, cfg:0x%lx, big-endian:%d\n",
  413. dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
  414. pcie->big_endian);
  415. pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
  416. if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
  417. printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
  418. ls_pcie_g4_setup_ep(pcie);
  419. } else {
  420. printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
  421. ls_pcie_g4_setup_ctrl(pcie);
  422. }
  423. /* Enable Amba & PEX PIO */
  424. val = ccsr_readl(pcie, PAB_CTRL);
  425. val |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;
  426. ccsr_writel(pcie, PAB_CTRL, val);
  427. val = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));
  428. val |= PPIO_EN;
  429. ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
  430. if (!ls_pcie_g4_link_up(pcie)) {
  431. /* Let the user know there's no PCIe link */
  432. printf(": no link\n");
  433. return 0;
  434. }
  435. /* Print the negotiated PCIe link width */
  436. link_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);
  437. printf(": x%d gen%d\n",
  438. (link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),
  439. (link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);
  440. return 0;
  441. }
  442. static const struct dm_pci_ops ls_pcie_g4_ops = {
  443. .read_config = ls_pcie_g4_read_config,
  444. .write_config = ls_pcie_g4_write_config,
  445. };
  446. static const struct udevice_id ls_pcie_g4_ids[] = {
  447. { .compatible = "fsl,lx2160a-pcie" },
  448. { }
  449. };
  450. U_BOOT_DRIVER(pcie_layerscape_gen4) = {
  451. .name = "pcie_layerscape_gen4",
  452. .id = UCLASS_PCI,
  453. .of_match = ls_pcie_g4_ids,
  454. .ops = &ls_pcie_g4_ops,
  455. .probe = ls_pcie_g4_probe,
  456. .priv_auto_alloc_size = sizeof(struct ls_pcie_g4),
  457. };