pcie_layerscape_fixup.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2020 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. * Layerscape PCIe driver
  6. */
  7. #include <common.h>
  8. #include <pci.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/io.h>
  11. #include <errno.h>
  12. #ifdef CONFIG_OF_BOARD_SETUP
  13. #include <linux/libfdt.h>
  14. #include <fdt_support.h>
  15. #ifdef CONFIG_ARM
  16. #include <asm/arch/clock.h>
  17. #endif
  18. #include "pcie_layerscape.h"
  19. #include "pcie_layerscape_fixup_common.h"
  20. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  21. /*
  22. * Return next available LUT index.
  23. */
  24. static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
  25. {
  26. if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  27. return pcie->next_lut_index++;
  28. else
  29. return -ENOSPC; /* LUT is full */
  30. }
  31. static void lut_writel(struct ls_pcie *pcie, unsigned int value,
  32. unsigned int offset)
  33. {
  34. if (pcie->big_endian)
  35. out_be32(pcie->lut + offset, value);
  36. else
  37. out_le32(pcie->lut + offset, value);
  38. }
  39. /*
  40. * Program a single LUT entry
  41. */
  42. static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
  43. u32 streamid)
  44. {
  45. /* leave mask as all zeroes, want to match all bits */
  46. lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  47. lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  48. }
  49. /*
  50. * An msi-map is a property to be added to the pci controller
  51. * node. It is a table, where each entry consists of 4 fields
  52. * e.g.:
  53. *
  54. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  55. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  56. */
  57. static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
  58. u32 devid, u32 streamid)
  59. {
  60. u32 *prop;
  61. u32 phandle;
  62. int nodeoffset;
  63. uint svr;
  64. char *compat = NULL;
  65. /* find pci controller node */
  66. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  67. pcie->dbi_res.start);
  68. if (nodeoffset < 0) {
  69. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  70. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  71. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  72. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  73. svr == SVR_LS2081A || svr == SVR_LS2041A)
  74. compat = "fsl,ls2088a-pcie";
  75. else
  76. compat = CONFIG_FSL_PCIE_COMPAT;
  77. if (compat)
  78. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  79. compat, pcie->dbi_res.start);
  80. #endif
  81. if (nodeoffset < 0)
  82. return;
  83. }
  84. /* get phandle to MSI controller */
  85. prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
  86. if (prop == NULL) {
  87. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  88. __func__, pcie->idx);
  89. return;
  90. }
  91. phandle = fdt32_to_cpu(*prop);
  92. /* set one msi-map row */
  93. fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
  94. fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
  95. fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
  96. fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
  97. }
  98. /*
  99. * An iommu-map is a property to be added to the pci controller
  100. * node. It is a table, where each entry consists of 4 fields
  101. * e.g.:
  102. *
  103. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  104. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  105. */
  106. static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
  107. u32 devid, u32 streamid)
  108. {
  109. u32 *prop;
  110. u32 iommu_map[4];
  111. int nodeoffset;
  112. int lenp;
  113. uint svr;
  114. char *compat = NULL;
  115. /* find pci controller node */
  116. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  117. pcie->dbi_res.start);
  118. if (nodeoffset < 0) {
  119. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  120. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  121. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  122. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  123. svr == SVR_LS2081A || svr == SVR_LS2041A)
  124. compat = "fsl,ls2088a-pcie";
  125. else
  126. compat = CONFIG_FSL_PCIE_COMPAT;
  127. if (compat)
  128. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  129. compat, pcie->dbi_res.start);
  130. #endif
  131. if (nodeoffset < 0)
  132. return;
  133. }
  134. /* get phandle to iommu controller */
  135. prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
  136. if (prop == NULL) {
  137. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  138. __func__, pcie->idx);
  139. return;
  140. }
  141. /* set iommu-map row */
  142. iommu_map[0] = cpu_to_fdt32(devid);
  143. iommu_map[1] = *++prop;
  144. iommu_map[2] = cpu_to_fdt32(streamid);
  145. iommu_map[3] = cpu_to_fdt32(1);
  146. if (devid == 0) {
  147. fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
  148. iommu_map, 16);
  149. } else {
  150. fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
  151. }
  152. }
  153. static void fdt_fixup_pcie_ls(void *blob)
  154. {
  155. struct udevice *dev, *bus;
  156. struct ls_pcie *pcie;
  157. int streamid;
  158. int index;
  159. pci_dev_t bdf;
  160. /* Scan all known buses */
  161. for (pci_find_first_device(&dev);
  162. dev;
  163. pci_find_next_device(&dev)) {
  164. for (bus = dev; device_is_on_pci_bus(bus);)
  165. bus = bus->parent;
  166. pcie = dev_get_priv(bus);
  167. streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
  168. if (streamid < 0) {
  169. debug("ERROR: no stream ids free\n");
  170. continue;
  171. } else {
  172. pcie->stream_id_cur++;
  173. }
  174. index = ls_pcie_next_lut_index(pcie);
  175. if (index < 0) {
  176. debug("ERROR: no LUT indexes free\n");
  177. continue;
  178. }
  179. /* the DT fixup must be relative to the hose first_busno */
  180. bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
  181. /* map PCI b.d.f to streamID in LUT */
  182. ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
  183. streamid);
  184. /* update msi-map in device tree */
  185. fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
  186. streamid);
  187. /* update iommu-map in device tree */
  188. fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
  189. streamid);
  190. }
  191. pcie_board_fix_fdt(blob);
  192. }
  193. #endif
  194. static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
  195. {
  196. int off;
  197. uint svr;
  198. char *compat = NULL;
  199. off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  200. pcie->dbi_res.start);
  201. if (off < 0) {
  202. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  203. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  204. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  205. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  206. svr == SVR_LS2081A || svr == SVR_LS2041A)
  207. compat = "fsl,ls2088a-pcie";
  208. else
  209. compat = CONFIG_FSL_PCIE_COMPAT;
  210. if (compat)
  211. off = fdt_node_offset_by_compat_reg(blob,
  212. compat, pcie->dbi_res.start);
  213. #endif
  214. if (off < 0)
  215. return;
  216. }
  217. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
  218. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  219. else
  220. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  221. }
  222. static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
  223. {
  224. int off;
  225. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
  226. pcie->dbi_res.start);
  227. if (off < 0)
  228. return;
  229. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  230. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  231. else
  232. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  233. }
  234. static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
  235. {
  236. ft_pcie_ep_fix(blob, pcie);
  237. ft_pcie_rc_fix(blob, pcie);
  238. }
  239. /* Fixup Kernel DT for PCIe */
  240. void ft_pci_setup_ls(void *blob, bd_t *bd)
  241. {
  242. struct ls_pcie *pcie;
  243. list_for_each_entry(pcie, &ls_pcie_list, list)
  244. ft_pcie_ls_setup(blob, pcie);
  245. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  246. fdt_fixup_pcie_ls(blob);
  247. #endif
  248. }
  249. #else /* !CONFIG_OF_BOARD_SETUP */
  250. void ft_pci_setup_ls(void *blob, bd_t *bd)
  251. {
  252. }
  253. #endif