pci_tegra.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010, CompuLab, Ltd.
  4. * Author: Mike Rapoport <mike@compulab.co.il>
  5. *
  6. * Based on NVIDIA PCIe driver
  7. * Copyright (c) 2008-2009, NVIDIA Corporation.
  8. *
  9. * Copyright (c) 2013-2014, NVIDIA Corporation.
  10. */
  11. #define pr_fmt(fmt) "tegra-pcie: " fmt
  12. #include <common.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <malloc.h>
  17. #include <pci.h>
  18. #include <pci_tegra.h>
  19. #include <power-domain.h>
  20. #include <reset.h>
  21. #include <asm/io.h>
  22. #include <asm/gpio.h>
  23. #include <linux/ioport.h>
  24. #include <linux/list.h>
  25. #ifndef CONFIG_TEGRA186
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/powergate.h>
  28. #include <asm/arch-tegra/xusb-padctl.h>
  29. #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  30. #endif
  31. /*
  32. * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
  33. * should not be present. These are needed because newer Tegra SoCs support
  34. * only the standard clock/reset APIs, whereas older Tegra SoCs support only
  35. * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
  36. * fixed to implement the standard APIs, and all drivers converted to solely
  37. * use the new standard APIs, with no ifdefs.
  38. */
  39. #define AFI_AXI_BAR0_SZ 0x00
  40. #define AFI_AXI_BAR1_SZ 0x04
  41. #define AFI_AXI_BAR2_SZ 0x08
  42. #define AFI_AXI_BAR3_SZ 0x0c
  43. #define AFI_AXI_BAR4_SZ 0x10
  44. #define AFI_AXI_BAR5_SZ 0x14
  45. #define AFI_AXI_BAR0_START 0x18
  46. #define AFI_AXI_BAR1_START 0x1c
  47. #define AFI_AXI_BAR2_START 0x20
  48. #define AFI_AXI_BAR3_START 0x24
  49. #define AFI_AXI_BAR4_START 0x28
  50. #define AFI_AXI_BAR5_START 0x2c
  51. #define AFI_FPCI_BAR0 0x30
  52. #define AFI_FPCI_BAR1 0x34
  53. #define AFI_FPCI_BAR2 0x38
  54. #define AFI_FPCI_BAR3 0x3c
  55. #define AFI_FPCI_BAR4 0x40
  56. #define AFI_FPCI_BAR5 0x44
  57. #define AFI_CACHE_BAR0_SZ 0x48
  58. #define AFI_CACHE_BAR0_ST 0x4c
  59. #define AFI_CACHE_BAR1_SZ 0x50
  60. #define AFI_CACHE_BAR1_ST 0x54
  61. #define AFI_MSI_BAR_SZ 0x60
  62. #define AFI_MSI_FPCI_BAR_ST 0x64
  63. #define AFI_MSI_AXI_BAR_ST 0x68
  64. #define AFI_CONFIGURATION 0xac
  65. #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
  66. #define AFI_FPCI_ERROR_MASKS 0xb0
  67. #define AFI_INTR_MASK 0xb4
  68. #define AFI_INTR_MASK_INT_MASK (1 << 0)
  69. #define AFI_INTR_MASK_MSI_MASK (1 << 8)
  70. #define AFI_SM_INTR_ENABLE 0xc4
  71. #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
  72. #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
  73. #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
  74. #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
  75. #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
  76. #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
  77. #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
  78. #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
  79. #define AFI_AFI_INTR_ENABLE 0xc8
  80. #define AFI_INTR_EN_INI_SLVERR (1 << 0)
  81. #define AFI_INTR_EN_INI_DECERR (1 << 1)
  82. #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
  83. #define AFI_INTR_EN_TGT_DECERR (1 << 3)
  84. #define AFI_INTR_EN_TGT_WRERR (1 << 4)
  85. #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
  86. #define AFI_INTR_EN_AXI_DECERR (1 << 6)
  87. #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
  88. #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
  89. #define AFI_PCIE_CONFIG 0x0f8
  90. #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
  91. #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
  92. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
  93. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
  94. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
  95. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
  96. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
  97. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
  98. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
  99. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
  100. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
  101. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
  102. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
  103. #define AFI_FUSE 0x104
  104. #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
  105. #define AFI_PEX0_CTRL 0x110
  106. #define AFI_PEX1_CTRL 0x118
  107. #define AFI_PEX2_CTRL 0x128
  108. #define AFI_PEX2_CTRL_T186 0x19c
  109. #define AFI_PEX_CTRL_RST (1 << 0)
  110. #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
  111. #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
  112. #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
  113. #define AFI_PLLE_CONTROL 0x160
  114. #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
  115. #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
  116. #define AFI_PEXBIAS_CTRL_0 0x168
  117. #define PADS_CTL_SEL 0x0000009C
  118. #define PADS_CTL 0x000000A0
  119. #define PADS_CTL_IDDQ_1L (1 << 0)
  120. #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
  121. #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
  122. #define PADS_PLL_CTL_TEGRA20 0x000000B8
  123. #define PADS_PLL_CTL_TEGRA30 0x000000B4
  124. #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
  125. #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
  126. #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
  127. #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
  128. #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
  129. #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
  130. #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
  131. #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
  132. #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
  133. #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
  134. #define PADS_REFCLK_CFG0 0x000000C8
  135. #define PADS_REFCLK_CFG1 0x000000CC
  136. /*
  137. * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
  138. * entries, one entry per PCIe port. These field definitions and desired
  139. * values aren't in the TRM, but do come from NVIDIA.
  140. */
  141. #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
  142. #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
  143. #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
  144. #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
  145. #define RP_VEND_XP 0x00000F00
  146. #define RP_VEND_XP_DL_UP (1 << 30)
  147. #define RP_VEND_CTL2 0x00000FA8
  148. #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
  149. #define RP_PRIV_MISC 0x00000FE0
  150. #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
  151. #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
  152. #define RP_LINK_CONTROL_STATUS 0x00000090
  153. #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
  154. #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
  155. enum tegra_pci_id {
  156. TEGRA20_PCIE,
  157. TEGRA30_PCIE,
  158. TEGRA124_PCIE,
  159. TEGRA210_PCIE,
  160. TEGRA186_PCIE,
  161. };
  162. struct tegra_pcie_port {
  163. struct tegra_pcie *pcie;
  164. struct fdt_resource regs;
  165. unsigned int num_lanes;
  166. unsigned int index;
  167. struct list_head list;
  168. };
  169. struct tegra_pcie_soc {
  170. unsigned int num_ports;
  171. unsigned long pads_pll_ctl;
  172. unsigned long tx_ref_sel;
  173. unsigned long afi_pex2_ctrl;
  174. u32 pads_refclk_cfg0;
  175. u32 pads_refclk_cfg1;
  176. bool has_pex_clkreq_en;
  177. bool has_pex_bias_ctrl;
  178. bool has_cml_clk;
  179. bool has_gen2;
  180. bool force_pca_enable;
  181. };
  182. struct tegra_pcie {
  183. struct resource pads;
  184. struct resource afi;
  185. struct resource cs;
  186. struct list_head ports;
  187. unsigned long xbar;
  188. const struct tegra_pcie_soc *soc;
  189. #ifdef CONFIG_TEGRA186
  190. struct clk clk_afi;
  191. struct clk clk_pex;
  192. struct reset_ctl reset_afi;
  193. struct reset_ctl reset_pex;
  194. struct reset_ctl reset_pcie_x;
  195. struct power_domain pwrdom;
  196. #else
  197. struct tegra_xusb_phy *phy;
  198. #endif
  199. };
  200. static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
  201. unsigned long offset)
  202. {
  203. writel(value, pcie->afi.start + offset);
  204. }
  205. static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
  206. {
  207. return readl(pcie->afi.start + offset);
  208. }
  209. static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
  210. unsigned long offset)
  211. {
  212. writel(value, pcie->pads.start + offset);
  213. }
  214. #ifndef CONFIG_TEGRA186
  215. static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
  216. {
  217. return readl(pcie->pads.start + offset);
  218. }
  219. #endif
  220. static unsigned long rp_readl(struct tegra_pcie_port *port,
  221. unsigned long offset)
  222. {
  223. return readl(port->regs.start + offset);
  224. }
  225. static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
  226. unsigned long offset)
  227. {
  228. writel(value, port->regs.start + offset);
  229. }
  230. static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
  231. {
  232. return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
  233. (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
  234. (where & 0xfc);
  235. }
  236. static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
  237. int where, unsigned long *address)
  238. {
  239. unsigned int bus = PCI_BUS(bdf);
  240. if (bus == 0) {
  241. unsigned int dev = PCI_DEV(bdf);
  242. struct tegra_pcie_port *port;
  243. list_for_each_entry(port, &pcie->ports, list) {
  244. if (port->index + 1 == dev) {
  245. *address = port->regs.start + (where & ~3);
  246. return 0;
  247. }
  248. }
  249. return -EFAULT;
  250. } else {
  251. #ifdef CONFIG_TEGRA20
  252. unsigned int dev = PCI_DEV(bdf);
  253. if (dev != 0)
  254. return -EFAULT;
  255. #endif
  256. *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
  257. return 0;
  258. }
  259. }
  260. static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
  261. uint offset, ulong *valuep,
  262. enum pci_size_t size)
  263. {
  264. struct tegra_pcie *pcie = dev_get_priv(bus);
  265. unsigned long address, value;
  266. int err;
  267. err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
  268. if (err < 0) {
  269. value = 0xffffffff;
  270. goto done;
  271. }
  272. value = readl(address);
  273. #ifdef CONFIG_TEGRA20
  274. /* fixup root port class */
  275. if (PCI_BUS(bdf) == 0) {
  276. if ((offset & ~3) == PCI_CLASS_REVISION) {
  277. value &= ~0x00ff0000;
  278. value |= PCI_CLASS_BRIDGE_PCI << 16;
  279. }
  280. }
  281. #endif
  282. done:
  283. *valuep = pci_conv_32_to_size(value, offset, size);
  284. return 0;
  285. }
  286. static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
  287. uint offset, ulong value,
  288. enum pci_size_t size)
  289. {
  290. struct tegra_pcie *pcie = dev_get_priv(bus);
  291. unsigned long address;
  292. ulong old;
  293. int err;
  294. err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
  295. if (err < 0)
  296. return 0;
  297. old = readl(address);
  298. value = pci_conv_size_to_32(old, value, offset, size);
  299. writel(value, address);
  300. return 0;
  301. }
  302. static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
  303. {
  304. const u32 *addr;
  305. int len;
  306. addr = ofnode_get_property(node, "assigned-addresses", &len);
  307. if (!addr) {
  308. pr_err("property \"assigned-addresses\" not found");
  309. return -FDT_ERR_NOTFOUND;
  310. }
  311. port->regs.start = fdt32_to_cpu(addr[2]);
  312. port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
  313. return 0;
  314. }
  315. static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
  316. enum tegra_pci_id id, unsigned long *xbar)
  317. {
  318. switch (id) {
  319. case TEGRA20_PCIE:
  320. switch (lanes) {
  321. case 0x00000004:
  322. debug("single-mode configuration\n");
  323. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
  324. return 0;
  325. case 0x00000202:
  326. debug("dual-mode configuration\n");
  327. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
  328. return 0;
  329. }
  330. break;
  331. case TEGRA30_PCIE:
  332. switch (lanes) {
  333. case 0x00000204:
  334. debug("4x1, 2x1 configuration\n");
  335. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
  336. return 0;
  337. case 0x00020202:
  338. debug("2x3 configuration\n");
  339. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
  340. return 0;
  341. case 0x00010104:
  342. debug("4x1, 1x2 configuration\n");
  343. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
  344. return 0;
  345. }
  346. break;
  347. case TEGRA124_PCIE:
  348. case TEGRA210_PCIE:
  349. switch (lanes) {
  350. case 0x0000104:
  351. debug("4x1, 1x1 configuration\n");
  352. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
  353. return 0;
  354. case 0x0000102:
  355. debug("2x1, 1x1 configuration\n");
  356. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
  357. return 0;
  358. }
  359. break;
  360. case TEGRA186_PCIE:
  361. switch (lanes) {
  362. case 0x0010004:
  363. debug("x4 x1 configuration\n");
  364. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
  365. return 0;
  366. case 0x0010102:
  367. debug("x2 x1 x1 configuration\n");
  368. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
  369. return 0;
  370. case 0x0010101:
  371. debug("x1 x1 x1 configuration\n");
  372. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
  373. return 0;
  374. }
  375. break;
  376. default:
  377. break;
  378. }
  379. return -FDT_ERR_NOTFOUND;
  380. }
  381. static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
  382. {
  383. struct fdt_pci_addr addr;
  384. int err;
  385. err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
  386. if (err < 0) {
  387. pr_err("failed to parse \"nvidia,num-lanes\" property");
  388. return err;
  389. }
  390. *lanes = err;
  391. err = ofnode_read_pci_addr(node, 0, "reg", &addr);
  392. if (err < 0) {
  393. pr_err("failed to parse \"reg\" property");
  394. return err;
  395. }
  396. *index = PCI_DEV(addr.phys_hi) - 1;
  397. return 0;
  398. }
  399. int __weak tegra_pcie_board_init(void)
  400. {
  401. return 0;
  402. }
  403. static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
  404. struct tegra_pcie *pcie)
  405. {
  406. ofnode subnode;
  407. u32 lanes = 0;
  408. int err;
  409. err = dev_read_resource(dev, 0, &pcie->pads);
  410. if (err < 0) {
  411. pr_err("resource \"pads\" not found");
  412. return err;
  413. }
  414. err = dev_read_resource(dev, 1, &pcie->afi);
  415. if (err < 0) {
  416. pr_err("resource \"afi\" not found");
  417. return err;
  418. }
  419. err = dev_read_resource(dev, 2, &pcie->cs);
  420. if (err < 0) {
  421. pr_err("resource \"cs\" not found");
  422. return err;
  423. }
  424. err = tegra_pcie_board_init();
  425. if (err < 0) {
  426. pr_err("tegra_pcie_board_init() failed: err=%d", err);
  427. return err;
  428. }
  429. #ifndef CONFIG_TEGRA186
  430. pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
  431. if (pcie->phy) {
  432. err = tegra_xusb_phy_prepare(pcie->phy);
  433. if (err < 0) {
  434. pr_err("failed to prepare PHY: %d", err);
  435. return err;
  436. }
  437. }
  438. #endif
  439. dev_for_each_subnode(subnode, dev) {
  440. unsigned int index = 0, num_lanes = 0;
  441. struct tegra_pcie_port *port;
  442. err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
  443. if (err < 0) {
  444. pr_err("failed to obtain root port info");
  445. continue;
  446. }
  447. lanes |= num_lanes << (index << 3);
  448. if (!ofnode_is_available(subnode))
  449. continue;
  450. port = malloc(sizeof(*port));
  451. if (!port)
  452. continue;
  453. memset(port, 0, sizeof(*port));
  454. port->num_lanes = num_lanes;
  455. port->index = index;
  456. err = tegra_pcie_port_parse_dt(subnode, port);
  457. if (err < 0) {
  458. free(port);
  459. continue;
  460. }
  461. list_add_tail(&port->list, &pcie->ports);
  462. port->pcie = pcie;
  463. }
  464. err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
  465. &pcie->xbar);
  466. if (err < 0) {
  467. pr_err("invalid lane configuration");
  468. return err;
  469. }
  470. return 0;
  471. }
  472. #ifdef CONFIG_TEGRA186
  473. static int tegra_pcie_power_on(struct tegra_pcie *pcie)
  474. {
  475. int ret;
  476. ret = power_domain_on(&pcie->pwrdom);
  477. if (ret) {
  478. pr_err("power_domain_on() failed: %d\n", ret);
  479. return ret;
  480. }
  481. ret = clk_enable(&pcie->clk_afi);
  482. if (ret) {
  483. pr_err("clk_enable(afi) failed: %d\n", ret);
  484. return ret;
  485. }
  486. ret = clk_enable(&pcie->clk_pex);
  487. if (ret) {
  488. pr_err("clk_enable(pex) failed: %d\n", ret);
  489. return ret;
  490. }
  491. ret = reset_deassert(&pcie->reset_afi);
  492. if (ret) {
  493. pr_err("reset_deassert(afi) failed: %d\n", ret);
  494. return ret;
  495. }
  496. ret = reset_deassert(&pcie->reset_pex);
  497. if (ret) {
  498. pr_err("reset_deassert(pex) failed: %d\n", ret);
  499. return ret;
  500. }
  501. return 0;
  502. }
  503. #else
  504. static int tegra_pcie_power_on(struct tegra_pcie *pcie)
  505. {
  506. const struct tegra_pcie_soc *soc = pcie->soc;
  507. unsigned long value;
  508. int err;
  509. /* reset PCIEXCLK logic, AFI controller and PCIe controller */
  510. reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
  511. reset_set_enable(PERIPH_ID_AFI, 1);
  512. reset_set_enable(PERIPH_ID_PCIE, 1);
  513. err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
  514. if (err < 0) {
  515. pr_err("failed to power off PCIe partition: %d", err);
  516. return err;
  517. }
  518. err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
  519. PERIPH_ID_PCIE);
  520. if (err < 0) {
  521. pr_err("failed to power up PCIe partition: %d", err);
  522. return err;
  523. }
  524. /* take AFI controller out of reset */
  525. reset_set_enable(PERIPH_ID_AFI, 0);
  526. /* enable AFI clock */
  527. clock_enable(PERIPH_ID_AFI);
  528. if (soc->has_cml_clk) {
  529. /* enable CML clock */
  530. value = readl(NV_PA_CLK_RST_BASE + 0x48c);
  531. value |= (1 << 0);
  532. value &= ~(1 << 1);
  533. writel(value, NV_PA_CLK_RST_BASE + 0x48c);
  534. }
  535. err = tegra_plle_enable();
  536. if (err < 0) {
  537. pr_err("failed to enable PLLE: %d\n", err);
  538. return err;
  539. }
  540. return 0;
  541. }
  542. static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
  543. {
  544. const struct tegra_pcie_soc *soc = pcie->soc;
  545. unsigned long start = get_timer(0);
  546. u32 value;
  547. while (get_timer(start) < timeout) {
  548. value = pads_readl(pcie, soc->pads_pll_ctl);
  549. if (value & PADS_PLL_CTL_LOCKDET)
  550. return 0;
  551. }
  552. return -ETIMEDOUT;
  553. }
  554. static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
  555. {
  556. const struct tegra_pcie_soc *soc = pcie->soc;
  557. u32 value;
  558. int err;
  559. /* initialize internal PHY, enable up to 16 PCIe lanes */
  560. pads_writel(pcie, 0, PADS_CTL_SEL);
  561. /* override IDDQ to 1 on all 4 lanes */
  562. value = pads_readl(pcie, PADS_CTL);
  563. value |= PADS_CTL_IDDQ_1L;
  564. pads_writel(pcie, value, PADS_CTL);
  565. /*
  566. * Set up PHY PLL inputs select PLLE output as refclock, set TX
  567. * ref sel to div10 (not div5).
  568. */
  569. value = pads_readl(pcie, soc->pads_pll_ctl);
  570. value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
  571. value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
  572. pads_writel(pcie, value, soc->pads_pll_ctl);
  573. /* reset PLL */
  574. value = pads_readl(pcie, soc->pads_pll_ctl);
  575. value &= ~PADS_PLL_CTL_RST_B4SM;
  576. pads_writel(pcie, value, soc->pads_pll_ctl);
  577. udelay(20);
  578. /* take PLL out of reset */
  579. value = pads_readl(pcie, soc->pads_pll_ctl);
  580. value |= PADS_PLL_CTL_RST_B4SM;
  581. pads_writel(pcie, value, soc->pads_pll_ctl);
  582. /* wait for the PLL to lock */
  583. err = tegra_pcie_pll_wait(pcie, 500);
  584. if (err < 0) {
  585. pr_err("PLL failed to lock: %d", err);
  586. return err;
  587. }
  588. /* turn off IDDQ override */
  589. value = pads_readl(pcie, PADS_CTL);
  590. value &= ~PADS_CTL_IDDQ_1L;
  591. pads_writel(pcie, value, PADS_CTL);
  592. /* enable TX/RX data */
  593. value = pads_readl(pcie, PADS_CTL);
  594. value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
  595. pads_writel(pcie, value, PADS_CTL);
  596. return 0;
  597. }
  598. #endif
  599. static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
  600. {
  601. const struct tegra_pcie_soc *soc = pcie->soc;
  602. struct tegra_pcie_port *port;
  603. u32 value;
  604. int err;
  605. #ifdef CONFIG_TEGRA186
  606. {
  607. #else
  608. if (pcie->phy) {
  609. #endif
  610. value = afi_readl(pcie, AFI_PLLE_CONTROL);
  611. value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
  612. value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
  613. afi_writel(pcie, value, AFI_PLLE_CONTROL);
  614. }
  615. if (soc->has_pex_bias_ctrl)
  616. afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
  617. value = afi_readl(pcie, AFI_PCIE_CONFIG);
  618. value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
  619. value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
  620. list_for_each_entry(port, &pcie->ports, list)
  621. value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
  622. afi_writel(pcie, value, AFI_PCIE_CONFIG);
  623. value = afi_readl(pcie, AFI_FUSE);
  624. if (soc->has_gen2)
  625. value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
  626. else
  627. value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
  628. afi_writel(pcie, value, AFI_FUSE);
  629. #ifndef CONFIG_TEGRA186
  630. if (pcie->phy)
  631. err = tegra_xusb_phy_enable(pcie->phy);
  632. else
  633. err = tegra_pcie_phy_enable(pcie);
  634. if (err < 0) {
  635. pr_err("failed to power on PHY: %d\n", err);
  636. return err;
  637. }
  638. #endif
  639. /* take the PCIEXCLK logic out of reset */
  640. #ifdef CONFIG_TEGRA186
  641. err = reset_deassert(&pcie->reset_pcie_x);
  642. if (err) {
  643. pr_err("reset_deassert(pcie_x) failed: %d\n", err);
  644. return err;
  645. }
  646. #else
  647. reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
  648. #endif
  649. /* finally enable PCIe */
  650. value = afi_readl(pcie, AFI_CONFIGURATION);
  651. value |= AFI_CONFIGURATION_EN_FPCI;
  652. afi_writel(pcie, value, AFI_CONFIGURATION);
  653. /* disable all interrupts */
  654. afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
  655. afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
  656. afi_writel(pcie, 0, AFI_INTR_MASK);
  657. afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
  658. return 0;
  659. }
  660. static int tegra_pcie_setup_translations(struct udevice *bus)
  661. {
  662. struct tegra_pcie *pcie = dev_get_priv(bus);
  663. unsigned long fpci, axi, size;
  664. struct pci_region *io, *mem, *pref;
  665. int count;
  666. /* BAR 0: type 1 extended configuration space */
  667. fpci = 0xfe100000;
  668. size = resource_size(&pcie->cs);
  669. axi = pcie->cs.start;
  670. afi_writel(pcie, axi, AFI_AXI_BAR0_START);
  671. afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
  672. afi_writel(pcie, fpci, AFI_FPCI_BAR0);
  673. count = pci_get_regions(bus, &io, &mem, &pref);
  674. if (count != 3)
  675. return -EINVAL;
  676. /* BAR 1: downstream I/O */
  677. fpci = 0xfdfc0000;
  678. size = io->size;
  679. axi = io->phys_start;
  680. afi_writel(pcie, axi, AFI_AXI_BAR1_START);
  681. afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
  682. afi_writel(pcie, fpci, AFI_FPCI_BAR1);
  683. /* BAR 2: prefetchable memory */
  684. fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
  685. size = pref->size;
  686. axi = pref->phys_start;
  687. afi_writel(pcie, axi, AFI_AXI_BAR2_START);
  688. afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
  689. afi_writel(pcie, fpci, AFI_FPCI_BAR2);
  690. /* BAR 3: non-prefetchable memory */
  691. fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
  692. size = mem->size;
  693. axi = mem->phys_start;
  694. afi_writel(pcie, axi, AFI_AXI_BAR3_START);
  695. afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
  696. afi_writel(pcie, fpci, AFI_FPCI_BAR3);
  697. /* NULL out the remaining BARs as they are not used */
  698. afi_writel(pcie, 0, AFI_AXI_BAR4_START);
  699. afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
  700. afi_writel(pcie, 0, AFI_FPCI_BAR4);
  701. afi_writel(pcie, 0, AFI_AXI_BAR5_START);
  702. afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
  703. afi_writel(pcie, 0, AFI_FPCI_BAR5);
  704. /* map all upstream transactions as uncached */
  705. afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
  706. afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
  707. afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
  708. afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
  709. /* MSI translations are setup only when needed */
  710. afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
  711. afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
  712. afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
  713. afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
  714. return 0;
  715. }
  716. static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
  717. {
  718. unsigned long ret = 0;
  719. switch (port->index) {
  720. case 0:
  721. ret = AFI_PEX0_CTRL;
  722. break;
  723. case 1:
  724. ret = AFI_PEX1_CTRL;
  725. break;
  726. case 2:
  727. ret = port->pcie->soc->afi_pex2_ctrl;
  728. break;
  729. }
  730. return ret;
  731. }
  732. void tegra_pcie_port_reset(struct tegra_pcie_port *port)
  733. {
  734. unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
  735. unsigned long value;
  736. /* pulse reset signel */
  737. value = afi_readl(port->pcie, ctrl);
  738. value &= ~AFI_PEX_CTRL_RST;
  739. afi_writel(port->pcie, value, ctrl);
  740. udelay(2000);
  741. value = afi_readl(port->pcie, ctrl);
  742. value |= AFI_PEX_CTRL_RST;
  743. afi_writel(port->pcie, value, ctrl);
  744. }
  745. int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port)
  746. {
  747. return port->index;
  748. }
  749. void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
  750. {
  751. tegra_pcie_port_reset(port);
  752. }
  753. static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
  754. {
  755. struct tegra_pcie *pcie = port->pcie;
  756. const struct tegra_pcie_soc *soc = pcie->soc;
  757. unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
  758. unsigned long value;
  759. /* enable reference clock */
  760. value = afi_readl(pcie, ctrl);
  761. value |= AFI_PEX_CTRL_REFCLK_EN;
  762. if (pcie->soc->has_pex_clkreq_en)
  763. value |= AFI_PEX_CTRL_CLKREQ_EN;
  764. value |= AFI_PEX_CTRL_OVERRIDE_EN;
  765. afi_writel(pcie, value, ctrl);
  766. tegra_pcie_board_port_reset(port);
  767. if (soc->force_pca_enable) {
  768. value = rp_readl(port, RP_VEND_CTL2);
  769. value |= RP_VEND_CTL2_PCA_ENABLE;
  770. rp_writel(port, value, RP_VEND_CTL2);
  771. }
  772. /* configure the reference clock driver */
  773. pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
  774. if (soc->num_ports > 2)
  775. pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
  776. }
  777. static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
  778. {
  779. unsigned int retries = 3;
  780. unsigned long value;
  781. value = rp_readl(port, RP_PRIV_MISC);
  782. value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
  783. value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
  784. rp_writel(port, value, RP_PRIV_MISC);
  785. do {
  786. unsigned int timeout = 200;
  787. do {
  788. value = rp_readl(port, RP_VEND_XP);
  789. if (value & RP_VEND_XP_DL_UP)
  790. break;
  791. udelay(2000);
  792. } while (--timeout);
  793. if (!timeout) {
  794. debug("link %u down, retrying\n", port->index);
  795. goto retry;
  796. }
  797. timeout = 200;
  798. do {
  799. value = rp_readl(port, RP_LINK_CONTROL_STATUS);
  800. if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
  801. return true;
  802. udelay(2000);
  803. } while (--timeout);
  804. retry:
  805. tegra_pcie_board_port_reset(port);
  806. } while (--retries);
  807. return false;
  808. }
  809. static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
  810. {
  811. unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
  812. unsigned long value;
  813. /* assert port reset */
  814. value = afi_readl(port->pcie, ctrl);
  815. value &= ~AFI_PEX_CTRL_RST;
  816. afi_writel(port->pcie, value, ctrl);
  817. /* disable reference clock */
  818. value = afi_readl(port->pcie, ctrl);
  819. value &= ~AFI_PEX_CTRL_REFCLK_EN;
  820. afi_writel(port->pcie, value, ctrl);
  821. }
  822. static void tegra_pcie_port_free(struct tegra_pcie_port *port)
  823. {
  824. list_del(&port->list);
  825. free(port);
  826. }
  827. static int tegra_pcie_enable(struct tegra_pcie *pcie)
  828. {
  829. struct tegra_pcie_port *port, *tmp;
  830. list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
  831. debug("probing port %u, using %u lanes\n", port->index,
  832. port->num_lanes);
  833. tegra_pcie_port_enable(port);
  834. if (tegra_pcie_port_check_link(port))
  835. continue;
  836. debug("link %u down, ignoring\n", port->index);
  837. tegra_pcie_port_disable(port);
  838. tegra_pcie_port_free(port);
  839. }
  840. return 0;
  841. }
  842. static const struct tegra_pcie_soc pci_tegra_soc[] = {
  843. [TEGRA20_PCIE] = {
  844. .num_ports = 2,
  845. .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
  846. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
  847. .pads_refclk_cfg0 = 0xfa5cfa5c,
  848. .has_pex_clkreq_en = false,
  849. .has_pex_bias_ctrl = false,
  850. .has_cml_clk = false,
  851. .has_gen2 = false,
  852. },
  853. [TEGRA30_PCIE] = {
  854. .num_ports = 3,
  855. .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
  856. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
  857. .afi_pex2_ctrl = AFI_PEX2_CTRL,
  858. .pads_refclk_cfg0 = 0xfa5cfa5c,
  859. .pads_refclk_cfg1 = 0xfa5cfa5c,
  860. .has_pex_clkreq_en = true,
  861. .has_pex_bias_ctrl = true,
  862. .has_cml_clk = true,
  863. .has_gen2 = false,
  864. },
  865. [TEGRA124_PCIE] = {
  866. .num_ports = 2,
  867. .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
  868. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
  869. .pads_refclk_cfg0 = 0x44ac44ac,
  870. .has_pex_clkreq_en = true,
  871. .has_pex_bias_ctrl = true,
  872. .has_cml_clk = true,
  873. .has_gen2 = true,
  874. },
  875. [TEGRA210_PCIE] = {
  876. .num_ports = 2,
  877. .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
  878. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
  879. .pads_refclk_cfg0 = 0x90b890b8,
  880. .has_pex_clkreq_en = true,
  881. .has_pex_bias_ctrl = true,
  882. .has_cml_clk = true,
  883. .has_gen2 = true,
  884. .force_pca_enable = true,
  885. },
  886. [TEGRA186_PCIE] = {
  887. .num_ports = 3,
  888. .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
  889. .pads_refclk_cfg0 = 0x80b880b8,
  890. .pads_refclk_cfg1 = 0x000480b8,
  891. .has_pex_clkreq_en = true,
  892. .has_pex_bias_ctrl = true,
  893. .has_gen2 = true,
  894. },
  895. };
  896. static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
  897. {
  898. struct tegra_pcie *pcie = dev_get_priv(dev);
  899. enum tegra_pci_id id;
  900. id = dev_get_driver_data(dev);
  901. pcie->soc = &pci_tegra_soc[id];
  902. INIT_LIST_HEAD(&pcie->ports);
  903. if (tegra_pcie_parse_dt(dev, id, pcie))
  904. return -EINVAL;
  905. return 0;
  906. }
  907. static int pci_tegra_probe(struct udevice *dev)
  908. {
  909. struct tegra_pcie *pcie = dev_get_priv(dev);
  910. int err;
  911. #ifdef CONFIG_TEGRA186
  912. err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
  913. if (err) {
  914. debug("clk_get_by_name(afi) failed: %d\n", err);
  915. return err;
  916. }
  917. err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
  918. if (err) {
  919. debug("clk_get_by_name(pex) failed: %d\n", err);
  920. return err;
  921. }
  922. err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
  923. if (err) {
  924. debug("reset_get_by_name(afi) failed: %d\n", err);
  925. return err;
  926. }
  927. err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
  928. if (err) {
  929. debug("reset_get_by_name(pex) failed: %d\n", err);
  930. return err;
  931. }
  932. err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
  933. if (err) {
  934. debug("reset_get_by_name(pcie_x) failed: %d\n", err);
  935. return err;
  936. }
  937. err = power_domain_get(dev, &pcie->pwrdom);
  938. if (err) {
  939. debug("power_domain_get() failed: %d\n", err);
  940. return err;
  941. }
  942. #endif
  943. err = tegra_pcie_power_on(pcie);
  944. if (err < 0) {
  945. pr_err("failed to power on");
  946. return err;
  947. }
  948. err = tegra_pcie_enable_controller(pcie);
  949. if (err < 0) {
  950. pr_err("failed to enable controller");
  951. return err;
  952. }
  953. err = tegra_pcie_setup_translations(dev);
  954. if (err < 0) {
  955. pr_err("failed to decode ranges");
  956. return err;
  957. }
  958. err = tegra_pcie_enable(pcie);
  959. if (err < 0) {
  960. pr_err("failed to enable PCIe");
  961. return err;
  962. }
  963. return 0;
  964. }
  965. static const struct dm_pci_ops pci_tegra_ops = {
  966. .read_config = pci_tegra_read_config,
  967. .write_config = pci_tegra_write_config,
  968. };
  969. static const struct udevice_id pci_tegra_ids[] = {
  970. { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
  971. { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
  972. { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
  973. { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
  974. { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
  975. { }
  976. };
  977. U_BOOT_DRIVER(pci_tegra) = {
  978. .name = "pci_tegra",
  979. .id = UCLASS_PCI,
  980. .of_match = pci_tegra_ids,
  981. .ops = &pci_tegra_ops,
  982. .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
  983. .probe = pci_tegra_probe,
  984. .priv_auto_alloc_size = sizeof(struct tegra_pcie),
  985. };