pci_sh7751.c 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SH7751 PCI Controller (PCIC) for U-Boot.
  4. * (C) Dustin McIntire (dustin@sensoria.com)
  5. * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/io.h>
  12. #include <asm/pci.h>
  13. /* Register addresses and such */
  14. #define SH7751_BCR1 (vu_long *)0xFF800000
  15. #define SH7751_BCR2 (vu_short *)0xFF800004
  16. #define SH7751_WCR1 (vu_long *)0xFF800008
  17. #define SH7751_WCR2 (vu_long *)0xFF80000C
  18. #define SH7751_WCR3 (vu_long *)0xFF800010
  19. #define SH7751_MCR (vu_long *)0xFF800014
  20. #define SH7751_BCR3 (vu_short *)0xFF800050
  21. #define SH7751_PCICONF0 (vu_long *)0xFE200000
  22. #define SH7751_PCICONF1 (vu_long *)0xFE200004
  23. #define SH7751_PCICONF2 (vu_long *)0xFE200008
  24. #define SH7751_PCICONF3 (vu_long *)0xFE20000C
  25. #define SH7751_PCICONF4 (vu_long *)0xFE200010
  26. #define SH7751_PCICONF5 (vu_long *)0xFE200014
  27. #define SH7751_PCICONF6 (vu_long *)0xFE200018
  28. #define SH7751_PCICR (vu_long *)0xFE200100
  29. #define SH7751_PCILSR0 (vu_long *)0xFE200104
  30. #define SH7751_PCILSR1 (vu_long *)0xFE200108
  31. #define SH7751_PCILAR0 (vu_long *)0xFE20010C
  32. #define SH7751_PCILAR1 (vu_long *)0xFE200110
  33. #define SH7751_PCIMBR (vu_long *)0xFE2001C4
  34. #define SH7751_PCIIOBR (vu_long *)0xFE2001C8
  35. #define SH7751_PCIPINT (vu_long *)0xFE2001CC
  36. #define SH7751_PCIPINTM (vu_long *)0xFE2001D0
  37. #define SH7751_PCICLKR (vu_long *)0xFE2001D4
  38. #define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
  39. #define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
  40. #define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
  41. #define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
  42. #define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
  43. #define SH7751_PCIMCR (vu_long *)0xFE2001F4
  44. #define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
  45. #define BCR1_BREQEN 0x00080000
  46. #define PCI_SH7751_ID 0x35051054
  47. #define PCI_SH7751R_ID 0x350E1054
  48. #define SH7751_PCICONF1_WCC 0x00000080
  49. #define SH7751_PCICONF1_PER 0x00000040
  50. #define SH7751_PCICONF1_BUM 0x00000004
  51. #define SH7751_PCICONF1_MES 0x00000002
  52. #define SH7751_PCICONF1_CMDS 0x000000C6
  53. #define SH7751_PCI_HOST_BRIDGE 0x6
  54. #define SH7751_PCICR_PREFIX 0xa5000000
  55. #define SH7751_PCICR_PRST 0x00000002
  56. #define SH7751_PCICR_CFIN 0x00000001
  57. #define SH7751_PCIPINT_D3 0x00000002
  58. #define SH7751_PCIPINT_D0 0x00000001
  59. #define SH7751_PCICLKR_PREFIX 0xa5000000
  60. #define SH7751_PCI_MEM_BASE 0xFD000000
  61. #define SH7751_PCI_MEM_SIZE 0x01000000
  62. #define SH7751_PCI_IO_BASE 0xFE240000
  63. #define SH7751_PCI_IO_SIZE 0x00040000
  64. #define SH7751_PCIPAR (vu_long *)0xFE2001C0
  65. #define SH7751_PCIPDR (vu_long *)0xFE200220
  66. #define p4_in(addr) (*addr)
  67. #define p4_out(data, addr) (*addr) = (data)
  68. static int sh7751_pci_addr_valid(pci_dev_t d, uint offset)
  69. {
  70. if (PCI_FUNC(d))
  71. return -EINVAL;
  72. return 0;
  73. }
  74. static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset)
  75. {
  76. return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3);
  77. }
  78. static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
  79. uint offset, ulong *value,
  80. enum pci_size_t size)
  81. {
  82. u32 addr, reg;
  83. int ret;
  84. ret = sh7751_pci_addr_valid(bdf, offset);
  85. if (ret) {
  86. *value = pci_get_ff(size);
  87. return 0;
  88. }
  89. addr = get_bus_address(dev, bdf, offset);
  90. p4_out(addr, SH7751_PCIPAR);
  91. reg = p4_in(SH7751_PCIPDR);
  92. *value = pci_conv_32_to_size(reg, offset, size);
  93. return 0;
  94. }
  95. static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
  96. uint offset, ulong value,
  97. enum pci_size_t size)
  98. {
  99. u32 addr, reg, old;
  100. int ret;
  101. ret = sh7751_pci_addr_valid(bdf, offset);
  102. if (ret)
  103. return ret;
  104. addr = get_bus_address(dev, bdf, offset);
  105. p4_out(addr, SH7751_PCIPAR);
  106. old = p4_in(SH7751_PCIPDR);
  107. reg = pci_conv_size_to_32(old, value, offset, size);
  108. p4_out(reg, SH7751_PCIPDR);
  109. return 0;
  110. }
  111. static int sh7751_pci_probe(struct udevice *dev)
  112. {
  113. /* Double-check that we're a 7751 or 7751R chip */
  114. if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
  115. && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
  116. printf("PCI: Unknown PCI host bridge.\n");
  117. return 1;
  118. }
  119. printf("PCI: SH7751 PCI host bridge found.\n");
  120. /* Double-check some BSC config settings */
  121. /* (Area 3 non-MPX 32-bit, PCI bus pins) */
  122. if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
  123. printf("SH7751_BCR1 value is wrong(0x%08X)\n",
  124. (unsigned int)p4_in(SH7751_BCR1));
  125. return 2;
  126. }
  127. if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
  128. printf("SH7751_BCR2 value is wrong(0x%08X)\n",
  129. (unsigned int)p4_in(SH7751_BCR2));
  130. return 3;
  131. }
  132. if (p4_in(SH7751_BCR2) & 0x01) {
  133. printf("SH7751_BCR2 value is wrong(0x%08X)\n",
  134. (unsigned int)p4_in(SH7751_BCR2));
  135. return 4;
  136. }
  137. /* Force BREQEN in BCR1 to allow PCIC access */
  138. p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
  139. /* Toggle PCI reset pin */
  140. p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
  141. udelay(32);
  142. p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
  143. /* Set cmd bits: WCC, PER, BUM, MES */
  144. /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
  145. p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
  146. /* Define this host as the host bridge */
  147. p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
  148. /* Force PCI clock(s) on */
  149. p4_out(0, SH7751_PCICLKR);
  150. p4_out(0x03, SH7751_PCICLKR);
  151. /* Clear powerdown IRQs, also mask them (unused) */
  152. p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
  153. p4_out(0, SH7751_PCIPINTM);
  154. p4_out(0xab000001, SH7751_PCICONF4);
  155. /* Set up target memory mappings (for external DMA access) */
  156. /* Map both P0 and P2 range to Area 3 RAM for ease of use */
  157. p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
  158. p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
  159. p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
  160. p4_out(0, SH7751_PCILSR1);
  161. p4_out(0, SH7751_PCILAR1);
  162. p4_out(0xd0000000, SH7751_PCICONF6);
  163. /* Map memory window to same address on PCI bus */
  164. p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
  165. /* Map IO window to same address on PCI bus */
  166. p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
  167. /* set BREQEN */
  168. p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
  169. /* Copy BSC registers into PCI BSC */
  170. p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
  171. p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
  172. p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
  173. p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
  174. p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
  175. p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
  176. p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
  177. /* Finally, set central function init complete */
  178. p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
  179. return 0;
  180. }
  181. static const struct dm_pci_ops sh7751_pci_ops = {
  182. .read_config = sh7751_pci_read_config,
  183. .write_config = sh7751_pci_write_config,
  184. };
  185. static const struct udevice_id sh7751_pci_ids[] = {
  186. { .compatible = "renesas,pci-sh7751" },
  187. { }
  188. };
  189. U_BOOT_DRIVER(sh7751_pci) = {
  190. .name = "sh7751_pci",
  191. .id = UCLASS_PCI,
  192. .of_match = sh7751_pci_ids,
  193. .ops = &sh7751_pci_ops,
  194. .probe = sh7751_pci_probe,
  195. };