pci_auto.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI autoconfiguration library
  4. *
  5. * Author: Matt Porter <mporter@mvista.com>
  6. *
  7. * Copyright 2000 MontaVista Software Inc.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <pci.h>
  13. /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  14. #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  15. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  16. #endif
  17. void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
  18. struct pci_region *mem,
  19. struct pci_region *prefetch, struct pci_region *io,
  20. bool enum_only)
  21. {
  22. u32 bar_response;
  23. pci_size_t bar_size;
  24. u16 cmdstat = 0;
  25. int bar, bar_nr = 0;
  26. u8 header_type;
  27. int rom_addr;
  28. pci_addr_t bar_value;
  29. struct pci_region *bar_res = NULL;
  30. int found_mem64 = 0;
  31. u16 class;
  32. dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  33. cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
  34. PCI_COMMAND_MASTER;
  35. for (bar = PCI_BASE_ADDRESS_0;
  36. bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  37. int ret = 0;
  38. /* Tickle the BAR and get the response */
  39. if (!enum_only)
  40. dm_pci_write_config32(dev, bar, 0xffffffff);
  41. dm_pci_read_config32(dev, bar, &bar_response);
  42. /* If BAR is not implemented go to the next BAR */
  43. if (!bar_response)
  44. continue;
  45. found_mem64 = 0;
  46. /* Check the BAR type and set our address mask */
  47. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  48. bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  49. & 0xffff) + 1;
  50. if (!enum_only)
  51. bar_res = io;
  52. debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  53. bar_nr, (unsigned long long)bar_size);
  54. } else {
  55. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  56. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  57. u32 bar_response_upper;
  58. u64 bar64;
  59. if (!enum_only) {
  60. dm_pci_write_config32(dev, bar + 4,
  61. 0xffffffff);
  62. }
  63. dm_pci_read_config32(dev, bar + 4,
  64. &bar_response_upper);
  65. bar64 = ((u64)bar_response_upper << 32) |
  66. bar_response;
  67. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
  68. + 1;
  69. if (!enum_only)
  70. found_mem64 = 1;
  71. } else {
  72. bar_size = (u32)(~(bar_response &
  73. PCI_BASE_ADDRESS_MEM_MASK) + 1);
  74. }
  75. if (!enum_only) {
  76. if (prefetch && (bar_response &
  77. PCI_BASE_ADDRESS_MEM_PREFETCH)) {
  78. bar_res = prefetch;
  79. } else {
  80. bar_res = mem;
  81. }
  82. }
  83. debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  84. bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  85. (unsigned long long)bar_size);
  86. }
  87. if (!enum_only) {
  88. ret = pciauto_region_allocate(bar_res, bar_size,
  89. &bar_value, found_mem64);
  90. if (ret)
  91. printf("PCI: Failed autoconfig bar %x\n", bar);
  92. }
  93. if (!enum_only && !ret) {
  94. /* Write it out and update our limit */
  95. dm_pci_write_config32(dev, bar, (u32)bar_value);
  96. if (found_mem64) {
  97. bar += 4;
  98. #ifdef CONFIG_SYS_PCI_64BIT
  99. dm_pci_write_config32(dev, bar,
  100. (u32)(bar_value >> 32));
  101. #else
  102. /*
  103. * If we are a 64-bit decoder then increment to
  104. * the upper 32 bits of the bar and force it to
  105. * locate in the lower 4GB of memory.
  106. */
  107. dm_pci_write_config32(dev, bar, 0x00000000);
  108. #endif
  109. }
  110. }
  111. cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
  112. PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
  113. debug("\n");
  114. bar_nr++;
  115. }
  116. if (!enum_only) {
  117. /* Configure the expansion ROM address */
  118. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  119. header_type &= 0x7f;
  120. if (header_type != PCI_HEADER_TYPE_CARDBUS) {
  121. rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
  122. PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
  123. dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
  124. dm_pci_read_config32(dev, rom_addr, &bar_response);
  125. if (bar_response) {
  126. bar_size = -(bar_response & ~1);
  127. debug("PCI Autoconfig: ROM, size=%#x, ",
  128. (unsigned int)bar_size);
  129. if (pciauto_region_allocate(mem, bar_size,
  130. &bar_value,
  131. false) == 0) {
  132. dm_pci_write_config32(dev, rom_addr,
  133. bar_value);
  134. }
  135. cmdstat |= PCI_COMMAND_MEMORY;
  136. debug("\n");
  137. }
  138. }
  139. }
  140. /* PCI_COMMAND_IO must be set for VGA device */
  141. dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
  142. if (class == PCI_CLASS_DISPLAY_VGA)
  143. cmdstat |= PCI_COMMAND_IO;
  144. dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
  145. dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
  146. CONFIG_SYS_PCI_CACHE_LINE_SIZE);
  147. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
  148. }
  149. void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
  150. {
  151. struct pci_region *pci_mem;
  152. struct pci_region *pci_prefetch;
  153. struct pci_region *pci_io;
  154. u16 cmdstat, prefechable_64;
  155. struct udevice *ctlr = pci_get_controller(dev);
  156. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  157. pci_mem = ctlr_hose->pci_mem;
  158. pci_prefetch = ctlr_hose->pci_prefetch;
  159. pci_io = ctlr_hose->pci_io;
  160. dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  161. dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
  162. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  163. /* Configure bus number registers */
  164. dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
  165. PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
  166. dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
  167. dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
  168. if (pci_mem) {
  169. /* Round memory allocator to 1MB boundary */
  170. pciauto_region_align(pci_mem, 0x100000);
  171. /*
  172. * Set up memory and I/O filter limits, assume 32-bit
  173. * I/O space
  174. */
  175. dm_pci_write_config16(dev, PCI_MEMORY_BASE,
  176. (pci_mem->bus_lower & 0xfff00000) >> 16);
  177. cmdstat |= PCI_COMMAND_MEMORY;
  178. }
  179. if (pci_prefetch) {
  180. /* Round memory allocator to 1MB boundary */
  181. pciauto_region_align(pci_prefetch, 0x100000);
  182. /*
  183. * Set up memory and I/O filter limits, assume 32-bit
  184. * I/O space
  185. */
  186. dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
  187. (pci_prefetch->bus_lower & 0xfff00000) >> 16);
  188. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  189. #ifdef CONFIG_SYS_PCI_64BIT
  190. dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
  191. pci_prefetch->bus_lower >> 32);
  192. #else
  193. dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
  194. #endif
  195. cmdstat |= PCI_COMMAND_MEMORY;
  196. } else {
  197. /* We don't support prefetchable memory for now, so disable */
  198. dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
  199. dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
  200. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
  201. dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
  202. dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  203. }
  204. }
  205. if (pci_io) {
  206. /* Round I/O allocator to 4KB boundary */
  207. pciauto_region_align(pci_io, 0x1000);
  208. dm_pci_write_config8(dev, PCI_IO_BASE,
  209. (pci_io->bus_lower & 0x0000f000) >> 8);
  210. dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
  211. (pci_io->bus_lower & 0xffff0000) >> 16);
  212. cmdstat |= PCI_COMMAND_IO;
  213. }
  214. /* Enable memory and I/O accesses, enable bus master */
  215. dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
  216. }
  217. void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
  218. {
  219. struct pci_region *pci_mem;
  220. struct pci_region *pci_prefetch;
  221. struct pci_region *pci_io;
  222. struct udevice *ctlr = pci_get_controller(dev);
  223. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  224. pci_mem = ctlr_hose->pci_mem;
  225. pci_prefetch = ctlr_hose->pci_prefetch;
  226. pci_io = ctlr_hose->pci_io;
  227. /* Configure bus number registers */
  228. dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);
  229. if (pci_mem) {
  230. /* Round memory allocator to 1MB boundary */
  231. pciauto_region_align(pci_mem, 0x100000);
  232. dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
  233. (pci_mem->bus_lower - 1) >> 16);
  234. }
  235. if (pci_prefetch) {
  236. u16 prefechable_64;
  237. dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
  238. &prefechable_64);
  239. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  240. /* Round memory allocator to 1MB boundary */
  241. pciauto_region_align(pci_prefetch, 0x100000);
  242. dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
  243. (pci_prefetch->bus_lower - 1) >> 16);
  244. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  245. #ifdef CONFIG_SYS_PCI_64BIT
  246. dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
  247. (pci_prefetch->bus_lower - 1) >> 32);
  248. #else
  249. dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  250. #endif
  251. }
  252. if (pci_io) {
  253. /* Round I/O allocator to 4KB boundary */
  254. pciauto_region_align(pci_io, 0x1000);
  255. dm_pci_write_config8(dev, PCI_IO_LIMIT,
  256. ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
  257. dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
  258. ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
  259. }
  260. }
  261. /*
  262. * HJF: Changed this to return int. I think this is required
  263. * to get the correct result when scanning bridges
  264. */
  265. int dm_pciauto_config_device(struct udevice *dev)
  266. {
  267. struct pci_region *pci_mem;
  268. struct pci_region *pci_prefetch;
  269. struct pci_region *pci_io;
  270. unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
  271. unsigned short class;
  272. bool enum_only = false;
  273. struct udevice *ctlr = pci_get_controller(dev);
  274. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  275. int n;
  276. #ifdef CONFIG_PCI_ENUM_ONLY
  277. enum_only = true;
  278. #endif
  279. pci_mem = ctlr_hose->pci_mem;
  280. pci_prefetch = ctlr_hose->pci_prefetch;
  281. pci_io = ctlr_hose->pci_io;
  282. dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
  283. switch (class) {
  284. case PCI_CLASS_BRIDGE_PCI:
  285. debug("PCI Autoconfig: Found P2P bridge, device %d\n",
  286. PCI_DEV(dm_pci_get_bdf(dev)));
  287. dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
  288. enum_only);
  289. n = dm_pci_hose_probe_bus(dev);
  290. if (n < 0)
  291. return n;
  292. sub_bus = (unsigned int)n;
  293. break;
  294. case PCI_CLASS_BRIDGE_CARDBUS:
  295. /*
  296. * just do a minimal setup of the bridge,
  297. * let the OS take care of the rest
  298. */
  299. dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
  300. enum_only);
  301. debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
  302. PCI_DEV(dm_pci_get_bdf(dev)));
  303. break;
  304. #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
  305. case PCI_CLASS_BRIDGE_OTHER:
  306. debug("PCI Autoconfig: Skipping bridge device %d\n",
  307. PCI_DEV(dm_pci_get_bdf(dev)));
  308. break;
  309. #endif
  310. #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
  311. !defined(CONFIG_TARGET_CADDY2)
  312. case PCI_CLASS_BRIDGE_OTHER:
  313. /*
  314. * The host/PCI bridge 1 seems broken in 8349 - it presents
  315. * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
  316. * device claiming resources io/mem/irq.. we only allow for
  317. * the PIMMR window to be allocated (BAR0 - 1MB size)
  318. */
  319. debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
  320. dm_pciauto_setup_device(dev, 0, hose->pci_mem,
  321. hose->pci_prefetch, hose->pci_io,
  322. enum_only);
  323. break;
  324. #endif
  325. case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
  326. debug("PCI AutoConfig: Found PowerPC device\n");
  327. /* fall through */
  328. default:
  329. dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
  330. enum_only);
  331. break;
  332. }
  333. return sub_bus;
  334. }