fsl_pci_init.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <malloc.h>
  8. #include <asm/fsl_serdes.h>
  9. DECLARE_GLOBAL_DATA_PTR;
  10. /*
  11. * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  12. *
  13. * Initialize controller and call the common driver/pci pci_hose_scan to
  14. * scan for bridges and devices.
  15. *
  16. * Hose fields which need to be pre-initialized by board specific code:
  17. * regions[]
  18. * first_busno
  19. *
  20. * Fields updated:
  21. * last_busno
  22. */
  23. #include <pci.h>
  24. #include <asm/io.h>
  25. #include <asm/fsl_pci.h>
  26. #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  27. #define CONFIG_SYS_PCI_MEMORY_BUS 0
  28. #endif
  29. #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  30. #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  31. #endif
  32. #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  33. #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  34. #endif
  35. /* Setup one inbound ATMU window.
  36. *
  37. * We let the caller decide what the window size should be
  38. */
  39. static void set_inbound_window(volatile pit_t *pi,
  40. struct pci_region *r,
  41. u64 size)
  42. {
  43. u32 sz = (__ilog2_u64(size) - 1);
  44. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  45. u32 flag = 0;
  46. #else
  47. u32 flag = PIWAR_LOCAL;
  48. #endif
  49. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  50. out_be32(&pi->pitar, r->phys_start >> 12);
  51. out_be32(&pi->piwbar, r->bus_start >> 12);
  52. #ifdef CONFIG_SYS_PCI_64BIT
  53. out_be32(&pi->piwbear, r->bus_start >> 44);
  54. #else
  55. out_be32(&pi->piwbear, 0);
  56. #endif
  57. if (r->flags & PCI_REGION_PREFETCH)
  58. flag |= PIWAR_PF;
  59. out_be32(&pi->piwar, flag | sz);
  60. }
  61. int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
  62. {
  63. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
  64. /* Reset hose to make sure its in a clean state */
  65. memset(hose, 0, sizeof(struct pci_controller));
  66. pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
  67. return fsl_is_pci_agent(hose);
  68. }
  69. static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
  70. u64 out_lo, u8 pcie_cap,
  71. volatile pit_t *pi)
  72. {
  73. struct pci_region *r = hose->regions + hose->region_count;
  74. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  75. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  76. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  77. pci_size_t pci_sz;
  78. /* we have no space available for inbound memory mapping */
  79. if (bus_start > out_lo) {
  80. printf ("no space for inbound mapping of memory\n");
  81. return 0;
  82. }
  83. /* limit size */
  84. if ((bus_start + sz) > out_lo) {
  85. sz = out_lo - bus_start;
  86. debug ("limiting size to %llx\n", sz);
  87. }
  88. pci_sz = 1ull << __ilog2_u64(sz);
  89. /*
  90. * we can overlap inbound/outbound windows on PCI-E since RX & TX
  91. * links a separate
  92. */
  93. if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
  94. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  95. (u64)bus_start, (u64)phys_start, (u64)sz);
  96. pci_set_region(r, bus_start, phys_start, sz,
  97. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  98. PCI_REGION_PREFETCH);
  99. /* if we aren't an exact power of two match, pci_sz is smaller
  100. * round it up to the next power of two. We report the actual
  101. * size to pci region tracking.
  102. */
  103. if (pci_sz != sz)
  104. sz = 2ull << __ilog2_u64(sz);
  105. set_inbound_window(pi--, r++, sz);
  106. sz = 0; /* make sure we dont set the R2 window */
  107. } else {
  108. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  109. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  110. pci_set_region(r, bus_start, phys_start, pci_sz,
  111. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  112. PCI_REGION_PREFETCH);
  113. set_inbound_window(pi--, r++, pci_sz);
  114. sz -= pci_sz;
  115. bus_start += pci_sz;
  116. phys_start += pci_sz;
  117. pci_sz = 1ull << __ilog2_u64(sz);
  118. if (sz) {
  119. debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
  120. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  121. pci_set_region(r, bus_start, phys_start, pci_sz,
  122. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  123. PCI_REGION_PREFETCH);
  124. set_inbound_window(pi--, r++, pci_sz);
  125. sz -= pci_sz;
  126. bus_start += pci_sz;
  127. phys_start += pci_sz;
  128. }
  129. }
  130. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  131. /*
  132. * On 64-bit capable systems, set up a mapping for all of DRAM
  133. * in high pci address space.
  134. */
  135. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  136. /* round up to the next largest power of two */
  137. if (gd->ram_size > pci_sz)
  138. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  139. debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
  140. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  141. (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
  142. (u64)pci_sz);
  143. pci_set_region(r,
  144. CONFIG_SYS_PCI64_MEMORY_BUS,
  145. CONFIG_SYS_PCI_MEMORY_PHYS,
  146. pci_sz,
  147. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  148. PCI_REGION_PREFETCH);
  149. set_inbound_window(pi--, r++, pci_sz);
  150. #else
  151. pci_sz = 1ull << __ilog2_u64(sz);
  152. if (sz) {
  153. debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
  154. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  155. pci_set_region(r, bus_start, phys_start, pci_sz,
  156. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  157. PCI_REGION_PREFETCH);
  158. sz -= pci_sz;
  159. bus_start += pci_sz;
  160. phys_start += pci_sz;
  161. set_inbound_window(pi--, r++, pci_sz);
  162. }
  163. #endif
  164. #ifdef CONFIG_PHYS_64BIT
  165. if (sz && (((u64)gd->ram_size) < (1ull << 32)))
  166. printf("Was not able to map all of memory via "
  167. "inbound windows -- %lld remaining\n", sz);
  168. #endif
  169. hose->region_count = r - hose->regions;
  170. return 1;
  171. }
  172. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  173. static void fsl_pcie_boot_master(pit_t *pi)
  174. {
  175. /* configure inbound window for slave's u-boot image */
  176. debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
  177. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  178. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  179. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  180. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  181. struct pci_region r_inbound;
  182. u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
  183. - 1;
  184. pci_set_region(&r_inbound,
  185. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  186. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  187. sz_inbound,
  188. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  189. set_inbound_window(pi--, &r_inbound,
  190. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  191. /* configure inbound window for slave's u-boot image */
  192. debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
  193. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  194. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  195. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  196. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  197. pci_set_region(&r_inbound,
  198. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  199. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  200. sz_inbound,
  201. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  202. set_inbound_window(pi--, &r_inbound,
  203. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  204. /* configure inbound window for slave's ucode and ENV */
  205. debug("PCIEBOOT - MASTER: Inbound window for slave's "
  206. "ucode and ENV; "
  207. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  208. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  209. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  210. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  211. sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
  212. - 1;
  213. pci_set_region(&r_inbound,
  214. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  215. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  216. sz_inbound,
  217. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  218. set_inbound_window(pi--, &r_inbound,
  219. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  220. }
  221. static void fsl_pcie_boot_master_release_slave(int port)
  222. {
  223. unsigned long release_addr;
  224. /* now release slave's core 0 */
  225. switch (port) {
  226. case 1:
  227. release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
  228. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  229. break;
  230. #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
  231. case 2:
  232. release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
  233. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  234. break;
  235. #endif
  236. #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
  237. case 3:
  238. release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
  239. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  240. break;
  241. #endif
  242. default:
  243. release_addr = 0;
  244. break;
  245. }
  246. if (release_addr != 0) {
  247. out_be32((void *)release_addr,
  248. CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
  249. debug("PCIEBOOT - MASTER: "
  250. "Release slave successfully! Now the slave should start up!\n");
  251. } else {
  252. debug("PCIEBOOT - MASTER: "
  253. "Release slave failed!\n");
  254. }
  255. }
  256. #endif
  257. void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
  258. {
  259. u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
  260. u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
  261. u16 temp16;
  262. u32 temp32;
  263. u32 block_rev;
  264. int enabled, r, inbound = 0;
  265. u16 ltssm;
  266. u8 temp8, pcie_cap;
  267. int pcie_cap_pos;
  268. int pci_dcr;
  269. int pci_dsr;
  270. int pci_lsr;
  271. #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
  272. int pci_lcr;
  273. #endif
  274. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
  275. struct pci_region *reg = hose->regions + hose->region_count;
  276. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  277. /* Initialize ATMU registers based on hose regions and flags */
  278. volatile pot_t *po = &pci->pot[1]; /* skip 0 */
  279. volatile pit_t *pi;
  280. u64 out_hi = 0, out_lo = -1ULL;
  281. u32 pcicsrbar, pcicsrbar_sz;
  282. pci_setup_indirect(hose, cfg_addr, cfg_data);
  283. #ifdef PEX_CCB_DIV
  284. /* Configure the PCIE controller core clock ratio */
  285. pci_hose_write_config_dword(hose, dev, 0x440,
  286. ((gd->bus_clk / 1000000) *
  287. (16 / PEX_CCB_DIV)) / 333);
  288. #endif
  289. block_rev = in_be32(&pci->block_rev1);
  290. if (PEX_IP_BLK_REV_2_2 <= block_rev) {
  291. pi = &pci->pit[2]; /* 0xDC0 */
  292. } else {
  293. pi = &pci->pit[3]; /* 0xDE0 */
  294. }
  295. /* Handle setup of outbound windows first */
  296. for (r = 0; r < hose->region_count; r++) {
  297. unsigned long flags = hose->regions[r].flags;
  298. u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
  299. flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
  300. if (flags != PCI_REGION_SYS_MEMORY) {
  301. u64 start = hose->regions[r].bus_start;
  302. u64 end = start + hose->regions[r].size;
  303. out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
  304. out_be32(&po->potar, start >> 12);
  305. #ifdef CONFIG_SYS_PCI_64BIT
  306. out_be32(&po->potear, start >> 44);
  307. #else
  308. out_be32(&po->potear, 0);
  309. #endif
  310. if (hose->regions[r].flags & PCI_REGION_IO) {
  311. out_be32(&po->powar, POWAR_EN | sz |
  312. POWAR_IO_READ | POWAR_IO_WRITE);
  313. } else {
  314. out_be32(&po->powar, POWAR_EN | sz |
  315. POWAR_MEM_READ | POWAR_MEM_WRITE);
  316. out_lo = min(start, out_lo);
  317. out_hi = max(end, out_hi);
  318. }
  319. po++;
  320. }
  321. }
  322. debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
  323. /* setup PCSRBAR/PEXCSRBAR */
  324. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
  325. pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
  326. pcicsrbar_sz = ~pcicsrbar_sz + 1;
  327. if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
  328. (out_lo > 0x100000000ull))
  329. pcicsrbar = 0x100000000ull - pcicsrbar_sz;
  330. else
  331. pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
  332. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
  333. out_lo = min(out_lo, (u64)pcicsrbar);
  334. debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
  335. pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
  336. pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
  337. hose->region_count++;
  338. /* see if we are a PCIe or PCI controller */
  339. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  340. pci_dcr = pcie_cap_pos + 0x08;
  341. pci_dsr = pcie_cap_pos + 0x0a;
  342. pci_lsr = pcie_cap_pos + 0x12;
  343. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  344. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  345. /* boot from PCIE --master */
  346. char *s = env_get("bootmaster");
  347. char pcie[6];
  348. sprintf(pcie, "PCIE%d", pci_info->pci_num);
  349. if (s && (strcmp(s, pcie) == 0)) {
  350. debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
  351. pci_info->pci_num);
  352. fsl_pcie_boot_master((pit_t *)pi);
  353. } else {
  354. /* inbound */
  355. inbound = fsl_pci_setup_inbound_windows(hose,
  356. out_lo, pcie_cap, pi);
  357. }
  358. #else
  359. /* inbound */
  360. inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
  361. #endif
  362. for (r = 0; r < hose->region_count; r++)
  363. debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
  364. (u64)hose->regions[r].phys_start,
  365. (u64)hose->regions[r].bus_start,
  366. (u64)hose->regions[r].size,
  367. hose->regions[r].flags);
  368. pci_register_hose(hose);
  369. pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
  370. hose->current_busno = hose->first_busno;
  371. out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
  372. out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
  373. * - Master abort (pci)
  374. * - Master PERR (pci)
  375. * - ICCA (PCIe)
  376. */
  377. pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
  378. temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
  379. pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
  380. #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
  381. pci_lcr = pcie_cap_pos + 0x10;
  382. temp32 = 0;
  383. pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
  384. temp32 &= ~0x03; /* Disable ASPM */
  385. pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
  386. udelay(1);
  387. #endif
  388. if (pcie_cap == PCI_CAP_ID_EXP) {
  389. if (block_rev >= PEX_IP_BLK_REV_3_0) {
  390. #define PEX_CSR0_LTSSM_MASK 0xFC
  391. #define PEX_CSR0_LTSSM_SHIFT 2
  392. ltssm = (in_be32(&pci->pex_csr0)
  393. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  394. enabled = (ltssm == 0x11) ? 1 : 0;
  395. #ifdef CONFIG_FSL_PCIE_RESET
  396. int i;
  397. /* assert PCIe reset */
  398. setbits_be32(&pci->pdb_stat, 0x08000000);
  399. (void) in_be32(&pci->pdb_stat);
  400. udelay(1000);
  401. /* clear PCIe reset */
  402. clrbits_be32(&pci->pdb_stat, 0x08000000);
  403. asm("sync;isync");
  404. for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  405. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  406. &ltssm);
  407. udelay(1000);
  408. }
  409. #endif
  410. } else {
  411. /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
  412. /* enabled = ltssm >= PCI_LTSSM_L0; */
  413. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  414. enabled = ltssm >= PCI_LTSSM_L0;
  415. #ifdef CONFIG_FSL_PCIE_RESET
  416. if (ltssm == 1) {
  417. int i;
  418. debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
  419. /* assert PCIe reset */
  420. setbits_be32(&pci->pdb_stat, 0x08000000);
  421. (void) in_be32(&pci->pdb_stat);
  422. udelay(100);
  423. debug(" Asserting PCIe reset @%p = %x\n",
  424. &pci->pdb_stat, in_be32(&pci->pdb_stat));
  425. /* clear PCIe reset */
  426. clrbits_be32(&pci->pdb_stat, 0x08000000);
  427. asm("sync;isync");
  428. for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
  429. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  430. &ltssm);
  431. udelay(1000);
  432. debug("....PCIe link error. "
  433. "LTSSM=0x%02x.\n", ltssm);
  434. }
  435. enabled = ltssm >= PCI_LTSSM_L0;
  436. /* we need to re-write the bar0 since a reset will
  437. * clear it
  438. */
  439. pci_hose_write_config_dword(hose, dev,
  440. PCI_BASE_ADDRESS_0, pcicsrbar);
  441. }
  442. #endif
  443. }
  444. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  445. if (enabled == 0) {
  446. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  447. temp32 = in_be32(&srds_regs->srdspccr0);
  448. if ((temp32 >> 28) == 3) {
  449. int i;
  450. out_be32(&srds_regs->srdspccr0, 2 << 28);
  451. setbits_be32(&pci->pdb_stat, 0x08000000);
  452. in_be32(&pci->pdb_stat);
  453. udelay(100);
  454. clrbits_be32(&pci->pdb_stat, 0x08000000);
  455. asm("sync;isync");
  456. for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  457. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  458. udelay(1000);
  459. }
  460. enabled = ltssm >= PCI_LTSSM_L0;
  461. }
  462. }
  463. #endif
  464. if (!enabled) {
  465. /* Let the user know there's no PCIe link for root
  466. * complex. for endpoint, the link may not setup, so
  467. * print undetermined.
  468. */
  469. if (fsl_is_pci_agent(hose))
  470. printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
  471. else
  472. printf("no link, regs @ 0x%lx\n", pci_info->regs);
  473. hose->last_busno = hose->first_busno;
  474. return;
  475. }
  476. out_be32(&pci->pme_msg_det, 0xffffffff);
  477. out_be32(&pci->pme_msg_int_en, 0xffffffff);
  478. /* Print the negotiated PCIe link width */
  479. pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
  480. printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
  481. (temp16 & 0xf), pci_info->regs);
  482. hose->current_busno++; /* Start scan with secondary */
  483. pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
  484. }
  485. #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
  486. /* The Read-Only Write Enable bit defaults to 1 instead of 0.
  487. * Set to 0 to protect the read-only registers.
  488. */
  489. clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
  490. #endif
  491. /* Use generic setup_device to initialize standard pci regs,
  492. * but do not allocate any windows since any BAR found (such
  493. * as PCSRBAR) is not in this cpu's memory space.
  494. */
  495. pciauto_setup_device(hose, dev, 0, hose->pci_mem,
  496. hose->pci_prefetch, hose->pci_io);
  497. if (inbound) {
  498. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
  499. pci_hose_write_config_word(hose, dev, PCI_COMMAND,
  500. temp16 | PCI_COMMAND_MEMORY);
  501. }
  502. #ifndef CONFIG_PCI_NOSCAN
  503. if (!fsl_is_pci_agent(hose)) {
  504. debug(" Scanning PCI bus %02x\n",
  505. hose->current_busno);
  506. hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
  507. } else {
  508. debug(" Not scanning PCI bus %02x. PI=%x\n",
  509. hose->current_busno, temp8);
  510. hose->last_busno = hose->current_busno;
  511. }
  512. /* if we are PCIe - update limit regs and subordinate busno
  513. * for the virtual P2P bridge
  514. */
  515. if (pcie_cap == PCI_CAP_ID_EXP) {
  516. pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
  517. }
  518. #else
  519. hose->last_busno = hose->current_busno;
  520. #endif
  521. /* Clear all error indications */
  522. if (pcie_cap == PCI_CAP_ID_EXP)
  523. out_be32(&pci->pme_msg_det, 0xffffffff);
  524. out_be32(&pci->pedr, 0xffffffff);
  525. pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
  526. if (temp16) {
  527. pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
  528. }
  529. pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
  530. if (temp16) {
  531. pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
  532. }
  533. }
  534. int fsl_is_pci_agent(struct pci_controller *hose)
  535. {
  536. int pcie_cap_pos;
  537. u8 pcie_cap;
  538. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  539. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  540. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  541. if (pcie_cap == PCI_CAP_ID_EXP) {
  542. u8 header_type;
  543. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
  544. &header_type);
  545. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  546. } else {
  547. u8 prog_if;
  548. pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
  549. /* Programming Interface (PCI_CLASS_PROG)
  550. * 0 == pci host or pcie root-complex,
  551. * 1 == pci agent or pcie end-point
  552. */
  553. return (prog_if == FSL_PROG_IF_AGENT);
  554. }
  555. }
  556. int fsl_pci_init_port(struct fsl_pci_info *pci_info,
  557. struct pci_controller *hose, int busno)
  558. {
  559. volatile ccsr_fsl_pci_t *pci;
  560. struct pci_region *r;
  561. pci_dev_t dev = PCI_BDF(busno,0,0);
  562. int pcie_cap_pos;
  563. u8 pcie_cap;
  564. pci = (ccsr_fsl_pci_t *) pci_info->regs;
  565. /* on non-PCIe controllers we don't have pme_msg_det so this code
  566. * should do nothing since the read will return 0
  567. */
  568. if (in_be32(&pci->pme_msg_det)) {
  569. out_be32(&pci->pme_msg_det, 0xffffffff);
  570. debug (" with errors. Clearing. Now 0x%08x",
  571. pci->pme_msg_det);
  572. }
  573. r = hose->regions + hose->region_count;
  574. /* outbound memory */
  575. pci_set_region(r++,
  576. pci_info->mem_bus,
  577. pci_info->mem_phys,
  578. pci_info->mem_size,
  579. PCI_REGION_MEM);
  580. /* outbound io */
  581. pci_set_region(r++,
  582. pci_info->io_bus,
  583. pci_info->io_phys,
  584. pci_info->io_size,
  585. PCI_REGION_IO);
  586. hose->region_count = r - hose->regions;
  587. hose->first_busno = busno;
  588. fsl_pci_init(hose, pci_info);
  589. if (fsl_is_pci_agent(hose)) {
  590. fsl_pci_config_unlock(hose);
  591. hose->last_busno = hose->first_busno;
  592. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  593. } else {
  594. /* boot from PCIE --master releases slave's core 0 */
  595. char *s = env_get("bootmaster");
  596. char pcie[6];
  597. sprintf(pcie, "PCIE%d", pci_info->pci_num);
  598. if (s && (strcmp(s, pcie) == 0))
  599. fsl_pcie_boot_master_release_slave(pci_info->pci_num);
  600. #endif
  601. }
  602. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  603. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  604. printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
  605. "e" : "", pci_info->pci_num,
  606. hose->first_busno, hose->last_busno);
  607. return(hose->last_busno + 1);
  608. }
  609. /* Enable inbound PCI config cycles for agent/endpoint interface */
  610. void fsl_pci_config_unlock(struct pci_controller *hose)
  611. {
  612. pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
  613. int pcie_cap_pos;
  614. u8 pcie_cap;
  615. u16 pbfr;
  616. if (!fsl_is_pci_agent(hose))
  617. return;
  618. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  619. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  620. if (pcie_cap != 0x0) {
  621. ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
  622. u32 block_rev = in_be32(&pci->block_rev1);
  623. /* PCIe - set CFG_READY bit of Configuration Ready Register */
  624. if (block_rev >= PEX_IP_BLK_REV_3_0)
  625. setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
  626. else
  627. pci_hose_write_config_byte(hose, dev,
  628. FSL_PCIE_CFG_RDY, 0x1);
  629. } else {
  630. /* PCI - clear ACL bit of PBFR */
  631. pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
  632. pbfr &= ~0x20;
  633. pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
  634. }
  635. }
  636. #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
  637. defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
  638. int fsl_configure_pcie(struct fsl_pci_info *info,
  639. struct pci_controller *hose,
  640. const char *connected, int busno)
  641. {
  642. int is_endpoint;
  643. set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
  644. set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
  645. is_endpoint = fsl_setup_hose(hose, info->regs);
  646. printf("PCIe%u: %s", info->pci_num,
  647. is_endpoint ? "Endpoint" : "Root Complex");
  648. if (connected)
  649. printf(" of %s", connected);
  650. puts(", ");
  651. return fsl_pci_init_port(info, hose, busno);
  652. }
  653. #if defined(CONFIG_FSL_CORENET)
  654. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  655. #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
  656. #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
  657. #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
  658. #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
  659. #else
  660. #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
  661. #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
  662. #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
  663. #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
  664. #endif
  665. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  666. #elif defined(CONFIG_MPC85xx)
  667. #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
  668. #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
  669. #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
  670. #define _DEVDISR_PCIE4 0
  671. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  672. #elif defined(CONFIG_MPC86xx)
  673. #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
  674. #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
  675. #define _DEVDISR_PCIE3 0
  676. #define _DEVDISR_PCIE4 0
  677. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
  678. (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
  679. #else
  680. #error "No defines for DEVDISR_PCIE"
  681. #endif
  682. /* Implement a dummy function for those platforms w/o SERDES */
  683. static const char *__board_serdes_name(enum srds_prtcl device)
  684. {
  685. switch (device) {
  686. #ifdef CONFIG_SYS_PCIE1_NAME
  687. case PCIE1:
  688. return CONFIG_SYS_PCIE1_NAME;
  689. #endif
  690. #ifdef CONFIG_SYS_PCIE2_NAME
  691. case PCIE2:
  692. return CONFIG_SYS_PCIE2_NAME;
  693. #endif
  694. #ifdef CONFIG_SYS_PCIE3_NAME
  695. case PCIE3:
  696. return CONFIG_SYS_PCIE3_NAME;
  697. #endif
  698. #ifdef CONFIG_SYS_PCIE4_NAME
  699. case PCIE4:
  700. return CONFIG_SYS_PCIE4_NAME;
  701. #endif
  702. default:
  703. return NULL;
  704. }
  705. return NULL;
  706. }
  707. __attribute__((weak, alias("__board_serdes_name"))) const char *
  708. board_serdes_name(enum srds_prtcl device);
  709. static u32 devdisr_mask[] = {
  710. _DEVDISR_PCIE1,
  711. _DEVDISR_PCIE2,
  712. _DEVDISR_PCIE3,
  713. _DEVDISR_PCIE4,
  714. };
  715. int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
  716. struct fsl_pci_info *pci_info)
  717. {
  718. struct pci_controller *hose;
  719. int num = dev - PCIE1;
  720. hose = calloc(1, sizeof(struct pci_controller));
  721. if (!hose)
  722. return busno;
  723. if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
  724. busno = fsl_configure_pcie(pci_info, hose,
  725. board_serdes_name(dev), busno);
  726. } else {
  727. printf("PCIe%d: disabled\n", num + 1);
  728. }
  729. return busno;
  730. }
  731. int fsl_pcie_init_board(int busno)
  732. {
  733. struct fsl_pci_info pci_info;
  734. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
  735. u32 devdisr;
  736. u32 *addr;
  737. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  738. addr = &gur->devdisr3;
  739. #else
  740. addr = &gur->devdisr;
  741. #endif
  742. devdisr = in_be32(addr);
  743. #ifdef CONFIG_PCIE1
  744. SET_STD_PCIE_INFO(pci_info, 1);
  745. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
  746. #else
  747. setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
  748. #endif
  749. #ifdef CONFIG_PCIE2
  750. SET_STD_PCIE_INFO(pci_info, 2);
  751. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
  752. #else
  753. setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
  754. #endif
  755. #ifdef CONFIG_PCIE3
  756. SET_STD_PCIE_INFO(pci_info, 3);
  757. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
  758. #else
  759. setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
  760. #endif
  761. #ifdef CONFIG_PCIE4
  762. SET_STD_PCIE_INFO(pci_info, 4);
  763. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
  764. #else
  765. setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
  766. #endif
  767. return busno;
  768. }
  769. #else
  770. int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
  771. struct fsl_pci_info *pci_info)
  772. {
  773. return busno;
  774. }
  775. int fsl_pcie_init_board(int busno)
  776. {
  777. return busno;
  778. }
  779. #endif
  780. #ifdef CONFIG_OF_BOARD_SETUP
  781. #include <linux/libfdt.h>
  782. #include <fdt_support.h>
  783. void ft_fsl_pci_setup(void *blob, const char *pci_compat,
  784. unsigned long ctrl_addr)
  785. {
  786. int off;
  787. u32 bus_range[2];
  788. phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
  789. struct pci_controller *hose;
  790. hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
  791. /* convert ctrl_addr to true physical address */
  792. p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
  793. p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
  794. off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
  795. if (off < 0)
  796. return;
  797. /* We assume a cfg_addr not being set means we didn't setup the controller */
  798. if ((hose == NULL) || (hose->cfg_addr == NULL)) {
  799. fdt_del_node(blob, off);
  800. } else {
  801. bus_range[0] = 0;
  802. bus_range[1] = hose->last_busno - hose->first_busno;
  803. fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
  804. fdt_pci_dma_ranges(blob, off, hose);
  805. }
  806. }
  807. #endif