tegra_mmc.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 SAMSUNG Electronics
  4. * Minkyu Kang <mk7.kang@samsung.com>
  5. * Jaehoon Chung <jh80.chung@samsung.com>
  6. * Portions Copyright 2011-2019 NVIDIA Corporation
  7. */
  8. #include <bouncebuf.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <mmc.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-tegra/tegra_mmc.h>
  16. #include <linux/err.h>
  17. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  18. #include <asm/arch/clock.h>
  19. #endif
  20. struct tegra_mmc_plat {
  21. struct mmc_config cfg;
  22. struct mmc mmc;
  23. };
  24. struct tegra_mmc_priv {
  25. struct tegra_mmc *reg;
  26. struct reset_ctl reset_ctl;
  27. struct clk clk;
  28. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  29. struct gpio_desc pwr_gpio; /* Power GPIO */
  30. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  31. unsigned int version; /* SDHCI spec. version */
  32. unsigned int clock; /* Current clock (MHz) */
  33. int mmc_id; /* peripheral id */
  34. };
  35. static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  36. unsigned short power)
  37. {
  38. u8 pwr = 0;
  39. debug("%s: power = %x\n", __func__, power);
  40. if (power != (unsigned short)-1) {
  41. switch (1 << power) {
  42. case MMC_VDD_165_195:
  43. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  44. break;
  45. case MMC_VDD_29_30:
  46. case MMC_VDD_30_31:
  47. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  48. break;
  49. case MMC_VDD_32_33:
  50. case MMC_VDD_33_34:
  51. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  52. break;
  53. }
  54. }
  55. debug("%s: pwr = %X\n", __func__, pwr);
  56. /* Set the bus voltage first (if any) */
  57. writeb(pwr, &priv->reg->pwrcon);
  58. if (pwr == 0)
  59. return;
  60. /* Now enable bus power */
  61. pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  62. writeb(pwr, &priv->reg->pwrcon);
  63. }
  64. static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  65. struct mmc_data *data,
  66. struct bounce_buffer *bbstate)
  67. {
  68. unsigned char ctrl;
  69. debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  70. bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  71. data->blocksize);
  72. writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  73. /*
  74. * DMASEL[4:3]
  75. * 00 = Selects SDMA
  76. * 01 = Reserved
  77. * 10 = Selects 32-bit Address ADMA2
  78. * 11 = Selects 64-bit Address ADMA2
  79. */
  80. ctrl = readb(&priv->reg->hostctl);
  81. ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  82. ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  83. writeb(ctrl, &priv->reg->hostctl);
  84. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  85. writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
  86. writew(data->blocks, &priv->reg->blkcnt);
  87. }
  88. static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
  89. struct mmc_data *data)
  90. {
  91. unsigned short mode;
  92. debug(" mmc_set_transfer_mode called\n");
  93. /*
  94. * TRNMOD
  95. * MUL1SIN0[5] : Multi/Single Block Select
  96. * RD1WT0[4] : Data Transfer Direction Select
  97. * 1 = read
  98. * 0 = write
  99. * ENACMD12[2] : Auto CMD12 Enable
  100. * ENBLKCNT[1] : Block Count Enable
  101. * ENDMA[0] : DMA Enable
  102. */
  103. mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
  104. TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
  105. if (data->blocks > 1)
  106. mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
  107. if (data->flags & MMC_DATA_READ)
  108. mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
  109. writew(mode, &priv->reg->trnmod);
  110. }
  111. static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
  112. struct mmc_cmd *cmd,
  113. struct mmc_data *data,
  114. unsigned int timeout)
  115. {
  116. /*
  117. * PRNSTS
  118. * CMDINHDAT[1] : Command Inhibit (DAT)
  119. * CMDINHCMD[0] : Command Inhibit (CMD)
  120. */
  121. unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
  122. /*
  123. * We shouldn't wait for data inhibit for stop commands, even
  124. * though they might use busy signaling
  125. */
  126. if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
  127. mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
  128. while (readl(&priv->reg->prnsts) & mask) {
  129. if (timeout == 0) {
  130. printf("%s: timeout error\n", __func__);
  131. return -1;
  132. }
  133. timeout--;
  134. udelay(1000);
  135. }
  136. return 0;
  137. }
  138. static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
  139. struct mmc_data *data,
  140. struct bounce_buffer *bbstate)
  141. {
  142. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  143. int flags, i;
  144. int result;
  145. unsigned int mask = 0;
  146. unsigned int retry = 0x100000;
  147. debug(" mmc_send_cmd called\n");
  148. result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
  149. if (result < 0)
  150. return result;
  151. if (data)
  152. tegra_mmc_prepare_data(priv, data, bbstate);
  153. debug("cmd->arg: %08x\n", cmd->cmdarg);
  154. writel(cmd->cmdarg, &priv->reg->argument);
  155. if (data)
  156. tegra_mmc_set_transfer_mode(priv, data);
  157. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  158. return -1;
  159. /*
  160. * CMDREG
  161. * CMDIDX[13:8] : Command index
  162. * DATAPRNT[5] : Data Present Select
  163. * ENCMDIDX[4] : Command Index Check Enable
  164. * ENCMDCRC[3] : Command CRC Check Enable
  165. * RSPTYP[1:0]
  166. * 00 = No Response
  167. * 01 = Length 136
  168. * 10 = Length 48
  169. * 11 = Length 48 Check busy after response
  170. */
  171. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  172. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
  173. else if (cmd->resp_type & MMC_RSP_136)
  174. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
  175. else if (cmd->resp_type & MMC_RSP_BUSY)
  176. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
  177. else
  178. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
  179. if (cmd->resp_type & MMC_RSP_CRC)
  180. flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
  181. if (cmd->resp_type & MMC_RSP_OPCODE)
  182. flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
  183. if (data)
  184. flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
  185. debug("cmd: %d\n", cmd->cmdidx);
  186. writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
  187. for (i = 0; i < retry; i++) {
  188. mask = readl(&priv->reg->norintsts);
  189. /* Command Complete */
  190. if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
  191. if (!data)
  192. writel(mask, &priv->reg->norintsts);
  193. break;
  194. }
  195. }
  196. if (i == retry) {
  197. printf("%s: waiting for status update\n", __func__);
  198. writel(mask, &priv->reg->norintsts);
  199. return -ETIMEDOUT;
  200. }
  201. if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
  202. /* Timeout Error */
  203. debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
  204. writel(mask, &priv->reg->norintsts);
  205. return -ETIMEDOUT;
  206. } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  207. /* Error Interrupt */
  208. debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
  209. writel(mask, &priv->reg->norintsts);
  210. return -1;
  211. }
  212. if (cmd->resp_type & MMC_RSP_PRESENT) {
  213. if (cmd->resp_type & MMC_RSP_136) {
  214. /* CRC is stripped so we need to do some shifting. */
  215. for (i = 0; i < 4; i++) {
  216. unsigned long offset = (unsigned long)
  217. (&priv->reg->rspreg3 - i);
  218. cmd->response[i] = readl(offset) << 8;
  219. if (i != 3) {
  220. cmd->response[i] |=
  221. readb(offset - 1);
  222. }
  223. debug("cmd->resp[%d]: %08x\n",
  224. i, cmd->response[i]);
  225. }
  226. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  227. for (i = 0; i < retry; i++) {
  228. /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
  229. if (readl(&priv->reg->prnsts)
  230. & (1 << 20)) /* DAT[0] */
  231. break;
  232. }
  233. if (i == retry) {
  234. printf("%s: card is still busy\n", __func__);
  235. writel(mask, &priv->reg->norintsts);
  236. return -ETIMEDOUT;
  237. }
  238. cmd->response[0] = readl(&priv->reg->rspreg0);
  239. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  240. } else {
  241. cmd->response[0] = readl(&priv->reg->rspreg0);
  242. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  243. }
  244. }
  245. if (data) {
  246. unsigned long start = get_timer(0);
  247. while (1) {
  248. mask = readl(&priv->reg->norintsts);
  249. if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  250. /* Error Interrupt */
  251. writel(mask, &priv->reg->norintsts);
  252. printf("%s: error during transfer: 0x%08x\n",
  253. __func__, mask);
  254. return -1;
  255. } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
  256. /*
  257. * DMA Interrupt, restart the transfer where
  258. * it was interrupted.
  259. */
  260. unsigned int address = readl(&priv->reg->sysad);
  261. debug("DMA end\n");
  262. writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
  263. &priv->reg->norintsts);
  264. writel(address, &priv->reg->sysad);
  265. } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
  266. /* Transfer Complete */
  267. debug("r/w is done\n");
  268. break;
  269. } else if (get_timer(start) > 8000UL) {
  270. writel(mask, &priv->reg->norintsts);
  271. printf("%s: MMC Timeout\n"
  272. " Interrupt status 0x%08x\n"
  273. " Interrupt status enable 0x%08x\n"
  274. " Interrupt signal enable 0x%08x\n"
  275. " Present status 0x%08x\n",
  276. __func__, mask,
  277. readl(&priv->reg->norintstsen),
  278. readl(&priv->reg->norintsigen),
  279. readl(&priv->reg->prnsts));
  280. return -1;
  281. }
  282. }
  283. writel(mask, &priv->reg->norintsts);
  284. }
  285. udelay(1000);
  286. return 0;
  287. }
  288. static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  289. struct mmc_data *data)
  290. {
  291. void *buf;
  292. unsigned int bbflags;
  293. size_t len;
  294. struct bounce_buffer bbstate;
  295. int ret;
  296. if (data) {
  297. if (data->flags & MMC_DATA_READ) {
  298. buf = data->dest;
  299. bbflags = GEN_BB_WRITE;
  300. } else {
  301. buf = (void *)data->src;
  302. bbflags = GEN_BB_READ;
  303. }
  304. len = data->blocks * data->blocksize;
  305. bounce_buffer_start(&bbstate, buf, len, bbflags);
  306. }
  307. ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
  308. if (data)
  309. bounce_buffer_stop(&bbstate);
  310. return ret;
  311. }
  312. static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
  313. {
  314. ulong rate;
  315. int div;
  316. unsigned short clk;
  317. unsigned long timeout;
  318. debug(" mmc_change_clock called\n");
  319. /*
  320. * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
  321. */
  322. if (clock == 0)
  323. goto out;
  324. rate = clk_set_rate(&priv->clk, clock);
  325. div = (rate + clock - 1) / clock;
  326. #if defined(CONFIG_TEGRA210)
  327. if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
  328. /* clock_adjust_periph_pll_div() chooses a 'bad' clock
  329. * on SDMMC1 T210, so skip it here and force a clock
  330. * that's been spec'd in the table in the TRM for
  331. * card-detect (400KHz).
  332. */
  333. uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
  334. CLOCK_ID_PERIPH, 24727273, NULL);
  335. div = 62;
  336. debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
  337. __func__, effective_rate, div, clock);
  338. } else {
  339. clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
  340. clock, &div);
  341. }
  342. #endif
  343. debug("div = %d\n", div);
  344. writew(0, &priv->reg->clkcon);
  345. /*
  346. * CLKCON
  347. * SELFREQ[15:8] : base clock divided by value
  348. * ENSDCLK[2] : SD Clock Enable
  349. * STBLINTCLK[1] : Internal Clock Stable
  350. * ENINTCLK[0] : Internal Clock Enable
  351. */
  352. div >>= 1;
  353. clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
  354. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
  355. writew(clk, &priv->reg->clkcon);
  356. /* Wait max 10 ms */
  357. timeout = 10;
  358. while (!(readw(&priv->reg->clkcon) &
  359. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
  360. if (timeout == 0) {
  361. printf("%s: timeout error\n", __func__);
  362. return;
  363. }
  364. timeout--;
  365. udelay(1000);
  366. }
  367. clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  368. writew(clk, &priv->reg->clkcon);
  369. debug("mmc_change_clock: clkcon = %08X\n", clk);
  370. out:
  371. priv->clock = clock;
  372. }
  373. static int tegra_mmc_set_ios(struct udevice *dev)
  374. {
  375. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  376. struct mmc *mmc = mmc_get_mmc_dev(dev);
  377. unsigned char ctrl;
  378. debug(" mmc_set_ios called\n");
  379. debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
  380. /* Change clock first */
  381. tegra_mmc_change_clock(priv, mmc->clock);
  382. ctrl = readb(&priv->reg->hostctl);
  383. /*
  384. * WIDE8[5]
  385. * 0 = Depend on WIDE4
  386. * 1 = 8-bit mode
  387. * WIDE4[1]
  388. * 1 = 4-bit mode
  389. * 0 = 1-bit mode
  390. */
  391. if (mmc->bus_width == 8)
  392. ctrl |= (1 << 5);
  393. else if (mmc->bus_width == 4)
  394. ctrl |= (1 << 1);
  395. else
  396. ctrl &= ~(1 << 1 | 1 << 5);
  397. writeb(ctrl, &priv->reg->hostctl);
  398. debug("mmc_set_ios: hostctl = %08X\n", ctrl);
  399. return 0;
  400. }
  401. static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
  402. {
  403. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  404. u32 val;
  405. u16 clk_con;
  406. int timeout;
  407. int id = priv->mmc_id;
  408. debug("%s: sdmmc address = %p, id = %d\n", __func__,
  409. priv->reg, id);
  410. /* Set the pad drive strength for SDMMC1 or 3 only */
  411. if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
  412. debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
  413. __func__);
  414. return;
  415. }
  416. val = readl(&priv->reg->sdmemcmppadctl);
  417. val &= 0xFFFFFFF0;
  418. val |= MEMCOMP_PADCTRL_VREF;
  419. writel(val, &priv->reg->sdmemcmppadctl);
  420. /* Disable SD Clock Enable before running auto-cal as per TRM */
  421. clk_con = readw(&priv->reg->clkcon);
  422. debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
  423. clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  424. writew(clk_con, &priv->reg->clkcon);
  425. val = readl(&priv->reg->autocalcfg);
  426. val &= 0xFFFF0000;
  427. val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
  428. writel(val, &priv->reg->autocalcfg);
  429. val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
  430. writel(val, &priv->reg->autocalcfg);
  431. debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
  432. udelay(1);
  433. timeout = 100; /* 10 mSec max (100*100uS) */
  434. do {
  435. val = readl(&priv->reg->autocalsts);
  436. udelay(100);
  437. } while ((val & AUTO_CAL_ACTIVE) && --timeout);
  438. val = readl(&priv->reg->autocalsts);
  439. debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
  440. __func__, val, timeout);
  441. /* Re-enable SD Clock Enable when auto-cal is done */
  442. clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  443. writew(clk_con, &priv->reg->clkcon);
  444. clk_con = readw(&priv->reg->clkcon);
  445. debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
  446. if (timeout == 0) {
  447. printf("%s: Warning: Autocal timed out!\n", __func__);
  448. /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
  449. }
  450. #if defined(CONFIG_TEGRA210)
  451. u32 tap_value, trim_value;
  452. /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
  453. val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
  454. val &= IO_TRIM_BYPASS_MASK;
  455. if (id == PERIPH_ID_SDMMC1) {
  456. tap_value = 4; /* default */
  457. if (val)
  458. tap_value = 3;
  459. trim_value = 2;
  460. } else { /* SDMMC3 */
  461. tap_value = 3;
  462. trim_value = 3;
  463. }
  464. val = readl(&priv->reg->venclkctl);
  465. val &= ~TRIM_VAL_MASK;
  466. val |= (trim_value << TRIM_VAL_SHIFT);
  467. val &= ~TAP_VAL_MASK;
  468. val |= (tap_value << TAP_VAL_SHIFT);
  469. writel(val, &priv->reg->venclkctl);
  470. debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
  471. #endif /* T210 */
  472. #endif /* T30/T210 */
  473. }
  474. static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
  475. {
  476. unsigned int timeout;
  477. debug(" mmc_reset called\n");
  478. /*
  479. * RSTALL[0] : Software reset for all
  480. * 1 = reset
  481. * 0 = work
  482. */
  483. writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
  484. priv->clock = 0;
  485. /* Wait max 100 ms */
  486. timeout = 100;
  487. /* hw clears the bit when it's done */
  488. while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
  489. if (timeout == 0) {
  490. printf("%s: timeout error\n", __func__);
  491. return;
  492. }
  493. timeout--;
  494. udelay(1000);
  495. }
  496. /* Set SD bus voltage & enable bus power */
  497. tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
  498. debug("%s: power control = %02X, host control = %02X\n", __func__,
  499. readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
  500. /* Make sure SDIO pads are set up */
  501. tegra_mmc_pad_init(priv);
  502. }
  503. static int tegra_mmc_init(struct udevice *dev)
  504. {
  505. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  506. struct mmc *mmc = mmc_get_mmc_dev(dev);
  507. unsigned int mask;
  508. debug(" tegra_mmc_init called\n");
  509. #if defined(CONFIG_TEGRA210)
  510. priv->mmc_id = clock_decode_periph_id(dev);
  511. if (priv->mmc_id == PERIPH_ID_NONE) {
  512. printf("%s: Missing/invalid peripheral ID\n", __func__);
  513. return -EINVAL;
  514. }
  515. #endif
  516. tegra_mmc_reset(priv, mmc);
  517. #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
  518. /*
  519. * Disable the external clock loopback and use the internal one on
  520. * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
  521. * bits being set to 0xfffd according to the TRM.
  522. *
  523. * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
  524. * approach once proper kernel integration made it mainline.
  525. */
  526. if (priv->reg == (void *)0x700b0400) {
  527. mask = readl(&priv->reg->venmiscctl);
  528. mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
  529. writel(mask, &priv->reg->venmiscctl);
  530. }
  531. #endif
  532. priv->version = readw(&priv->reg->hcver);
  533. debug("host version = %x\n", priv->version);
  534. /* mask all */
  535. writel(0xffffffff, &priv->reg->norintstsen);
  536. writel(0xffffffff, &priv->reg->norintsigen);
  537. writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
  538. /*
  539. * NORMAL Interrupt Status Enable Register init
  540. * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
  541. * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
  542. * [3] ENSTADMAINT : DMA boundary interrupt
  543. * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
  544. * [0] ENSTACMDCMPLT : Command Complete Status Enable
  545. */
  546. mask = readl(&priv->reg->norintstsen);
  547. mask &= ~(0xffff);
  548. mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
  549. TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
  550. TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
  551. TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
  552. TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
  553. writel(mask, &priv->reg->norintstsen);
  554. /*
  555. * NORMAL Interrupt Signal Enable Register init
  556. * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
  557. */
  558. mask = readl(&priv->reg->norintsigen);
  559. mask &= ~(0xffff);
  560. mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
  561. writel(mask, &priv->reg->norintsigen);
  562. return 0;
  563. }
  564. static int tegra_mmc_getcd(struct udevice *dev)
  565. {
  566. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  567. debug("tegra_mmc_getcd called\n");
  568. if (dm_gpio_is_valid(&priv->cd_gpio))
  569. return dm_gpio_get_value(&priv->cd_gpio);
  570. return 1;
  571. }
  572. static const struct dm_mmc_ops tegra_mmc_ops = {
  573. .send_cmd = tegra_mmc_send_cmd,
  574. .set_ios = tegra_mmc_set_ios,
  575. .get_cd = tegra_mmc_getcd,
  576. };
  577. static int tegra_mmc_probe(struct udevice *dev)
  578. {
  579. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  580. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  581. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  582. struct mmc_config *cfg = &plat->cfg;
  583. int bus_width, ret;
  584. cfg->name = dev->name;
  585. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  586. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  587. cfg->host_caps = 0;
  588. if (bus_width == 8)
  589. cfg->host_caps |= MMC_MODE_8BIT;
  590. if (bus_width >= 4)
  591. cfg->host_caps |= MMC_MODE_4BIT;
  592. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  593. /*
  594. * min freq is for card identification, and is the highest
  595. * low-speed SDIO card frequency (actually 400KHz)
  596. * max freq is highest HS eMMC clock as per the SD/MMC spec
  597. * (actually 52MHz)
  598. */
  599. cfg->f_min = 375000;
  600. cfg->f_max = 48000000;
  601. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  602. priv->reg = (void *)dev_read_addr(dev);
  603. ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
  604. if (ret) {
  605. debug("reset_get_by_name() failed: %d\n", ret);
  606. return ret;
  607. }
  608. ret = clk_get_by_index(dev, 0, &priv->clk);
  609. if (ret) {
  610. debug("clk_get_by_index() failed: %d\n", ret);
  611. return ret;
  612. }
  613. ret = reset_assert(&priv->reset_ctl);
  614. if (ret)
  615. return ret;
  616. ret = clk_enable(&priv->clk);
  617. if (ret)
  618. return ret;
  619. ret = clk_set_rate(&priv->clk, 20000000);
  620. if (IS_ERR_VALUE(ret))
  621. return ret;
  622. ret = reset_deassert(&priv->reset_ctl);
  623. if (ret)
  624. return ret;
  625. /* These GPIOs are optional */
  626. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  627. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  628. gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
  629. GPIOD_IS_OUT);
  630. if (dm_gpio_is_valid(&priv->pwr_gpio))
  631. dm_gpio_set_value(&priv->pwr_gpio, 1);
  632. upriv->mmc = &plat->mmc;
  633. return tegra_mmc_init(dev);
  634. }
  635. static int tegra_mmc_bind(struct udevice *dev)
  636. {
  637. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  638. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  639. }
  640. static const struct udevice_id tegra_mmc_ids[] = {
  641. { .compatible = "nvidia,tegra20-sdhci" },
  642. { .compatible = "nvidia,tegra30-sdhci" },
  643. { .compatible = "nvidia,tegra114-sdhci" },
  644. { .compatible = "nvidia,tegra124-sdhci" },
  645. { .compatible = "nvidia,tegra210-sdhci" },
  646. { .compatible = "nvidia,tegra186-sdhci" },
  647. { }
  648. };
  649. U_BOOT_DRIVER(tegra_mmc_drv) = {
  650. .name = "tegra_mmc",
  651. .id = UCLASS_MMC,
  652. .of_match = tegra_mmc_ids,
  653. .bind = tegra_mmc_bind,
  654. .probe = tegra_mmc_probe,
  655. .ops = &tegra_mmc_ops,
  656. .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
  657. .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
  658. };