s5p_sdhci.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <sdhci.h>
  10. #include <fdtdec.h>
  11. #include <linux/libfdt.h>
  12. #include <asm/gpio.h>
  13. #include <asm/arch/mmc.h>
  14. #include <asm/arch/clk.h>
  15. #include <errno.h>
  16. #include <asm/arch/pinmux.h>
  17. #ifdef CONFIG_DM_MMC
  18. struct s5p_sdhci_plat {
  19. struct mmc_config cfg;
  20. struct mmc mmc;
  21. };
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #endif
  24. static char *S5P_NAME = "SAMSUNG SDHCI";
  25. static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
  26. {
  27. unsigned long val, ctrl;
  28. /*
  29. * SELCLKPADDS[17:16]
  30. * 00 = 2mA
  31. * 01 = 4mA
  32. * 10 = 7mA
  33. * 11 = 9mA
  34. */
  35. sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
  36. val = sdhci_readl(host, SDHCI_CONTROL2);
  37. val &= SDHCI_CTRL2_SELBASECLK_MASK(3);
  38. val |= SDHCI_CTRL2_ENSTAASYNCCLR |
  39. SDHCI_CTRL2_ENCMDCNFMSK |
  40. SDHCI_CTRL2_ENFBCLKRX |
  41. SDHCI_CTRL2_ENCLKOUTHOLD;
  42. sdhci_writel(host, val, SDHCI_CONTROL2);
  43. /*
  44. * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
  45. * FCSel[1:0] : Rx Feedback Clock Delay Control
  46. * Inverter delay means10ns delay if SDCLK 50MHz setting
  47. * 01 = Delay1 (basic delay)
  48. * 11 = Delay2 (basic delay + 2ns)
  49. * 00 = Delay3 (inverter delay)
  50. * 10 = Delay4 (inverter delay + 2ns)
  51. */
  52. val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
  53. sdhci_writel(host, val, SDHCI_CONTROL3);
  54. /*
  55. * SELBASECLK[5:4]
  56. * 00/01 = HCLK
  57. * 10 = EPLL
  58. * 11 = XTI or XEXTCLK
  59. */
  60. ctrl = sdhci_readl(host, SDHCI_CONTROL2);
  61. ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
  62. ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
  63. sdhci_writel(host, ctrl, SDHCI_CONTROL2);
  64. }
  65. static void s5p_set_clock(struct sdhci_host *host, u32 div)
  66. {
  67. /* ToDo : Use the Clock Framework */
  68. set_mmc_clk(host->index, div);
  69. }
  70. static const struct sdhci_ops s5p_sdhci_ops = {
  71. .set_clock = &s5p_set_clock,
  72. .set_control_reg = &s5p_sdhci_set_control_reg,
  73. };
  74. static int s5p_sdhci_core_init(struct sdhci_host *host)
  75. {
  76. host->name = S5P_NAME;
  77. host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
  78. SDHCI_QUIRK_32BIT_DMA_ADDR |
  79. SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
  80. host->max_clk = 52000000;
  81. host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  82. host->ops = &s5p_sdhci_ops;
  83. if (host->bus_width == 8)
  84. host->host_caps |= MMC_MODE_8BIT;
  85. #ifndef CONFIG_BLK
  86. return add_sdhci(host, 0, 400000);
  87. #else
  88. return 0;
  89. #endif
  90. }
  91. int s5p_sdhci_init(u32 regbase, int index, int bus_width)
  92. {
  93. struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host));
  94. if (!host) {
  95. printf("sdhci__host allocation fail!\n");
  96. return -ENOMEM;
  97. }
  98. host->ioaddr = (void *)regbase;
  99. host->index = index;
  100. host->bus_width = bus_width;
  101. return s5p_sdhci_core_init(host);
  102. }
  103. static int do_sdhci_init(struct sdhci_host *host)
  104. {
  105. int dev_id, flag, ret;
  106. flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
  107. dev_id = host->index + PERIPH_ID_SDMMC0;
  108. ret = exynos_pinmux_config(dev_id, flag);
  109. if (ret) {
  110. printf("external SD not configured\n");
  111. return ret;
  112. }
  113. if (dm_gpio_is_valid(&host->pwr_gpio)) {
  114. dm_gpio_set_value(&host->pwr_gpio, 1);
  115. ret = exynos_pinmux_config(dev_id, flag);
  116. if (ret) {
  117. debug("MMC not configured\n");
  118. return ret;
  119. }
  120. }
  121. if (dm_gpio_is_valid(&host->cd_gpio)) {
  122. ret = dm_gpio_get_value(&host->cd_gpio);
  123. if (ret) {
  124. debug("no SD card detected (%d)\n", ret);
  125. return -ENODEV;
  126. }
  127. }
  128. return s5p_sdhci_core_init(host);
  129. }
  130. static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
  131. {
  132. int bus_width, dev_id;
  133. unsigned int base;
  134. /* Get device id */
  135. dev_id = pinmux_decode_periph_id(blob, node);
  136. if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
  137. debug("MMC: Can't get device id\n");
  138. return -EINVAL;
  139. }
  140. host->index = dev_id - PERIPH_ID_SDMMC0;
  141. /* Get bus width */
  142. bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
  143. if (bus_width <= 0) {
  144. debug("MMC: Can't get bus-width\n");
  145. return -EINVAL;
  146. }
  147. host->bus_width = bus_width;
  148. /* Get the base address from the device node */
  149. base = fdtdec_get_addr(blob, node, "reg");
  150. if (!base) {
  151. debug("MMC: Can't get base address\n");
  152. return -EINVAL;
  153. }
  154. host->ioaddr = (void *)base;
  155. gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0,
  156. &host->pwr_gpio, GPIOD_IS_OUT);
  157. gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0,
  158. &host->cd_gpio, GPIOD_IS_IN);
  159. return 0;
  160. }
  161. #ifdef CONFIG_DM_MMC
  162. static int s5p_sdhci_probe(struct udevice *dev)
  163. {
  164. struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
  165. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  166. struct sdhci_host *host = dev_get_priv(dev);
  167. int ret;
  168. ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
  169. if (ret)
  170. return ret;
  171. ret = do_sdhci_init(host);
  172. if (ret)
  173. return ret;
  174. ret = mmc_of_parse(dev, &plat->cfg);
  175. if (ret)
  176. return ret;
  177. host->mmc = &plat->mmc;
  178. host->mmc->dev = dev;
  179. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000);
  180. if (ret)
  181. return ret;
  182. host->mmc->priv = host;
  183. upriv->mmc = host->mmc;
  184. return sdhci_probe(dev);
  185. }
  186. static int s5p_sdhci_bind(struct udevice *dev)
  187. {
  188. struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
  189. int ret;
  190. ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
  191. if (ret)
  192. return ret;
  193. return 0;
  194. }
  195. static const struct udevice_id s5p_sdhci_ids[] = {
  196. { .compatible = "samsung,exynos4412-sdhci"},
  197. { }
  198. };
  199. U_BOOT_DRIVER(s5p_sdhci_drv) = {
  200. .name = "s5p_sdhci",
  201. .id = UCLASS_MMC,
  202. .of_match = s5p_sdhci_ids,
  203. .bind = s5p_sdhci_bind,
  204. .ops = &sdhci_ops,
  205. .probe = s5p_sdhci_probe,
  206. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  207. .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat),
  208. };
  209. #endif /* CONFIG_DM_MMC */