mvebu_mmc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell MMC/SD/SDIO driver
  4. *
  5. * (C) Copyright 2012-2014
  6. * Marvell Semiconductor <www.marvell.com>
  7. * Written-by: Maen Suleiman, Gerald Kerma
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <part.h>
  13. #include <mmc.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/soc.h>
  17. #include <mvebu_mmc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define DRIVER_NAME "MVEBU_MMC"
  20. #define MVEBU_TARGET_DRAM 0
  21. #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
  22. static void mvebu_mmc_write(u32 offs, u32 val)
  23. {
  24. writel(val, CONFIG_SYS_MMC_BASE + (offs));
  25. }
  26. static u32 mvebu_mmc_read(u32 offs)
  27. {
  28. return readl(CONFIG_SYS_MMC_BASE + (offs));
  29. }
  30. static int mvebu_mmc_setup_data(struct mmc_data *data)
  31. {
  32. u32 ctrl_reg;
  33. debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
  34. (data->flags & MMC_DATA_READ) ? "read" : "write",
  35. data->blocks, data->blocksize);
  36. /* default to maximum timeout */
  37. ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
  38. ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  39. mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
  40. if (data->flags & MMC_DATA_READ) {
  41. mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
  42. mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
  43. } else {
  44. mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
  45. mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
  46. }
  47. mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
  48. mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
  49. return 0;
  50. }
  51. static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  52. struct mmc_data *data)
  53. {
  54. ulong start;
  55. ushort waittype = 0;
  56. ushort resptype = 0;
  57. ushort xfertype = 0;
  58. ushort resp_indx = 0;
  59. debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
  60. DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
  61. debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
  62. cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
  63. /*
  64. * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
  65. * register is sometimes not set before a while when some
  66. * "unusual" data block sizes are used (such as with the SWITCH
  67. * command), even despite the fact that the XFER_DONE interrupt
  68. * was raised. And if another data transfer starts before
  69. * this bit comes to good sense (which eventually happens by
  70. * itself) then the new transfer simply fails with a timeout.
  71. */
  72. if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
  73. ushort hw_state, count = 0;
  74. start = get_timer(0);
  75. do {
  76. hw_state = mvebu_mmc_read(SDIO_HW_STATE);
  77. if ((get_timer(0) - start) > TIMEOUT_DELAY) {
  78. printf("%s : FIFO_EMPTY bit missing\n",
  79. DRIVER_NAME);
  80. break;
  81. }
  82. count++;
  83. } while (!(hw_state & CMD_FIFO_EMPTY));
  84. debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
  85. DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
  86. }
  87. /* Clear status */
  88. mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  89. mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  90. resptype = SDIO_CMD_INDEX(cmd->cmdidx);
  91. /* Analyzing resptype/xfertype/waittype for the command */
  92. if (cmd->resp_type & MMC_RSP_BUSY)
  93. resptype |= SDIO_CMD_RSP_48BUSY;
  94. else if (cmd->resp_type & MMC_RSP_136)
  95. resptype |= SDIO_CMD_RSP_136;
  96. else if (cmd->resp_type & MMC_RSP_PRESENT)
  97. resptype |= SDIO_CMD_RSP_48;
  98. else
  99. resptype |= SDIO_CMD_RSP_NONE;
  100. if (cmd->resp_type & MMC_RSP_CRC)
  101. resptype |= SDIO_CMD_CHECK_CMDCRC;
  102. if (cmd->resp_type & MMC_RSP_OPCODE)
  103. resptype |= SDIO_CMD_INDX_CHECK;
  104. if (cmd->resp_type & MMC_RSP_PRESENT) {
  105. resptype |= SDIO_UNEXPECTED_RESP;
  106. waittype |= SDIO_NOR_UNEXP_RSP;
  107. }
  108. if (data) {
  109. int err = mvebu_mmc_setup_data(data);
  110. if (err) {
  111. debug("%s: command DATA error :%x\n",
  112. DRIVER_NAME, err);
  113. return err;
  114. }
  115. resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
  116. xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
  117. if (data->flags & MMC_DATA_READ) {
  118. xfertype |= SDIO_XFER_MODE_TO_HOST;
  119. waittype = SDIO_NOR_DMA_INI;
  120. } else {
  121. waittype |= SDIO_NOR_XFER_DONE;
  122. }
  123. } else {
  124. waittype |= SDIO_NOR_CMD_DONE;
  125. }
  126. /* Setting cmd arguments */
  127. mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
  128. mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
  129. /* Setting Xfer mode */
  130. mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
  131. /* Sending command */
  132. mvebu_mmc_write(SDIO_CMD, resptype);
  133. start = get_timer(0);
  134. while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
  135. if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
  136. debug("%s: error! cmdidx : %d, err reg: %04x\n",
  137. DRIVER_NAME, cmd->cmdidx,
  138. mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
  139. if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
  140. (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
  141. debug("%s: command READ timed out\n",
  142. DRIVER_NAME);
  143. return -ETIMEDOUT;
  144. }
  145. debug("%s: command READ error\n", DRIVER_NAME);
  146. return -ECOMM;
  147. }
  148. if ((get_timer(0) - start) > TIMEOUT_DELAY) {
  149. debug("%s: command timed out\n", DRIVER_NAME);
  150. return -ETIMEDOUT;
  151. }
  152. }
  153. /* Handling response */
  154. if (cmd->resp_type & MMC_RSP_136) {
  155. uint response[8];
  156. for (resp_indx = 0; resp_indx < 8; resp_indx++)
  157. response[resp_indx]
  158. = mvebu_mmc_read(SDIO_RSP(resp_indx));
  159. cmd->response[0] = ((response[0] & 0x03ff) << 22) |
  160. ((response[1] & 0xffff) << 6) |
  161. ((response[2] & 0xfc00) >> 10);
  162. cmd->response[1] = ((response[2] & 0x03ff) << 22) |
  163. ((response[3] & 0xffff) << 6) |
  164. ((response[4] & 0xfc00) >> 10);
  165. cmd->response[2] = ((response[4] & 0x03ff) << 22) |
  166. ((response[5] & 0xffff) << 6) |
  167. ((response[6] & 0xfc00) >> 10);
  168. cmd->response[3] = ((response[6] & 0x03ff) << 22) |
  169. ((response[7] & 0x3fff) << 8);
  170. } else if (cmd->resp_type & MMC_RSP_PRESENT) {
  171. uint response[3];
  172. for (resp_indx = 0; resp_indx < 3; resp_indx++)
  173. response[resp_indx]
  174. = mvebu_mmc_read(SDIO_RSP(resp_indx));
  175. cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
  176. ((response[1] & 0xffff) << (14 - 8)) |
  177. ((response[0] & 0x03ff) << (30 - 8));
  178. cmd->response[1] = ((response[0] & 0xfc00) >> 10);
  179. cmd->response[2] = 0;
  180. cmd->response[3] = 0;
  181. } else {
  182. cmd->response[0] = 0;
  183. cmd->response[1] = 0;
  184. cmd->response[2] = 0;
  185. cmd->response[3] = 0;
  186. }
  187. debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
  188. debug("[0x%x] ", cmd->response[0]);
  189. debug("[0x%x] ", cmd->response[1]);
  190. debug("[0x%x] ", cmd->response[2]);
  191. debug("[0x%x] ", cmd->response[3]);
  192. debug("\n");
  193. if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
  194. (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
  195. return -ETIMEDOUT;
  196. return 0;
  197. }
  198. static void mvebu_mmc_power_up(void)
  199. {
  200. debug("%s: power up\n", DRIVER_NAME);
  201. /* disable interrupts */
  202. mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
  203. mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
  204. /* SW reset */
  205. mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  206. mvebu_mmc_write(SDIO_XFER_MODE, 0);
  207. /* enable status */
  208. mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  209. mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  210. /* enable interrupts status */
  211. mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  212. mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  213. }
  214. static void mvebu_mmc_set_clk(unsigned int clock)
  215. {
  216. unsigned int m;
  217. if (clock == 0) {
  218. debug("%s: clock off\n", DRIVER_NAME);
  219. mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
  220. mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
  221. } else {
  222. m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
  223. if (m > MVEBU_MMC_BASE_DIV_MAX)
  224. m = MVEBU_MMC_BASE_DIV_MAX;
  225. mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
  226. debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
  227. }
  228. }
  229. static void mvebu_mmc_set_bus(unsigned int bus)
  230. {
  231. u32 ctrl_reg = 0;
  232. ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
  233. ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  234. switch (bus) {
  235. case 4:
  236. ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  237. break;
  238. case 1:
  239. default:
  240. ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
  241. }
  242. /* default transfer mode */
  243. ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
  244. ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
  245. /* default to maximum timeout */
  246. ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  247. ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
  248. ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
  249. ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
  250. debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
  251. (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
  252. "push-pull" : "open-drain",
  253. (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
  254. "4bit-width" : "1bit-width",
  255. (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
  256. "high-speed" : "");
  257. mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
  258. }
  259. static int mvebu_mmc_set_ios(struct mmc *mmc)
  260. {
  261. debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
  262. mmc->bus_width, mmc->clock);
  263. mvebu_mmc_set_bus(mmc->bus_width);
  264. mvebu_mmc_set_clk(mmc->clock);
  265. return 0;
  266. }
  267. /*
  268. * Set window register.
  269. */
  270. static void mvebu_window_setup(void)
  271. {
  272. int i;
  273. for (i = 0; i < 4; i++) {
  274. mvebu_mmc_write(WINDOW_CTRL(i), 0);
  275. mvebu_mmc_write(WINDOW_BASE(i), 0);
  276. }
  277. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  278. u32 size, base, attrib;
  279. /* Enable DRAM bank */
  280. switch (i) {
  281. case 0:
  282. attrib = KWCPU_ATTR_DRAM_CS0;
  283. break;
  284. case 1:
  285. attrib = KWCPU_ATTR_DRAM_CS1;
  286. break;
  287. case 2:
  288. attrib = KWCPU_ATTR_DRAM_CS2;
  289. break;
  290. case 3:
  291. attrib = KWCPU_ATTR_DRAM_CS3;
  292. break;
  293. default:
  294. /* invalide bank, disable access */
  295. attrib = 0;
  296. break;
  297. }
  298. size = gd->bd->bi_dram[i].size;
  299. base = gd->bd->bi_dram[i].start;
  300. if (size && attrib) {
  301. mvebu_mmc_write(WINDOW_CTRL(i),
  302. MVCPU_WIN_CTRL_DATA(size,
  303. MVEBU_TARGET_DRAM,
  304. attrib,
  305. MVCPU_WIN_ENABLE));
  306. } else {
  307. mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
  308. }
  309. mvebu_mmc_write(WINDOW_BASE(i), base);
  310. }
  311. }
  312. static int mvebu_mmc_initialize(struct mmc *mmc)
  313. {
  314. debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
  315. /*
  316. * Setting host parameters
  317. * Initial Host Ctrl : Timeout : max , Normal Speed mode,
  318. * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
  319. */
  320. mvebu_mmc_write(SDIO_HOST_CTRL,
  321. SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
  322. SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
  323. SDIO_HOST_CTRL_BIG_ENDIAN |
  324. SDIO_HOST_CTRL_PUSH_PULL_EN |
  325. SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
  326. mvebu_mmc_write(SDIO_CLK_CTRL, 0);
  327. /* enable status */
  328. mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  329. mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  330. /* disable interrupts */
  331. mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
  332. mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
  333. mvebu_window_setup();
  334. /* SW reset */
  335. mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  336. return 0;
  337. }
  338. static const struct mmc_ops mvebu_mmc_ops = {
  339. .send_cmd = mvebu_mmc_send_cmd,
  340. .set_ios = mvebu_mmc_set_ios,
  341. .init = mvebu_mmc_initialize,
  342. };
  343. static struct mmc_config mvebu_mmc_cfg = {
  344. .name = DRIVER_NAME,
  345. .ops = &mvebu_mmc_ops,
  346. .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
  347. .f_max = MVEBU_MMC_CLOCKRATE_MAX,
  348. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  349. .host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
  350. MMC_MODE_HS_52MHz,
  351. .part_type = PART_TYPE_DOS,
  352. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  353. };
  354. int mvebu_mmc_init(bd_t *bis)
  355. {
  356. struct mmc *mmc;
  357. mvebu_mmc_power_up();
  358. mmc = mmc_create(&mvebu_mmc_cfg, bis);
  359. if (mmc == NULL)
  360. return -1;
  361. return 0;
  362. }