arm_pl180_mmci.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ARM PrimeCell MultiMedia Card Interface - PL180
  4. *
  5. * Copyright (C) ST-Ericsson SA 2010
  6. *
  7. * Author: Ulf Hansson <ulf.hansson@stericsson.com>
  8. * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
  9. * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
  10. */
  11. /* #define DEBUG */
  12. #include "common.h"
  13. #include <clk.h>
  14. #include <errno.h>
  15. #include <malloc.h>
  16. #include <mmc.h>
  17. #include <dm/device_compat.h>
  18. #include <asm/io.h>
  19. #include <asm-generic/gpio.h>
  20. #include "arm_pl180_mmci.h"
  21. #ifdef CONFIG_DM_MMC
  22. #include <dm.h>
  23. #define MMC_CLOCK_MAX 48000000
  24. #define MMC_CLOCK_MIN 400000
  25. struct arm_pl180_mmc_plat {
  26. struct mmc_config cfg;
  27. struct mmc mmc;
  28. };
  29. #endif
  30. static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
  31. {
  32. u32 hoststatus, statusmask;
  33. struct pl180_mmc_host *host = dev->priv;
  34. statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
  35. if ((cmd->resp_type & MMC_RSP_PRESENT))
  36. statusmask |= SDI_STA_CMDREND;
  37. else
  38. statusmask |= SDI_STA_CMDSENT;
  39. do
  40. hoststatus = readl(&host->base->status) & statusmask;
  41. while (!hoststatus);
  42. writel(statusmask, &host->base->status_clear);
  43. if (hoststatus & SDI_STA_CTIMEOUT) {
  44. debug("CMD%d time out\n", cmd->cmdidx);
  45. return -ETIMEDOUT;
  46. } else if ((hoststatus & SDI_STA_CCRCFAIL) &&
  47. (cmd->resp_type & MMC_RSP_CRC)) {
  48. printf("CMD%d CRC error\n", cmd->cmdidx);
  49. return -EILSEQ;
  50. }
  51. if (cmd->resp_type & MMC_RSP_PRESENT) {
  52. cmd->response[0] = readl(&host->base->response0);
  53. cmd->response[1] = readl(&host->base->response1);
  54. cmd->response[2] = readl(&host->base->response2);
  55. cmd->response[3] = readl(&host->base->response3);
  56. debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
  57. "response[2]:0x%08X, response[3]:0x%08X\n",
  58. cmd->cmdidx, cmd->response[0], cmd->response[1],
  59. cmd->response[2], cmd->response[3]);
  60. }
  61. return 0;
  62. }
  63. /* send command to the mmc card and wait for results */
  64. static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
  65. {
  66. int result;
  67. u32 sdi_cmd = 0;
  68. struct pl180_mmc_host *host = dev->priv;
  69. sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
  70. if (cmd->resp_type) {
  71. sdi_cmd |= SDI_CMD_WAITRESP;
  72. if (cmd->resp_type & MMC_RSP_136)
  73. sdi_cmd |= SDI_CMD_LONGRESP;
  74. }
  75. writel((u32)cmd->cmdarg, &host->base->argument);
  76. udelay(COMMAND_REG_DELAY);
  77. writel(sdi_cmd, &host->base->command);
  78. result = wait_for_command_end(dev, cmd);
  79. /* After CMD2 set RCA to a none zero value. */
  80. if ((result == 0) && (cmd->cmdidx == MMC_CMD_ALL_SEND_CID))
  81. dev->rca = 10;
  82. /* After CMD3 open drain is switched off and push pull is used. */
  83. if ((result == 0) && (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR)) {
  84. u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD;
  85. writel(sdi_pwr, &host->base->power);
  86. }
  87. return result;
  88. }
  89. static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
  90. {
  91. u32 *tempbuff = dest;
  92. u64 xfercount = blkcount * blksize;
  93. struct pl180_mmc_host *host = dev->priv;
  94. u32 status, status_err;
  95. debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
  96. status = readl(&host->base->status);
  97. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
  98. SDI_STA_RXOVERR);
  99. while ((!status_err) && (xfercount >= sizeof(u32))) {
  100. if (status & SDI_STA_RXDAVL) {
  101. *(tempbuff) = readl(&host->base->fifo);
  102. tempbuff++;
  103. xfercount -= sizeof(u32);
  104. }
  105. status = readl(&host->base->status);
  106. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
  107. SDI_STA_RXOVERR);
  108. }
  109. status_err = status &
  110. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
  111. SDI_STA_RXOVERR);
  112. while (!status_err) {
  113. status = readl(&host->base->status);
  114. status_err = status &
  115. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
  116. SDI_STA_RXOVERR);
  117. }
  118. if (status & SDI_STA_DTIMEOUT) {
  119. printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
  120. xfercount, status);
  121. return -ETIMEDOUT;
  122. } else if (status & SDI_STA_DCRCFAIL) {
  123. printf("Read data bytes CRC error: 0x%x\n", status);
  124. return -EILSEQ;
  125. } else if (status & SDI_STA_RXOVERR) {
  126. printf("Read data RX overflow error\n");
  127. return -EIO;
  128. }
  129. writel(SDI_ICR_MASK, &host->base->status_clear);
  130. if (xfercount) {
  131. printf("Read data error, xfercount: %llu\n", xfercount);
  132. return -ENOBUFS;
  133. }
  134. return 0;
  135. }
  136. static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize)
  137. {
  138. u32 *tempbuff = src;
  139. int i;
  140. u64 xfercount = blkcount * blksize;
  141. struct pl180_mmc_host *host = dev->priv;
  142. u32 status, status_err;
  143. debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
  144. status = readl(&host->base->status);
  145. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
  146. while (!status_err && xfercount) {
  147. if (status & SDI_STA_TXFIFOBW) {
  148. if (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32)) {
  149. for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
  150. writel(*(tempbuff + i),
  151. &host->base->fifo);
  152. tempbuff += SDI_FIFO_BURST_SIZE;
  153. xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
  154. } else {
  155. while (xfercount >= sizeof(u32)) {
  156. writel(*(tempbuff), &host->base->fifo);
  157. tempbuff++;
  158. xfercount -= sizeof(u32);
  159. }
  160. }
  161. }
  162. status = readl(&host->base->status);
  163. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
  164. }
  165. status_err = status &
  166. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
  167. while (!status_err) {
  168. status = readl(&host->base->status);
  169. status_err = status &
  170. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
  171. }
  172. if (status & SDI_STA_DTIMEOUT) {
  173. printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
  174. xfercount, status);
  175. return -ETIMEDOUT;
  176. } else if (status & SDI_STA_DCRCFAIL) {
  177. printf("Write data CRC error\n");
  178. return -EILSEQ;
  179. }
  180. writel(SDI_ICR_MASK, &host->base->status_clear);
  181. if (xfercount) {
  182. printf("Write data error, xfercount:%llu", xfercount);
  183. return -ENOBUFS;
  184. }
  185. return 0;
  186. }
  187. static int do_data_transfer(struct mmc *dev,
  188. struct mmc_cmd *cmd,
  189. struct mmc_data *data)
  190. {
  191. int error = -ETIMEDOUT;
  192. struct pl180_mmc_host *host = dev->priv;
  193. u32 blksz = 0;
  194. u32 data_ctrl = 0;
  195. u32 data_len = (u32) (data->blocks * data->blocksize);
  196. if (!host->version2) {
  197. blksz = (ffs(data->blocksize) - 1);
  198. data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
  199. } else {
  200. blksz = data->blocksize;
  201. data_ctrl |= (blksz << SDI_DCTRL_DBLOCKSIZE_V2_SHIFT);
  202. }
  203. data_ctrl |= SDI_DCTRL_DTEN | SDI_DCTRL_BUSYMODE;
  204. writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
  205. writel(data_len, &host->base->datalength);
  206. udelay(DATA_REG_DELAY);
  207. if (data->flags & MMC_DATA_READ) {
  208. data_ctrl |= SDI_DCTRL_DTDIR_IN;
  209. writel(data_ctrl, &host->base->datactrl);
  210. error = do_command(dev, cmd);
  211. if (error)
  212. return error;
  213. error = read_bytes(dev, (u32 *)data->dest, (u32)data->blocks,
  214. (u32)data->blocksize);
  215. } else if (data->flags & MMC_DATA_WRITE) {
  216. error = do_command(dev, cmd);
  217. if (error)
  218. return error;
  219. writel(data_ctrl, &host->base->datactrl);
  220. error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
  221. (u32)data->blocksize);
  222. }
  223. return error;
  224. }
  225. static int host_request(struct mmc *dev,
  226. struct mmc_cmd *cmd,
  227. struct mmc_data *data)
  228. {
  229. int result;
  230. if (data)
  231. result = do_data_transfer(dev, cmd, data);
  232. else
  233. result = do_command(dev, cmd);
  234. return result;
  235. }
  236. static int host_set_ios(struct mmc *dev)
  237. {
  238. struct pl180_mmc_host *host = dev->priv;
  239. u32 sdi_clkcr;
  240. sdi_clkcr = readl(&host->base->clock);
  241. /* Ramp up the clock rate */
  242. if (dev->clock) {
  243. u32 clkdiv = 0;
  244. u32 tmp_clock;
  245. if (dev->clock >= dev->cfg->f_max) {
  246. clkdiv = 0;
  247. dev->clock = dev->cfg->f_max;
  248. } else {
  249. clkdiv = (host->clock_in / dev->clock) - 2;
  250. }
  251. tmp_clock = host->clock_in / (clkdiv + 2);
  252. while (tmp_clock > dev->clock) {
  253. clkdiv++;
  254. tmp_clock = host->clock_in / (clkdiv + 2);
  255. }
  256. if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
  257. clkdiv = SDI_CLKCR_CLKDIV_MASK;
  258. tmp_clock = host->clock_in / (clkdiv + 2);
  259. dev->clock = tmp_clock;
  260. sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
  261. sdi_clkcr |= clkdiv;
  262. }
  263. /* Set the bus width */
  264. if (dev->bus_width) {
  265. u32 buswidth = 0;
  266. switch (dev->bus_width) {
  267. case 1:
  268. buswidth |= SDI_CLKCR_WIDBUS_1;
  269. break;
  270. case 4:
  271. buswidth |= SDI_CLKCR_WIDBUS_4;
  272. break;
  273. case 8:
  274. buswidth |= SDI_CLKCR_WIDBUS_8;
  275. break;
  276. default:
  277. printf("Invalid bus width: %d\n", dev->bus_width);
  278. break;
  279. }
  280. sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
  281. sdi_clkcr |= buswidth;
  282. }
  283. writel(sdi_clkcr, &host->base->clock);
  284. udelay(CLK_CHANGE_DELAY);
  285. return 0;
  286. }
  287. #ifndef CONFIG_DM_MMC
  288. /* MMC uses open drain drivers in the enumeration phase */
  289. static int mmc_host_reset(struct mmc *dev)
  290. {
  291. struct pl180_mmc_host *host = dev->priv;
  292. writel(host->pwr_init, &host->base->power);
  293. return 0;
  294. }
  295. static const struct mmc_ops arm_pl180_mmci_ops = {
  296. .send_cmd = host_request,
  297. .set_ios = host_set_ios,
  298. .init = mmc_host_reset,
  299. };
  300. /*
  301. * mmc_host_init - initialize the mmc controller.
  302. * Set initial clock and power for mmc slot.
  303. * Initialize mmc struct and register with mmc framework.
  304. */
  305. int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
  306. {
  307. u32 sdi_u32;
  308. writel(host->pwr_init, &host->base->power);
  309. writel(host->clkdiv_init, &host->base->clock);
  310. udelay(CLK_CHANGE_DELAY);
  311. /* Disable mmc interrupts */
  312. sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
  313. writel(sdi_u32, &host->base->mask0);
  314. host->cfg.name = host->name;
  315. host->cfg.ops = &arm_pl180_mmci_ops;
  316. /* TODO remove the duplicates */
  317. host->cfg.host_caps = host->caps;
  318. host->cfg.voltages = host->voltages;
  319. host->cfg.f_min = host->clock_min;
  320. host->cfg.f_max = host->clock_max;
  321. if (host->b_max != 0)
  322. host->cfg.b_max = host->b_max;
  323. else
  324. host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  325. *mmc = mmc_create(&host->cfg, host);
  326. if (!*mmc)
  327. return -1;
  328. debug("registered mmc interface number is:%d\n",
  329. (*mmc)->block_dev.devnum);
  330. return 0;
  331. }
  332. #endif
  333. #ifdef CONFIG_DM_MMC
  334. static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
  335. {
  336. u32 sdi_u32;
  337. writel(host->pwr_init, &host->base->power);
  338. writel(host->clkdiv_init, &host->base->clock);
  339. udelay(CLK_CHANGE_DELAY);
  340. /* Disable mmc interrupts */
  341. sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
  342. writel(sdi_u32, &host->base->mask0);
  343. }
  344. static int arm_pl180_mmc_probe(struct udevice *dev)
  345. {
  346. struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
  347. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  348. struct mmc *mmc = &pdata->mmc;
  349. struct pl180_mmc_host *host = dev->priv;
  350. struct mmc_config *cfg = &pdata->cfg;
  351. struct clk clk;
  352. u32 bus_width;
  353. u32 periphid;
  354. int ret;
  355. ret = clk_get_by_index(dev, 0, &clk);
  356. if (ret < 0)
  357. return ret;
  358. ret = clk_enable(&clk);
  359. if (ret) {
  360. clk_free(&clk);
  361. dev_err(dev, "failed to enable clock\n");
  362. return ret;
  363. }
  364. host->pwr_init = INIT_PWR;
  365. host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
  366. SDI_CLKCR_HWFC_EN;
  367. host->clock_in = clk_get_rate(&clk);
  368. periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
  369. switch (periphid) {
  370. case STM32_MMCI_ID: /* stm32 variant */
  371. host->version2 = false;
  372. break;
  373. default:
  374. host->version2 = true;
  375. }
  376. cfg->name = dev->name;
  377. cfg->voltages = VOLTAGE_WINDOW_SD;
  378. cfg->host_caps = 0;
  379. cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
  380. cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
  381. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  382. gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
  383. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  384. switch (bus_width) {
  385. case 8:
  386. cfg->host_caps |= MMC_MODE_8BIT;
  387. /* Hosts capable of 8-bit transfers can also do 4 bits */
  388. case 4:
  389. cfg->host_caps |= MMC_MODE_4BIT;
  390. break;
  391. case 1:
  392. break;
  393. default:
  394. dev_err(dev, "Invalid bus-width value %u\n", bus_width);
  395. }
  396. arm_pl180_mmc_init(host);
  397. mmc->priv = host;
  398. mmc->dev = dev;
  399. upriv->mmc = mmc;
  400. return 0;
  401. }
  402. int arm_pl180_mmc_bind(struct udevice *dev)
  403. {
  404. struct arm_pl180_mmc_plat *plat = dev_get_platdata(dev);
  405. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  406. }
  407. static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
  408. struct mmc_data *data)
  409. {
  410. struct mmc *mmc = mmc_get_mmc_dev(dev);
  411. return host_request(mmc, cmd, data);
  412. }
  413. static int dm_host_set_ios(struct udevice *dev)
  414. {
  415. struct mmc *mmc = mmc_get_mmc_dev(dev);
  416. return host_set_ios(mmc);
  417. }
  418. static int dm_mmc_getcd(struct udevice *dev)
  419. {
  420. struct pl180_mmc_host *host = dev->priv;
  421. int value = 1;
  422. if (dm_gpio_is_valid(&host->cd_gpio))
  423. value = dm_gpio_get_value(&host->cd_gpio);
  424. return value;
  425. }
  426. static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = {
  427. .send_cmd = dm_host_request,
  428. .set_ios = dm_host_set_ios,
  429. .get_cd = dm_mmc_getcd,
  430. };
  431. static int arm_pl180_mmc_ofdata_to_platdata(struct udevice *dev)
  432. {
  433. struct pl180_mmc_host *host = dev->priv;
  434. fdt_addr_t addr;
  435. addr = dev_read_addr(dev);
  436. if (addr == FDT_ADDR_T_NONE)
  437. return -EINVAL;
  438. host->base = (void *)addr;
  439. return 0;
  440. }
  441. static const struct udevice_id arm_pl180_mmc_match[] = {
  442. { .compatible = "arm,pl180" },
  443. { .compatible = "arm,primecell" },
  444. { /* sentinel */ }
  445. };
  446. U_BOOT_DRIVER(arm_pl180_mmc) = {
  447. .name = "arm_pl180_mmc",
  448. .id = UCLASS_MMC,
  449. .of_match = arm_pl180_mmc_match,
  450. .ops = &arm_pl180_dm_mmc_ops,
  451. .probe = arm_pl180_mmc_probe,
  452. .ofdata_to_platdata = arm_pl180_mmc_ofdata_to_platdata,
  453. .bind = arm_pl180_mmc_bind,
  454. .priv_auto_alloc_size = sizeof(struct pl180_mmc_host),
  455. .platdata_auto_alloc_size = sizeof(struct arm_pl180_mmc_plat),
  456. };
  457. #endif