tegra-hsp.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <asm/io.h>
  8. #include <dm.h>
  9. #include <mailbox-uclass.h>
  10. #include <dt-bindings/mailbox/tegra186-hsp.h>
  11. #define TEGRA_HSP_INT_DIMENSIONING 0x380
  12. #define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16
  13. #define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf
  14. #define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12
  15. #define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf
  16. #define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8
  17. #define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf
  18. #define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4
  19. #define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf
  20. #define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0
  21. #define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf
  22. #define TEGRA_HSP_DB_REG_TRIGGER 0x0
  23. #define TEGRA_HSP_DB_REG_ENABLE 0x4
  24. #define TEGRA_HSP_DB_REG_RAW 0x8
  25. #define TEGRA_HSP_DB_REG_PENDING 0xc
  26. #define TEGRA_HSP_DB_ID_CCPLEX 1
  27. #define TEGRA_HSP_DB_ID_BPMP 3
  28. #define TEGRA_HSP_DB_ID_NUM 7
  29. struct tegra_hsp {
  30. fdt_addr_t regs;
  31. uint32_t db_base;
  32. };
  33. static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
  34. uint32_t reg)
  35. {
  36. return (uint32_t *)(thsp->regs + thsp->db_base + (db_id * 0x100) + reg);
  37. }
  38. static uint32_t tegra_hsp_readl(struct tegra_hsp *thsp, uint32_t db_id,
  39. uint32_t reg)
  40. {
  41. uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
  42. return readl(r);
  43. }
  44. static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
  45. uint32_t db_id, uint32_t reg)
  46. {
  47. uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
  48. writel(val, r);
  49. readl(r);
  50. }
  51. static int tegra_hsp_db_id(ulong chan_id)
  52. {
  53. switch (chan_id) {
  54. case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
  55. return TEGRA_HSP_DB_ID_BPMP;
  56. default:
  57. debug("Invalid channel ID\n");
  58. return -EINVAL;
  59. }
  60. }
  61. static int tegra_hsp_of_xlate(struct mbox_chan *chan,
  62. struct ofnode_phandle_args *args)
  63. {
  64. debug("%s(chan=%p)\n", __func__, chan);
  65. if (args->args_count != 2) {
  66. debug("Invaild args_count: %d\n", args->args_count);
  67. return -EINVAL;
  68. }
  69. chan->id = (args->args[0] << 16) | args->args[1];
  70. return 0;
  71. }
  72. static int tegra_hsp_request(struct mbox_chan *chan)
  73. {
  74. int db_id;
  75. debug("%s(chan=%p)\n", __func__, chan);
  76. db_id = tegra_hsp_db_id(chan->id);
  77. if (db_id < 0) {
  78. debug("tegra_hsp_db_id() failed: %d\n", db_id);
  79. return -EINVAL;
  80. }
  81. return 0;
  82. }
  83. static int tegra_hsp_free(struct mbox_chan *chan)
  84. {
  85. debug("%s(chan=%p)\n", __func__, chan);
  86. return 0;
  87. }
  88. static int tegra_hsp_send(struct mbox_chan *chan, const void *data)
  89. {
  90. struct tegra_hsp *thsp = dev_get_priv(chan->dev);
  91. int db_id;
  92. debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
  93. db_id = tegra_hsp_db_id(chan->id);
  94. tegra_hsp_writel(thsp, 1, db_id, TEGRA_HSP_DB_REG_TRIGGER);
  95. return 0;
  96. }
  97. static int tegra_hsp_recv(struct mbox_chan *chan, void *data)
  98. {
  99. struct tegra_hsp *thsp = dev_get_priv(chan->dev);
  100. uint32_t db_id = TEGRA_HSP_DB_ID_CCPLEX;
  101. uint32_t val;
  102. debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
  103. val = tegra_hsp_readl(thsp, db_id, TEGRA_HSP_DB_REG_RAW);
  104. if (!(val & BIT(chan->id)))
  105. return -ENODATA;
  106. tegra_hsp_writel(thsp, BIT(chan->id), db_id, TEGRA_HSP_DB_REG_RAW);
  107. return 0;
  108. }
  109. static int tegra_hsp_bind(struct udevice *dev)
  110. {
  111. debug("%s(dev=%p)\n", __func__, dev);
  112. return 0;
  113. }
  114. static int tegra_hsp_probe(struct udevice *dev)
  115. {
  116. struct tegra_hsp *thsp = dev_get_priv(dev);
  117. u32 val;
  118. int nr_sm, nr_ss, nr_as;
  119. debug("%s(dev=%p)\n", __func__, dev);
  120. thsp->regs = devfdt_get_addr(dev);
  121. if (thsp->regs == FDT_ADDR_T_NONE)
  122. return -ENODEV;
  123. val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING);
  124. nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) &
  125. TEGRA_HSP_INT_DIMENSIONING_NSM_MASK;
  126. nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) &
  127. TEGRA_HSP_INT_DIMENSIONING_NSS_MASK;
  128. nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) &
  129. TEGRA_HSP_INT_DIMENSIONING_NAS_MASK;
  130. thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
  131. return 0;
  132. }
  133. static const struct udevice_id tegra_hsp_ids[] = {
  134. { .compatible = "nvidia,tegra186-hsp" },
  135. { }
  136. };
  137. struct mbox_ops tegra_hsp_mbox_ops = {
  138. .of_xlate = tegra_hsp_of_xlate,
  139. .request = tegra_hsp_request,
  140. .rfree = tegra_hsp_free,
  141. .send = tegra_hsp_send,
  142. .recv = tegra_hsp_recv,
  143. };
  144. U_BOOT_DRIVER(tegra_hsp) = {
  145. .name = "tegra-hsp",
  146. .id = UCLASS_MAILBOX,
  147. .of_match = tegra_hsp_ids,
  148. .bind = tegra_hsp_bind,
  149. .probe = tegra_hsp_probe,
  150. .priv_auto_alloc_size = sizeof(struct tegra_hsp),
  151. .ops = &tegra_hsp_mbox_ops,
  152. };