stm32-ipcc.c 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <mailbox-uclass.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <dm/device_compat.h>
  12. /*
  13. * IPCC has one set of registers per CPU
  14. * IPCC_PROC_OFFST allows to define cpu registers set base address
  15. * according to the assigned proc_id.
  16. */
  17. #define IPCC_PROC_OFFST 0x010
  18. #define IPCC_XSCR 0x008
  19. #define IPCC_XTOYSR 0x00c
  20. #define IPCC_HWCFGR 0x3f0
  21. #define IPCFGR_CHAN_MASK GENMASK(7, 0)
  22. #define RX_BIT_CHAN(chan) BIT(chan)
  23. #define TX_BIT_SHIFT 16
  24. #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
  25. #define STM32_MAX_PROCS 2
  26. struct stm32_ipcc {
  27. void __iomem *reg_base;
  28. void __iomem *reg_proc;
  29. u32 proc_id;
  30. u32 n_chans;
  31. };
  32. static int stm32_ipcc_request(struct mbox_chan *chan)
  33. {
  34. struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
  35. debug("%s(chan=%p)\n", __func__, chan);
  36. if (chan->id >= ipcc->n_chans) {
  37. debug("%s failed to request channel: %ld\n",
  38. __func__, chan->id);
  39. return -EINVAL;
  40. }
  41. return 0;
  42. }
  43. static int stm32_ipcc_free(struct mbox_chan *chan)
  44. {
  45. debug("%s(chan=%p)\n", __func__, chan);
  46. return 0;
  47. }
  48. static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
  49. {
  50. struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
  51. debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
  52. if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
  53. return -EBUSY;
  54. /* set channel n occupied */
  55. setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
  56. return 0;
  57. }
  58. static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
  59. {
  60. struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
  61. u32 val;
  62. int proc_offset;
  63. debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
  64. /* read 'channel occupied' status from other proc */
  65. proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
  66. val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
  67. if (!(val & BIT(chan->id)))
  68. return -ENODATA;
  69. setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
  70. return 0;
  71. }
  72. static int stm32_ipcc_probe(struct udevice *dev)
  73. {
  74. struct stm32_ipcc *ipcc = dev_get_priv(dev);
  75. fdt_addr_t addr;
  76. const fdt32_t *cell;
  77. struct clk clk;
  78. int len, ret;
  79. debug("%s(dev=%p)\n", __func__, dev);
  80. addr = dev_read_addr(dev);
  81. if (addr == FDT_ADDR_T_NONE)
  82. return -EINVAL;
  83. ipcc->reg_base = (void __iomem *)addr;
  84. /* proc_id */
  85. cell = dev_read_prop(dev, "st,proc_id", &len);
  86. if (len < sizeof(fdt32_t)) {
  87. dev_dbg(dev, "Missing st,proc_id\n");
  88. return -EINVAL;
  89. }
  90. ipcc->proc_id = fdtdec_get_number(cell, 1);
  91. if (ipcc->proc_id >= STM32_MAX_PROCS) {
  92. dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
  93. return -EINVAL;
  94. }
  95. ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
  96. ret = clk_get_by_index(dev, 0, &clk);
  97. if (ret)
  98. return ret;
  99. ret = clk_enable(&clk);
  100. if (ret)
  101. goto clk_free;
  102. /* get channel number */
  103. ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
  104. ipcc->n_chans &= IPCFGR_CHAN_MASK;
  105. return 0;
  106. clk_free:
  107. clk_free(&clk);
  108. return ret;
  109. }
  110. static const struct udevice_id stm32_ipcc_ids[] = {
  111. { .compatible = "st,stm32mp1-ipcc" },
  112. { }
  113. };
  114. struct mbox_ops stm32_ipcc_mbox_ops = {
  115. .request = stm32_ipcc_request,
  116. .rfree = stm32_ipcc_free,
  117. .send = stm32_ipcc_send,
  118. .recv = stm32_ipcc_recv,
  119. };
  120. U_BOOT_DRIVER(stm32_ipcc) = {
  121. .name = "stm32_ipcc",
  122. .id = UCLASS_MAILBOX,
  123. .of_match = stm32_ipcc_ids,
  124. .probe = stm32_ipcc_probe,
  125. .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
  126. .ops = &stm32_ipcc_mbox_ops,
  127. };