tegra_i2c.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  4. * Copyright (c) 2010-2011 NVIDIA Corporation
  5. * NVIDIA Corporation <www.nvidia.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <i2c.h>
  11. #include <asm/io.h>
  12. #include <clk.h>
  13. #include <reset.h>
  14. #ifndef CONFIG_TEGRA186
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/funcmux.h>
  17. #endif
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch-tegra/tegra_i2c.h>
  20. #include <linux/err.h>
  21. enum i2c_type {
  22. TYPE_114,
  23. TYPE_STD,
  24. TYPE_DVC,
  25. };
  26. /* Information about i2c controller */
  27. struct i2c_bus {
  28. int id;
  29. struct reset_ctl reset_ctl;
  30. struct clk clk;
  31. int speed;
  32. int pinmux_config;
  33. struct i2c_control *control;
  34. struct i2c_ctlr *regs;
  35. enum i2c_type type;
  36. int inited; /* bus is inited */
  37. };
  38. static void set_packet_mode(struct i2c_bus *i2c_bus)
  39. {
  40. u32 config;
  41. config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
  42. if (i2c_bus->type == TYPE_DVC) {
  43. struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
  44. writel(config, &dvc->cnfg);
  45. } else {
  46. writel(config, &i2c_bus->regs->cnfg);
  47. /*
  48. * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
  49. * issues, i.e., some slaves may be wrongly detected.
  50. */
  51. setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
  52. }
  53. }
  54. static void i2c_reset_controller(struct i2c_bus *i2c_bus)
  55. {
  56. /* Reset I2C controller. */
  57. reset_assert(&i2c_bus->reset_ctl);
  58. udelay(1);
  59. reset_deassert(&i2c_bus->reset_ctl);
  60. udelay(1);
  61. /* re-program config register to packet mode */
  62. set_packet_mode(i2c_bus);
  63. }
  64. static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
  65. {
  66. int ret;
  67. ret = reset_assert(&i2c_bus->reset_ctl);
  68. if (ret)
  69. return ret;
  70. ret = clk_enable(&i2c_bus->clk);
  71. if (ret)
  72. return ret;
  73. ret = clk_set_rate(&i2c_bus->clk, rate);
  74. if (IS_ERR_VALUE(ret))
  75. return ret;
  76. ret = reset_deassert(&i2c_bus->reset_ctl);
  77. if (ret)
  78. return ret;
  79. return 0;
  80. }
  81. static void i2c_init_controller(struct i2c_bus *i2c_bus)
  82. {
  83. if (!i2c_bus->speed)
  84. return;
  85. debug("%s: speed=%d\n", __func__, i2c_bus->speed);
  86. /*
  87. * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
  88. * here, in section 23.3.1, but in fact we seem to need a factor of
  89. * 16 to get the right frequency.
  90. */
  91. i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
  92. if (i2c_bus->type == TYPE_114) {
  93. /*
  94. * T114 I2C went to a single clock source for standard/fast and
  95. * HS clock speeds. The new clock rate setting calculation is:
  96. * SCL = CLK_SOURCE.I2C /
  97. * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
  98. * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
  99. *
  100. * NOTE: We do this here, after the initial clock/pll start,
  101. * because if we read the clk_div reg before the controller
  102. * is running, we hang, and we need it for the new calc.
  103. */
  104. int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
  105. unsigned rate = CLK_MULT_STD_FAST_MODE *
  106. (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
  107. debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
  108. clk_div_stdfst_mode);
  109. i2c_init_clock(i2c_bus, rate);
  110. }
  111. /* Reset I2C controller. */
  112. i2c_reset_controller(i2c_bus);
  113. /* Configure I2C controller. */
  114. if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
  115. struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
  116. setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
  117. }
  118. #ifndef CONFIG_TEGRA186
  119. funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
  120. #endif
  121. }
  122. static void send_packet_headers(
  123. struct i2c_bus *i2c_bus,
  124. struct i2c_trans_info *trans,
  125. u32 packet_id,
  126. bool end_with_repeated_start)
  127. {
  128. u32 data;
  129. /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
  130. data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
  131. data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
  132. data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
  133. writel(data, &i2c_bus->control->tx_fifo);
  134. debug("pkt header 1 sent (0x%x)\n", data);
  135. /* prepare header2 */
  136. data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
  137. writel(data, &i2c_bus->control->tx_fifo);
  138. debug("pkt header 2 sent (0x%x)\n", data);
  139. /* prepare IO specific header: configure the slave address */
  140. data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
  141. /* Enable Read if it is not a write transaction */
  142. if (!(trans->flags & I2C_IS_WRITE))
  143. data |= PKT_HDR3_READ_MODE_MASK;
  144. if (end_with_repeated_start)
  145. data |= PKT_HDR3_REPEAT_START_MASK;
  146. /* Write I2C specific header */
  147. writel(data, &i2c_bus->control->tx_fifo);
  148. debug("pkt header 3 sent (0x%x)\n", data);
  149. }
  150. static int wait_for_tx_fifo_empty(struct i2c_control *control)
  151. {
  152. u32 count;
  153. int timeout_us = I2C_TIMEOUT_USEC;
  154. while (timeout_us >= 0) {
  155. count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
  156. >> TX_FIFO_EMPTY_CNT_SHIFT;
  157. if (count == I2C_FIFO_DEPTH)
  158. return 1;
  159. udelay(10);
  160. timeout_us -= 10;
  161. }
  162. return 0;
  163. }
  164. static int wait_for_rx_fifo_notempty(struct i2c_control *control)
  165. {
  166. u32 count;
  167. int timeout_us = I2C_TIMEOUT_USEC;
  168. while (timeout_us >= 0) {
  169. count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
  170. >> TX_FIFO_FULL_CNT_SHIFT;
  171. if (count)
  172. return 1;
  173. udelay(10);
  174. timeout_us -= 10;
  175. }
  176. return 0;
  177. }
  178. static int wait_for_transfer_complete(struct i2c_control *control)
  179. {
  180. int int_status;
  181. int timeout_us = I2C_TIMEOUT_USEC;
  182. while (timeout_us >= 0) {
  183. int_status = readl(&control->int_status);
  184. if (int_status & I2C_INT_NO_ACK_MASK)
  185. return -int_status;
  186. if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
  187. return -int_status;
  188. if (int_status & I2C_INT_XFER_COMPLETE_MASK)
  189. return 0;
  190. udelay(10);
  191. timeout_us -= 10;
  192. }
  193. return -1;
  194. }
  195. static int send_recv_packets(struct i2c_bus *i2c_bus,
  196. struct i2c_trans_info *trans)
  197. {
  198. struct i2c_control *control = i2c_bus->control;
  199. u32 int_status;
  200. u32 words;
  201. u8 *dptr;
  202. u32 local;
  203. uchar last_bytes;
  204. int error = 0;
  205. int is_write = trans->flags & I2C_IS_WRITE;
  206. /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
  207. int_status = readl(&control->int_status);
  208. writel(int_status, &control->int_status);
  209. send_packet_headers(i2c_bus, trans, 1,
  210. trans->flags & I2C_USE_REPEATED_START);
  211. words = DIV_ROUND_UP(trans->num_bytes, 4);
  212. last_bytes = trans->num_bytes & 3;
  213. dptr = trans->buf;
  214. while (words) {
  215. u32 *wptr = (u32 *)dptr;
  216. if (is_write) {
  217. /* deal with word alignment */
  218. if ((words == 1) && last_bytes) {
  219. local = 0;
  220. memcpy(&local, dptr, last_bytes);
  221. } else if ((unsigned long)dptr & 3) {
  222. memcpy(&local, dptr, sizeof(u32));
  223. } else {
  224. local = *wptr;
  225. }
  226. writel(local, &control->tx_fifo);
  227. debug("pkt data sent (0x%x)\n", local);
  228. if (!wait_for_tx_fifo_empty(control)) {
  229. error = -1;
  230. goto exit;
  231. }
  232. } else {
  233. if (!wait_for_rx_fifo_notempty(control)) {
  234. error = -1;
  235. goto exit;
  236. }
  237. /*
  238. * for the last word, we read into our local buffer,
  239. * in case that caller did not provide enough buffer.
  240. */
  241. local = readl(&control->rx_fifo);
  242. if ((words == 1) && last_bytes)
  243. memcpy(dptr, (char *)&local, last_bytes);
  244. else if ((unsigned long)dptr & 3)
  245. memcpy(dptr, &local, sizeof(u32));
  246. else
  247. *wptr = local;
  248. debug("pkt data received (0x%x)\n", local);
  249. }
  250. words--;
  251. dptr += sizeof(u32);
  252. }
  253. if (wait_for_transfer_complete(control)) {
  254. error = -1;
  255. goto exit;
  256. }
  257. return 0;
  258. exit:
  259. /* error, reset the controller. */
  260. i2c_reset_controller(i2c_bus);
  261. return error;
  262. }
  263. static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
  264. u32 len, bool end_with_repeated_start)
  265. {
  266. int error;
  267. struct i2c_trans_info trans_info;
  268. trans_info.address = addr;
  269. trans_info.buf = data;
  270. trans_info.flags = I2C_IS_WRITE;
  271. if (end_with_repeated_start)
  272. trans_info.flags |= I2C_USE_REPEATED_START;
  273. trans_info.num_bytes = len;
  274. trans_info.is_10bit_address = 0;
  275. error = send_recv_packets(i2c_bus, &trans_info);
  276. if (error)
  277. debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
  278. return error;
  279. }
  280. static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
  281. u32 len)
  282. {
  283. int error;
  284. struct i2c_trans_info trans_info;
  285. trans_info.address = addr | 1;
  286. trans_info.buf = data;
  287. trans_info.flags = 0;
  288. trans_info.num_bytes = len;
  289. trans_info.is_10bit_address = 0;
  290. error = send_recv_packets(i2c_bus, &trans_info);
  291. if (error)
  292. debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
  293. return error;
  294. }
  295. static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  296. {
  297. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  298. i2c_bus->speed = speed;
  299. i2c_init_controller(i2c_bus);
  300. return 0;
  301. }
  302. static int tegra_i2c_probe(struct udevice *dev)
  303. {
  304. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  305. int ret;
  306. bool is_dvc;
  307. i2c_bus->id = dev->seq;
  308. i2c_bus->type = dev_get_driver_data(dev);
  309. i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
  310. if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
  311. debug("%s: Cannot get regs address\n", __func__);
  312. return -EINVAL;
  313. }
  314. ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
  315. if (ret) {
  316. pr_err("reset_get_by_name() failed: %d\n", ret);
  317. return ret;
  318. }
  319. ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
  320. if (ret) {
  321. pr_err("clk_get_by_name() failed: %d\n", ret);
  322. return ret;
  323. }
  324. #ifndef CONFIG_TEGRA186
  325. /*
  326. * We don't have a binding for pinmux yet. Leave it out for now. So
  327. * far no one needs anything other than the default.
  328. */
  329. i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
  330. /*
  331. * We can't specify the pinmux config in the fdt, so I2C2 will not
  332. * work on Seaboard. It normally has no devices on it anyway.
  333. * You could add in this little hack if you need to use it.
  334. * The correct solution is a pinmux binding in the fdt.
  335. *
  336. * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
  337. * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
  338. */
  339. #endif
  340. is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
  341. if (is_dvc) {
  342. i2c_bus->control =
  343. &((struct dvc_ctlr *)i2c_bus->regs)->control;
  344. } else {
  345. i2c_bus->control = &i2c_bus->regs->control;
  346. }
  347. i2c_init_controller(i2c_bus);
  348. debug("%s: controller bus %d at %p, speed %d: ",
  349. is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
  350. return 0;
  351. }
  352. /* i2c write version without the register address */
  353. static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
  354. int len, bool end_with_repeated_start)
  355. {
  356. int rc;
  357. debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
  358. debug("write_data: ");
  359. /* use rc for counter */
  360. for (rc = 0; rc < len; ++rc)
  361. debug(" 0x%02x", buffer[rc]);
  362. debug("\n");
  363. /* Shift 7-bit address over for lower-level i2c functions */
  364. rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
  365. end_with_repeated_start);
  366. if (rc)
  367. debug("i2c_write_data(): rc=%d\n", rc);
  368. return rc;
  369. }
  370. /* i2c read version without the register address */
  371. static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
  372. int len)
  373. {
  374. int rc;
  375. debug("inside i2c_read_data():\n");
  376. /* Shift 7-bit address over for lower-level i2c functions */
  377. rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
  378. if (rc) {
  379. debug("i2c_read_data(): rc=%d\n", rc);
  380. return rc;
  381. }
  382. debug("i2c_read_data: ");
  383. /* reuse rc for counter*/
  384. for (rc = 0; rc < len; ++rc)
  385. debug(" 0x%02x", buffer[rc]);
  386. debug("\n");
  387. return 0;
  388. }
  389. /* Probe to see if a chip is present. */
  390. static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  391. uint chip_flags)
  392. {
  393. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  394. int rc;
  395. u8 reg;
  396. /* Shift 7-bit address over for lower-level i2c functions */
  397. rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
  398. false);
  399. return rc;
  400. }
  401. static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  402. int nmsgs)
  403. {
  404. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  405. int ret;
  406. debug("i2c_xfer: %d messages\n", nmsgs);
  407. for (; nmsgs > 0; nmsgs--, msg++) {
  408. bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
  409. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  410. if (msg->flags & I2C_M_RD) {
  411. ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
  412. msg->len);
  413. } else {
  414. ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
  415. msg->len, next_is_read);
  416. }
  417. if (ret) {
  418. debug("i2c_write: error sending\n");
  419. return -EREMOTEIO;
  420. }
  421. }
  422. return 0;
  423. }
  424. int tegra_i2c_get_dvc_bus(struct udevice **busp)
  425. {
  426. return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
  427. }
  428. static const struct dm_i2c_ops tegra_i2c_ops = {
  429. .xfer = tegra_i2c_xfer,
  430. .probe_chip = tegra_i2c_probe_chip,
  431. .set_bus_speed = tegra_i2c_set_bus_speed,
  432. };
  433. static const struct udevice_id tegra_i2c_ids[] = {
  434. { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
  435. { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
  436. { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
  437. { }
  438. };
  439. U_BOOT_DRIVER(i2c_tegra) = {
  440. .name = "i2c_tegra",
  441. .id = UCLASS_I2C,
  442. .of_match = tegra_i2c_ids,
  443. .probe = tegra_i2c_probe,
  444. .priv_auto_alloc_size = sizeof(struct i2c_bus),
  445. .ops = &tegra_i2c_ops,
  446. };