stm32f7_i2c.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017 STMicroelectronics
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <i2c.h>
  9. #include <reset.h>
  10. #include <dm/device.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. /* STM32 I2C registers */
  14. struct stm32_i2c_regs {
  15. u32 cr1; /* I2C control register 1 */
  16. u32 cr2; /* I2C control register 2 */
  17. u32 oar1; /* I2C own address 1 register */
  18. u32 oar2; /* I2C own address 2 register */
  19. u32 timingr; /* I2C timing register */
  20. u32 timeoutr; /* I2C timeout register */
  21. u32 isr; /* I2C interrupt and status register */
  22. u32 icr; /* I2C interrupt clear register */
  23. u32 pecr; /* I2C packet error checking register */
  24. u32 rxdr; /* I2C receive data register */
  25. u32 txdr; /* I2C transmit data register */
  26. };
  27. #define STM32_I2C_CR1 0x00
  28. #define STM32_I2C_CR2 0x04
  29. #define STM32_I2C_TIMINGR 0x10
  30. #define STM32_I2C_ISR 0x18
  31. #define STM32_I2C_ICR 0x1C
  32. #define STM32_I2C_RXDR 0x24
  33. #define STM32_I2C_TXDR 0x28
  34. /* STM32 I2C control 1 */
  35. #define STM32_I2C_CR1_ANFOFF BIT(12)
  36. #define STM32_I2C_CR1_ERRIE BIT(7)
  37. #define STM32_I2C_CR1_TCIE BIT(6)
  38. #define STM32_I2C_CR1_STOPIE BIT(5)
  39. #define STM32_I2C_CR1_NACKIE BIT(4)
  40. #define STM32_I2C_CR1_ADDRIE BIT(3)
  41. #define STM32_I2C_CR1_RXIE BIT(2)
  42. #define STM32_I2C_CR1_TXIE BIT(1)
  43. #define STM32_I2C_CR1_PE BIT(0)
  44. /* STM32 I2C control 2 */
  45. #define STM32_I2C_CR2_AUTOEND BIT(25)
  46. #define STM32_I2C_CR2_RELOAD BIT(24)
  47. #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
  48. #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
  49. #define STM32_I2C_CR2_NACK BIT(15)
  50. #define STM32_I2C_CR2_STOP BIT(14)
  51. #define STM32_I2C_CR2_START BIT(13)
  52. #define STM32_I2C_CR2_HEAD10R BIT(12)
  53. #define STM32_I2C_CR2_ADD10 BIT(11)
  54. #define STM32_I2C_CR2_RD_WRN BIT(10)
  55. #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
  56. #define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
  57. #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
  58. #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
  59. #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
  60. | STM32_I2C_CR2_NBYTES_MASK \
  61. | STM32_I2C_CR2_SADD7_MASK \
  62. | STM32_I2C_CR2_RELOAD \
  63. | STM32_I2C_CR2_RD_WRN)
  64. /* STM32 I2C Interrupt Status */
  65. #define STM32_I2C_ISR_BUSY BIT(15)
  66. #define STM32_I2C_ISR_ARLO BIT(9)
  67. #define STM32_I2C_ISR_BERR BIT(8)
  68. #define STM32_I2C_ISR_TCR BIT(7)
  69. #define STM32_I2C_ISR_TC BIT(6)
  70. #define STM32_I2C_ISR_STOPF BIT(5)
  71. #define STM32_I2C_ISR_NACKF BIT(4)
  72. #define STM32_I2C_ISR_ADDR BIT(3)
  73. #define STM32_I2C_ISR_RXNE BIT(2)
  74. #define STM32_I2C_ISR_TXIS BIT(1)
  75. #define STM32_I2C_ISR_TXE BIT(0)
  76. #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
  77. | STM32_I2C_ISR_ARLO)
  78. /* STM32 I2C Interrupt Clear */
  79. #define STM32_I2C_ICR_ARLOCF BIT(9)
  80. #define STM32_I2C_ICR_BERRCF BIT(8)
  81. #define STM32_I2C_ICR_STOPCF BIT(5)
  82. #define STM32_I2C_ICR_NACKCF BIT(4)
  83. /* STM32 I2C Timing */
  84. #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
  85. #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
  86. #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
  87. #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
  88. #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
  89. #define STM32_I2C_MAX_LEN 0xff
  90. #define STM32_I2C_DNF_DEFAULT 0
  91. #define STM32_I2C_DNF_MAX 16
  92. #define STM32_I2C_ANALOG_FILTER_ENABLE 1
  93. #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
  94. #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
  95. #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
  96. #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
  97. #define STM32_PRESC_MAX BIT(4)
  98. #define STM32_SCLDEL_MAX BIT(4)
  99. #define STM32_SDADEL_MAX BIT(4)
  100. #define STM32_SCLH_MAX BIT(8)
  101. #define STM32_SCLL_MAX BIT(8)
  102. #define STM32_NSEC_PER_SEC 1000000000L
  103. /**
  104. * struct stm32_i2c_spec - private i2c specification timing
  105. * @rate: I2C bus speed (Hz)
  106. * @rate_min: 80% of I2C bus speed (Hz)
  107. * @rate_max: 120% of I2C bus speed (Hz)
  108. * @fall_max: Max fall time of both SDA and SCL signals (ns)
  109. * @rise_max: Max rise time of both SDA and SCL signals (ns)
  110. * @hddat_min: Min data hold time (ns)
  111. * @vddat_max: Max data valid time (ns)
  112. * @sudat_min: Min data setup time (ns)
  113. * @l_min: Min low period of the SCL clock (ns)
  114. * @h_min: Min high period of the SCL clock (ns)
  115. */
  116. struct stm32_i2c_spec {
  117. u32 rate;
  118. u32 rate_min;
  119. u32 rate_max;
  120. u32 fall_max;
  121. u32 rise_max;
  122. u32 hddat_min;
  123. u32 vddat_max;
  124. u32 sudat_min;
  125. u32 l_min;
  126. u32 h_min;
  127. };
  128. /**
  129. * struct stm32_i2c_setup - private I2C timing setup parameters
  130. * @speed_freq: I2C speed frequency (Hz)
  131. * @clock_src: I2C clock source frequency (Hz)
  132. * @rise_time: Rise time (ns)
  133. * @fall_time: Fall time (ns)
  134. * @dnf: Digital filter coefficient (0-16)
  135. * @analog_filter: Analog filter delay (On/Off)
  136. */
  137. struct stm32_i2c_setup {
  138. u32 speed_freq;
  139. u32 clock_src;
  140. u32 rise_time;
  141. u32 fall_time;
  142. u8 dnf;
  143. bool analog_filter;
  144. };
  145. /**
  146. * struct stm32_i2c_timings - private I2C output parameters
  147. * @prec: Prescaler value
  148. * @scldel: Data setup time
  149. * @sdadel: Data hold time
  150. * @sclh: SCL high period (master mode)
  151. * @sclh: SCL low period (master mode)
  152. */
  153. struct stm32_i2c_timings {
  154. struct list_head node;
  155. u8 presc;
  156. u8 scldel;
  157. u8 sdadel;
  158. u8 sclh;
  159. u8 scll;
  160. };
  161. struct stm32_i2c_priv {
  162. struct stm32_i2c_regs *regs;
  163. struct clk clk;
  164. struct stm32_i2c_setup *setup;
  165. u32 speed;
  166. };
  167. static const struct stm32_i2c_spec i2c_specs[] = {
  168. /* Standard speed - 100 KHz */
  169. [IC_SPEED_MODE_STANDARD] = {
  170. .rate = I2C_SPEED_STANDARD_RATE,
  171. .rate_min = 8000,
  172. .rate_max = 120000,
  173. .fall_max = 300,
  174. .rise_max = 1000,
  175. .hddat_min = 0,
  176. .vddat_max = 3450,
  177. .sudat_min = 250,
  178. .l_min = 4700,
  179. .h_min = 4000,
  180. },
  181. /* Fast speed - 400 KHz */
  182. [IC_SPEED_MODE_FAST] = {
  183. .rate = I2C_SPEED_FAST_RATE,
  184. .rate_min = 320000,
  185. .rate_max = 480000,
  186. .fall_max = 300,
  187. .rise_max = 300,
  188. .hddat_min = 0,
  189. .vddat_max = 900,
  190. .sudat_min = 100,
  191. .l_min = 1300,
  192. .h_min = 600,
  193. },
  194. /* Fast Plus Speed - 1 MHz */
  195. [IC_SPEED_MODE_FAST_PLUS] = {
  196. .rate = I2C_SPEED_FAST_PLUS_RATE,
  197. .rate_min = 800000,
  198. .rate_max = 1200000,
  199. .fall_max = 100,
  200. .rise_max = 120,
  201. .hddat_min = 0,
  202. .vddat_max = 450,
  203. .sudat_min = 50,
  204. .l_min = 500,
  205. .h_min = 260,
  206. },
  207. };
  208. static const struct stm32_i2c_setup stm32f7_setup = {
  209. .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
  210. .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
  211. .dnf = STM32_I2C_DNF_DEFAULT,
  212. .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
  213. };
  214. static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
  215. {
  216. struct stm32_i2c_regs *regs = i2c_priv->regs;
  217. u32 status = readl(&regs->isr);
  218. if (status & STM32_I2C_ISR_BUSY)
  219. return -EBUSY;
  220. return 0;
  221. }
  222. static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
  223. struct i2c_msg *msg, bool stop)
  224. {
  225. struct stm32_i2c_regs *regs = i2c_priv->regs;
  226. u32 cr2 = readl(&regs->cr2);
  227. /* Set transfer direction */
  228. cr2 &= ~STM32_I2C_CR2_RD_WRN;
  229. if (msg->flags & I2C_M_RD)
  230. cr2 |= STM32_I2C_CR2_RD_WRN;
  231. /* Set slave address */
  232. cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
  233. if (msg->flags & I2C_M_TEN) {
  234. cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
  235. cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
  236. cr2 |= STM32_I2C_CR2_ADD10;
  237. } else {
  238. cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
  239. cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
  240. }
  241. /* Set nb bytes to transfer and reload or autoend bits */
  242. cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
  243. STM32_I2C_CR2_AUTOEND);
  244. if (msg->len > STM32_I2C_MAX_LEN) {
  245. cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
  246. cr2 |= STM32_I2C_CR2_RELOAD;
  247. } else {
  248. cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
  249. }
  250. /* Write configurations register */
  251. writel(cr2, &regs->cr2);
  252. /* START/ReSTART generation */
  253. setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
  254. }
  255. /*
  256. * RELOAD mode must be selected if total number of data bytes to be
  257. * sent is greater than MAX_LEN
  258. */
  259. static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
  260. struct i2c_msg *msg, bool stop)
  261. {
  262. struct stm32_i2c_regs *regs = i2c_priv->regs;
  263. u32 cr2 = readl(&regs->cr2);
  264. cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
  265. if (msg->len > STM32_I2C_MAX_LEN) {
  266. cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
  267. } else {
  268. cr2 &= ~STM32_I2C_CR2_RELOAD;
  269. cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
  270. }
  271. writel(cr2, &regs->cr2);
  272. }
  273. static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
  274. u32 flags, u32 *status)
  275. {
  276. struct stm32_i2c_regs *regs = i2c_priv->regs;
  277. u32 time_start = get_timer(0);
  278. *status = readl(&regs->isr);
  279. while (!(*status & flags)) {
  280. if (get_timer(time_start) > CONFIG_SYS_HZ) {
  281. debug("%s: i2c timeout\n", __func__);
  282. return -ETIMEDOUT;
  283. }
  284. *status = readl(&regs->isr);
  285. }
  286. return 0;
  287. }
  288. static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
  289. {
  290. struct stm32_i2c_regs *regs = i2c_priv->regs;
  291. u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
  292. STM32_I2C_ISR_STOPF;
  293. u32 status;
  294. int ret;
  295. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  296. if (ret)
  297. return ret;
  298. if (status & STM32_I2C_ISR_BERR) {
  299. debug("%s: Bus error\n", __func__);
  300. /* Clear BERR flag */
  301. setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
  302. return -EIO;
  303. }
  304. if (status & STM32_I2C_ISR_ARLO) {
  305. debug("%s: Arbitration lost\n", __func__);
  306. /* Clear ARLO flag */
  307. setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
  308. return -EAGAIN;
  309. }
  310. if (status & STM32_I2C_ISR_NACKF) {
  311. debug("%s: Receive NACK\n", __func__);
  312. /* Clear NACK flag */
  313. setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
  314. /* Wait until STOPF flag is set */
  315. mask = STM32_I2C_ISR_STOPF;
  316. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  317. if (ret)
  318. return ret;
  319. ret = -EIO;
  320. }
  321. if (status & STM32_I2C_ISR_STOPF) {
  322. /* Clear STOP flag */
  323. setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
  324. /* Clear control register 2 */
  325. setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
  326. }
  327. return ret;
  328. }
  329. static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
  330. struct i2c_msg *msg, bool stop)
  331. {
  332. struct stm32_i2c_regs *regs = i2c_priv->regs;
  333. u32 status;
  334. u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
  335. STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
  336. int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
  337. STM32_I2C_MAX_LEN : msg->len;
  338. int ret = 0;
  339. /* Add errors */
  340. mask |= STM32_I2C_ISR_ERRORS;
  341. stm32_i2c_message_start(i2c_priv, msg, stop);
  342. while (msg->len) {
  343. /*
  344. * Wait until TXIS/NACKF/BERR/ARLO flags or
  345. * RXNE/BERR/ARLO flags are set
  346. */
  347. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  348. if (ret)
  349. break;
  350. if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
  351. break;
  352. if (status & STM32_I2C_ISR_RXNE) {
  353. *msg->buf++ = readb(&regs->rxdr);
  354. msg->len--;
  355. bytes_to_rw--;
  356. }
  357. if (status & STM32_I2C_ISR_TXIS) {
  358. writeb(*msg->buf++, &regs->txdr);
  359. msg->len--;
  360. bytes_to_rw--;
  361. }
  362. if (!bytes_to_rw && msg->len) {
  363. /* Wait until TCR flag is set */
  364. mask = STM32_I2C_ISR_TCR;
  365. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  366. if (ret)
  367. break;
  368. bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
  369. STM32_I2C_MAX_LEN : msg->len;
  370. mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
  371. STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
  372. stm32_i2c_handle_reload(i2c_priv, msg, stop);
  373. } else if (!bytes_to_rw) {
  374. /* Wait until TC flag is set */
  375. mask = STM32_I2C_ISR_TC;
  376. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  377. if (ret)
  378. break;
  379. if (!stop)
  380. /* Message sent, new message has to be sent */
  381. return 0;
  382. }
  383. }
  384. /* End of transfer, send stop condition */
  385. mask = STM32_I2C_CR2_STOP;
  386. setbits_le32(&regs->cr2, mask);
  387. return stm32_i2c_check_end_of_message(i2c_priv);
  388. }
  389. static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  390. int nmsgs)
  391. {
  392. struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
  393. int ret;
  394. ret = stm32_i2c_check_device_busy(i2c_priv);
  395. if (ret)
  396. return ret;
  397. for (; nmsgs > 0; nmsgs--, msg++) {
  398. ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
  399. if (ret)
  400. return ret;
  401. }
  402. return 0;
  403. }
  404. static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
  405. const struct stm32_i2c_spec *specs,
  406. struct list_head *solutions)
  407. {
  408. struct stm32_i2c_timings *v;
  409. u32 p_prev = STM32_PRESC_MAX;
  410. u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
  411. setup->clock_src);
  412. u32 af_delay_min, af_delay_max;
  413. u16 p, l, a;
  414. int sdadel_min, sdadel_max, scldel_min;
  415. int ret = 0;
  416. af_delay_min = setup->analog_filter ?
  417. STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
  418. af_delay_max = setup->analog_filter ?
  419. STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
  420. sdadel_min = specs->hddat_min + setup->fall_time -
  421. af_delay_min - (setup->dnf + 3) * i2cclk;
  422. sdadel_max = specs->vddat_max - setup->rise_time -
  423. af_delay_max - (setup->dnf + 4) * i2cclk;
  424. scldel_min = setup->rise_time + specs->sudat_min;
  425. if (sdadel_min < 0)
  426. sdadel_min = 0;
  427. if (sdadel_max < 0)
  428. sdadel_max = 0;
  429. debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
  430. sdadel_min, sdadel_max, scldel_min);
  431. /* Compute possible values for PRESC, SCLDEL and SDADEL */
  432. for (p = 0; p < STM32_PRESC_MAX; p++) {
  433. for (l = 0; l < STM32_SCLDEL_MAX; l++) {
  434. int scldel = (l + 1) * (p + 1) * i2cclk;
  435. if (scldel < scldel_min)
  436. continue;
  437. for (a = 0; a < STM32_SDADEL_MAX; a++) {
  438. int sdadel = (a * (p + 1) + 1) * i2cclk;
  439. if (((sdadel >= sdadel_min) &&
  440. (sdadel <= sdadel_max)) &&
  441. (p != p_prev)) {
  442. v = calloc(1, sizeof(*v));
  443. if (!v)
  444. return -ENOMEM;
  445. v->presc = p;
  446. v->scldel = l;
  447. v->sdadel = a;
  448. p_prev = p;
  449. list_add_tail(&v->node, solutions);
  450. break;
  451. }
  452. }
  453. if (p_prev == p)
  454. break;
  455. }
  456. }
  457. if (list_empty(solutions)) {
  458. pr_err("%s: no Prescaler solution\n", __func__);
  459. ret = -EPERM;
  460. }
  461. return ret;
  462. }
  463. static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
  464. const struct stm32_i2c_spec *specs,
  465. struct list_head *solutions,
  466. struct stm32_i2c_timings *s)
  467. {
  468. struct stm32_i2c_timings *v;
  469. u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
  470. setup->speed_freq);
  471. u32 clk_error_prev = i2cbus;
  472. u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
  473. setup->clock_src);
  474. u32 clk_min, clk_max;
  475. u32 af_delay_min;
  476. u32 dnf_delay;
  477. u32 tsync;
  478. u16 l, h;
  479. bool sol_found = false;
  480. int ret = 0;
  481. af_delay_min = setup->analog_filter ?
  482. STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
  483. dnf_delay = setup->dnf * i2cclk;
  484. tsync = af_delay_min + dnf_delay + (2 * i2cclk);
  485. clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
  486. clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
  487. /*
  488. * Among Prescaler possibilities discovered above figures out SCL Low
  489. * and High Period. Provided:
  490. * - SCL Low Period has to be higher than Low Period of the SCL Clock
  491. * defined by I2C Specification. I2C Clock has to be lower than
  492. * (SCL Low Period - Analog/Digital filters) / 4.
  493. * - SCL High Period has to be lower than High Period of the SCL Clock
  494. * defined by I2C Specification
  495. * - I2C Clock has to be lower than SCL High Period
  496. */
  497. list_for_each_entry(v, solutions, node) {
  498. u32 prescaler = (v->presc + 1) * i2cclk;
  499. for (l = 0; l < STM32_SCLL_MAX; l++) {
  500. u32 tscl_l = (l + 1) * prescaler + tsync;
  501. if (tscl_l < specs->l_min ||
  502. (i2cclk >=
  503. ((tscl_l - af_delay_min - dnf_delay) / 4))) {
  504. continue;
  505. }
  506. for (h = 0; h < STM32_SCLH_MAX; h++) {
  507. u32 tscl_h = (h + 1) * prescaler + tsync;
  508. u32 tscl = tscl_l + tscl_h +
  509. setup->rise_time + setup->fall_time;
  510. if ((tscl >= clk_min) && (tscl <= clk_max) &&
  511. (tscl_h >= specs->h_min) &&
  512. (i2cclk < tscl_h)) {
  513. u32 clk_error;
  514. if (tscl > i2cbus)
  515. clk_error = tscl - i2cbus;
  516. else
  517. clk_error = i2cbus - tscl;
  518. if (clk_error < clk_error_prev) {
  519. clk_error_prev = clk_error;
  520. v->scll = l;
  521. v->sclh = h;
  522. sol_found = true;
  523. memcpy(s, v, sizeof(*s));
  524. }
  525. }
  526. }
  527. }
  528. }
  529. if (!sol_found) {
  530. pr_err("%s: no solution at all\n", __func__);
  531. ret = -EPERM;
  532. }
  533. return ret;
  534. }
  535. static const struct stm32_i2c_spec *get_specs(u32 rate)
  536. {
  537. unsigned int i;
  538. for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
  539. if (rate <= i2c_specs[i].rate)
  540. return &i2c_specs[i];
  541. /* NOT REACHED */
  542. return ERR_PTR(-EINVAL);
  543. }
  544. static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
  545. struct stm32_i2c_setup *setup,
  546. struct stm32_i2c_timings *output)
  547. {
  548. const struct stm32_i2c_spec *specs;
  549. struct stm32_i2c_timings *v, *_v;
  550. struct list_head solutions;
  551. int ret;
  552. specs = get_specs(setup->speed_freq);
  553. if (specs == ERR_PTR(-EINVAL)) {
  554. pr_err("%s: speed out of bound {%d}\n", __func__,
  555. setup->speed_freq);
  556. return -EINVAL;
  557. }
  558. if (setup->rise_time > specs->rise_max ||
  559. setup->fall_time > specs->fall_max) {
  560. pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
  561. __func__,
  562. setup->rise_time, specs->rise_max,
  563. setup->fall_time, specs->fall_max);
  564. return -EINVAL;
  565. }
  566. if (setup->dnf > STM32_I2C_DNF_MAX) {
  567. pr_err("%s: DNF out of bound %d/%d\n", __func__,
  568. setup->dnf, STM32_I2C_DNF_MAX);
  569. return -EINVAL;
  570. }
  571. INIT_LIST_HEAD(&solutions);
  572. ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
  573. if (ret)
  574. goto exit;
  575. ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
  576. if (ret)
  577. goto exit;
  578. debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
  579. __func__, output->presc,
  580. output->scldel, output->sdadel,
  581. output->scll, output->sclh);
  582. exit:
  583. /* Release list and memory */
  584. list_for_each_entry_safe(v, _v, &solutions, node) {
  585. list_del(&v->node);
  586. free(v);
  587. }
  588. return ret;
  589. }
  590. static u32 get_lower_rate(u32 rate)
  591. {
  592. int i;
  593. for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
  594. if (rate > i2c_specs[i].rate)
  595. return i2c_specs[i].rate;
  596. return i2c_specs[0].rate;
  597. }
  598. static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
  599. struct stm32_i2c_timings *timing)
  600. {
  601. struct stm32_i2c_setup *setup = i2c_priv->setup;
  602. int ret = 0;
  603. setup->speed_freq = i2c_priv->speed;
  604. setup->clock_src = clk_get_rate(&i2c_priv->clk);
  605. if (!setup->clock_src) {
  606. pr_err("%s: clock rate is 0\n", __func__);
  607. return -EINVAL;
  608. }
  609. do {
  610. ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
  611. if (ret) {
  612. debug("%s: failed to compute I2C timings.\n",
  613. __func__);
  614. if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
  615. setup->speed_freq =
  616. get_lower_rate(setup->speed_freq);
  617. debug("%s: downgrade I2C Speed Freq to (%i)\n",
  618. __func__, setup->speed_freq);
  619. } else {
  620. break;
  621. }
  622. }
  623. } while (ret);
  624. if (ret) {
  625. pr_err("%s: impossible to compute I2C timings.\n", __func__);
  626. return ret;
  627. }
  628. debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
  629. setup->speed_freq, setup->clock_src);
  630. debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
  631. setup->rise_time, setup->fall_time);
  632. debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
  633. setup->analog_filter ? "On" : "Off", setup->dnf);
  634. i2c_priv->speed = setup->speed_freq;
  635. return 0;
  636. }
  637. static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
  638. {
  639. struct stm32_i2c_regs *regs = i2c_priv->regs;
  640. struct stm32_i2c_timings t;
  641. int ret;
  642. u32 timing = 0;
  643. ret = stm32_i2c_setup_timing(i2c_priv, &t);
  644. if (ret)
  645. return ret;
  646. /* Disable I2C */
  647. clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
  648. /* Timing settings */
  649. timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
  650. timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
  651. timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
  652. timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
  653. timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
  654. writel(timing, &regs->timingr);
  655. /* Enable I2C */
  656. if (i2c_priv->setup->analog_filter)
  657. clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
  658. else
  659. setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
  660. setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
  661. return 0;
  662. }
  663. static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  664. {
  665. struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
  666. if (speed > I2C_SPEED_FAST_PLUS_RATE) {
  667. debug("%s: Speed %d not supported\n", __func__, speed);
  668. return -EINVAL;
  669. }
  670. i2c_priv->speed = speed;
  671. return stm32_i2c_hw_config(i2c_priv);
  672. }
  673. static int stm32_i2c_probe(struct udevice *dev)
  674. {
  675. struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
  676. struct reset_ctl reset_ctl;
  677. fdt_addr_t addr;
  678. int ret;
  679. addr = dev_read_addr(dev);
  680. if (addr == FDT_ADDR_T_NONE)
  681. return -EINVAL;
  682. i2c_priv->regs = (struct stm32_i2c_regs *)addr;
  683. ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
  684. if (ret)
  685. return ret;
  686. ret = clk_enable(&i2c_priv->clk);
  687. if (ret)
  688. goto clk_free;
  689. ret = reset_get_by_index(dev, 0, &reset_ctl);
  690. if (ret)
  691. goto clk_disable;
  692. reset_assert(&reset_ctl);
  693. udelay(2);
  694. reset_deassert(&reset_ctl);
  695. return 0;
  696. clk_disable:
  697. clk_disable(&i2c_priv->clk);
  698. clk_free:
  699. clk_free(&i2c_priv->clk);
  700. return ret;
  701. }
  702. static int stm32_ofdata_to_platdata(struct udevice *dev)
  703. {
  704. struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
  705. u32 rise_time, fall_time;
  706. i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
  707. if (!i2c_priv->setup)
  708. return -EINVAL;
  709. rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
  710. if (rise_time)
  711. i2c_priv->setup->rise_time = rise_time;
  712. fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
  713. if (fall_time)
  714. i2c_priv->setup->fall_time = fall_time;
  715. return 0;
  716. }
  717. static const struct dm_i2c_ops stm32_i2c_ops = {
  718. .xfer = stm32_i2c_xfer,
  719. .set_bus_speed = stm32_i2c_set_bus_speed,
  720. };
  721. static const struct udevice_id stm32_i2c_of_match[] = {
  722. { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
  723. {}
  724. };
  725. U_BOOT_DRIVER(stm32f7_i2c) = {
  726. .name = "stm32f7-i2c",
  727. .id = UCLASS_I2C,
  728. .of_match = stm32_i2c_of_match,
  729. .ofdata_to_platdata = stm32_ofdata_to_platdata,
  730. .probe = stm32_i2c_probe,
  731. .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
  732. .ops = &stm32_i2c_ops,
  733. };