s3c24x0_i2c.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/pinmux.h>
  14. #else
  15. #include <asm/arch/s3c24x0_cpu.h>
  16. #endif
  17. #include <asm/io.h>
  18. #include <i2c.h>
  19. #include "s3c24x0_i2c.h"
  20. #ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
  21. #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
  22. #else
  23. #define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
  24. #endif
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /*
  27. * Wait til the byte transfer is completed.
  28. *
  29. * @param i2c- pointer to the appropriate i2c register bank.
  30. * @return I2C_OK, if transmission was ACKED
  31. * I2C_NACK, if transmission was NACKED
  32. * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
  33. */
  34. static int WaitForXfer(struct s3c24x0_i2c *i2c)
  35. {
  36. ulong start_time = get_timer(0);
  37. do {
  38. if (readl(&i2c->iiccon) & I2CCON_IRPND)
  39. return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
  40. I2C_NACK : I2C_OK;
  41. } while (get_timer(start_time) < I2C_TIMEOUT_MS);
  42. return I2C_NOK_TOUT;
  43. }
  44. static void read_write_byte(struct s3c24x0_i2c *i2c)
  45. {
  46. clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
  47. }
  48. static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
  49. {
  50. ulong freq, pres = 16, div;
  51. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  52. freq = get_i2c_clk();
  53. #else
  54. freq = get_PCLK();
  55. #endif
  56. /* calculate prescaler and divisor values */
  57. if ((freq / pres / (16 + 1)) > speed)
  58. /* set prescaler to 512 */
  59. pres = 512;
  60. div = 0;
  61. while ((freq / pres / (div + 1)) > speed)
  62. div++;
  63. /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
  64. writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
  65. /* init to SLAVE REVEIVE and set slaveaddr */
  66. writel(0, &i2c->iicstat);
  67. writel(slaveadd, &i2c->iicadd);
  68. /* program Master Transmit (and implicit STOP) */
  69. writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
  70. }
  71. static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  72. {
  73. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  74. i2c_bus->clock_frequency = speed;
  75. i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
  76. SYS_I2C_S3C24X0_SLAVE_ADDR);
  77. return 0;
  78. }
  79. /*
  80. * cmd_type is 0 for write, 1 for read.
  81. *
  82. * addr_len can take any value from 0-255, it is only limited
  83. * by the char, we could make it larger if needed. If it is
  84. * 0 we skip the address write cycle.
  85. */
  86. static int i2c_transfer(struct s3c24x0_i2c *i2c,
  87. unsigned char cmd_type,
  88. unsigned char chip,
  89. unsigned char addr[],
  90. unsigned char addr_len,
  91. unsigned char data[],
  92. unsigned short data_len)
  93. {
  94. int i = 0, result;
  95. ulong start_time = get_timer(0);
  96. if (data == 0 || data_len == 0) {
  97. /*Don't support data transfer of no length or to address 0 */
  98. debug("i2c_transfer: bad call\n");
  99. return I2C_NOK;
  100. }
  101. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  102. if (get_timer(start_time) > I2C_TIMEOUT_MS)
  103. return I2C_NOK_TOUT;
  104. }
  105. writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
  106. /* Get the slave chip address going */
  107. writel(chip, &i2c->iicds);
  108. if ((cmd_type == I2C_WRITE) || (addr && addr_len))
  109. writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
  110. &i2c->iicstat);
  111. else
  112. writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
  113. &i2c->iicstat);
  114. /* Wait for chip address to transmit. */
  115. result = WaitForXfer(i2c);
  116. if (result != I2C_OK)
  117. goto bailout;
  118. /* If register address needs to be transmitted - do it now. */
  119. if (addr && addr_len) {
  120. while ((i < addr_len) && (result == I2C_OK)) {
  121. writel(addr[i++], &i2c->iicds);
  122. read_write_byte(i2c);
  123. result = WaitForXfer(i2c);
  124. }
  125. i = 0;
  126. if (result != I2C_OK)
  127. goto bailout;
  128. }
  129. switch (cmd_type) {
  130. case I2C_WRITE:
  131. while ((i < data_len) && (result == I2C_OK)) {
  132. writel(data[i++], &i2c->iicds);
  133. read_write_byte(i2c);
  134. result = WaitForXfer(i2c);
  135. }
  136. break;
  137. case I2C_READ:
  138. if (addr && addr_len) {
  139. /*
  140. * Register address has been sent, now send slave chip
  141. * address again to start the actual read transaction.
  142. */
  143. writel(chip, &i2c->iicds);
  144. /* Generate a re-START. */
  145. writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
  146. &i2c->iicstat);
  147. read_write_byte(i2c);
  148. result = WaitForXfer(i2c);
  149. if (result != I2C_OK)
  150. goto bailout;
  151. }
  152. while ((i < data_len) && (result == I2C_OK)) {
  153. /* disable ACK for final READ */
  154. if (i == data_len - 1)
  155. writel(readl(&i2c->iiccon)
  156. & ~I2CCON_ACKGEN,
  157. &i2c->iiccon);
  158. read_write_byte(i2c);
  159. result = WaitForXfer(i2c);
  160. data[i++] = readl(&i2c->iicds);
  161. }
  162. if (result == I2C_NACK)
  163. result = I2C_OK; /* Normal terminated read. */
  164. break;
  165. default:
  166. debug("i2c_transfer: bad call\n");
  167. result = I2C_NOK;
  168. break;
  169. }
  170. bailout:
  171. /* Send STOP. */
  172. writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
  173. read_write_byte(i2c);
  174. return result;
  175. }
  176. static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
  177. {
  178. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  179. uchar buf[1];
  180. int ret;
  181. buf[0] = 0;
  182. /*
  183. * What is needed is to send the chip address and verify that the
  184. * address was <ACK>ed (i.e. there was a chip at that address which
  185. * drove the data line low).
  186. */
  187. ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
  188. return ret != I2C_OK;
  189. }
  190. static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
  191. int seq)
  192. {
  193. struct s3c24x0_i2c *i2c = i2c_bus->regs;
  194. bool is_read = msg->flags & I2C_M_RD;
  195. uint status;
  196. uint addr;
  197. int ret, i;
  198. if (!seq)
  199. setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  200. /* Get the slave chip address going */
  201. addr = msg->addr << 1;
  202. writel(addr, &i2c->iicds);
  203. status = I2C_TXRX_ENA | I2C_START_STOP;
  204. if (is_read)
  205. status |= I2C_MODE_MR;
  206. else
  207. status |= I2C_MODE_MT;
  208. writel(status, &i2c->iicstat);
  209. if (seq)
  210. read_write_byte(i2c);
  211. /* Wait for chip address to transmit */
  212. ret = WaitForXfer(i2c);
  213. if (ret)
  214. goto err;
  215. if (is_read) {
  216. for (i = 0; !ret && i < msg->len; i++) {
  217. /* disable ACK for final READ */
  218. if (i == msg->len - 1)
  219. clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  220. read_write_byte(i2c);
  221. ret = WaitForXfer(i2c);
  222. msg->buf[i] = readl(&i2c->iicds);
  223. }
  224. if (ret == I2C_NACK)
  225. ret = I2C_OK; /* Normal terminated read */
  226. } else {
  227. for (i = 0; !ret && i < msg->len; i++) {
  228. writel(msg->buf[i], &i2c->iicds);
  229. read_write_byte(i2c);
  230. ret = WaitForXfer(i2c);
  231. }
  232. }
  233. err:
  234. return ret;
  235. }
  236. static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  237. int nmsgs)
  238. {
  239. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  240. struct s3c24x0_i2c *i2c = i2c_bus->regs;
  241. ulong start_time;
  242. int ret, i;
  243. start_time = get_timer(0);
  244. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  245. if (get_timer(start_time) > I2C_TIMEOUT_MS) {
  246. debug("Timeout\n");
  247. return -ETIMEDOUT;
  248. }
  249. }
  250. for (ret = 0, i = 0; !ret && i < nmsgs; i++)
  251. ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
  252. /* Send STOP */
  253. writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
  254. read_write_byte(i2c);
  255. return ret ? -EREMOTEIO : 0;
  256. }
  257. static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
  258. {
  259. const void *blob = gd->fdt_blob;
  260. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  261. int node;
  262. node = dev_of_offset(dev);
  263. i2c_bus->regs = (struct s3c24x0_i2c *)devfdt_get_addr(dev);
  264. i2c_bus->id = pinmux_decode_periph_id(blob, node);
  265. i2c_bus->clock_frequency =
  266. dev_read_u32_default(dev, "clock-frequency",
  267. I2C_SPEED_STANDARD_RATE);
  268. i2c_bus->node = node;
  269. i2c_bus->bus_num = dev->seq;
  270. exynos_pinmux_config(i2c_bus->id, 0);
  271. i2c_bus->active = true;
  272. return 0;
  273. }
  274. static const struct dm_i2c_ops s3c_i2c_ops = {
  275. .xfer = s3c24x0_i2c_xfer,
  276. .probe_chip = s3c24x0_i2c_probe,
  277. .set_bus_speed = s3c24x0_i2c_set_bus_speed,
  278. };
  279. static const struct udevice_id s3c_i2c_ids[] = {
  280. { .compatible = "samsung,s3c2440-i2c" },
  281. { }
  282. };
  283. U_BOOT_DRIVER(i2c_s3c) = {
  284. .name = "i2c_s3c",
  285. .id = UCLASS_I2C,
  286. .of_match = s3c_i2c_ids,
  287. .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
  288. .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
  289. .ops = &s3c_i2c_ops,
  290. };