rk_i2c.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. *
  5. * (C) Copyright 2008-2014 Rockchip Electronics
  6. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <i2c.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/i2c.h>
  16. #include <asm/arch-rockchip/periph.h>
  17. #include <dm/pinctrl.h>
  18. #include <linux/sizes.h>
  19. /* i2c timerout */
  20. #define I2C_TIMEOUT_MS 100
  21. #define I2C_RETRY_COUNT 3
  22. /* rk i2c fifo max transfer bytes */
  23. #define RK_I2C_FIFO_SIZE 32
  24. struct rk_i2c {
  25. struct clk clk;
  26. struct i2c_regs *regs;
  27. unsigned int speed;
  28. };
  29. enum {
  30. RK_I2C_LEGACY,
  31. RK_I2C_NEW,
  32. };
  33. /**
  34. * @controller_type: i2c controller type
  35. */
  36. struct rk_i2c_soc_data {
  37. int controller_type;
  38. };
  39. static inline void rk_i2c_get_div(int div, int *divh, int *divl)
  40. {
  41. *divl = div / 2;
  42. if (div % 2 == 0)
  43. *divh = div / 2;
  44. else
  45. *divh = DIV_ROUND_UP(div, 2);
  46. }
  47. /*
  48. * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
  49. * SCL = PCLK / SCLK Divisor
  50. * i2c_rate = PCLK
  51. */
  52. static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
  53. {
  54. uint32_t i2c_rate;
  55. int div, divl, divh;
  56. /* First get i2c rate from pclk */
  57. i2c_rate = clk_get_rate(&i2c->clk);
  58. div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
  59. divh = 0;
  60. divl = 0;
  61. if (div >= 0)
  62. rk_i2c_get_div(div, &divh, &divl);
  63. writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
  64. debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
  65. scl_rate);
  66. debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
  67. debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
  68. }
  69. static void rk_i2c_show_regs(struct i2c_regs *regs)
  70. {
  71. #ifdef DEBUG
  72. uint i;
  73. debug("i2c_con: 0x%08x\n", readl(&regs->con));
  74. debug("i2c_clkdiv: 0x%08x\n", readl(&regs->clkdiv));
  75. debug("i2c_mrxaddr: 0x%08x\n", readl(&regs->mrxaddr));
  76. debug("i2c_mrxraddR: 0x%08x\n", readl(&regs->mrxraddr));
  77. debug("i2c_mtxcnt: 0x%08x\n", readl(&regs->mtxcnt));
  78. debug("i2c_mrxcnt: 0x%08x\n", readl(&regs->mrxcnt));
  79. debug("i2c_ien: 0x%08x\n", readl(&regs->ien));
  80. debug("i2c_ipd: 0x%08x\n", readl(&regs->ipd));
  81. debug("i2c_fcnt: 0x%08x\n", readl(&regs->fcnt));
  82. for (i = 0; i < 8; i++)
  83. debug("i2c_txdata%d: 0x%08x\n", i, readl(&regs->txdata[i]));
  84. for (i = 0; i < 8; i++)
  85. debug("i2c_rxdata%d: 0x%08x\n", i, readl(&regs->rxdata[i]));
  86. #endif
  87. }
  88. static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
  89. {
  90. struct i2c_regs *regs = i2c->regs;
  91. ulong start;
  92. debug("I2c Send Start bit.\n");
  93. writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
  94. writel(I2C_CON_EN | I2C_CON_START, &regs->con);
  95. writel(I2C_STARTIEN, &regs->ien);
  96. start = get_timer(0);
  97. while (1) {
  98. if (readl(&regs->ipd) & I2C_STARTIPD) {
  99. writel(I2C_STARTIPD, &regs->ipd);
  100. break;
  101. }
  102. if (get_timer(start) > I2C_TIMEOUT_MS) {
  103. debug("I2C Send Start Bit Timeout\n");
  104. rk_i2c_show_regs(regs);
  105. return -ETIMEDOUT;
  106. }
  107. udelay(1);
  108. }
  109. return 0;
  110. }
  111. static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
  112. {
  113. struct i2c_regs *regs = i2c->regs;
  114. ulong start;
  115. debug("I2c Send Stop bit.\n");
  116. writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
  117. writel(I2C_CON_EN | I2C_CON_STOP, &regs->con);
  118. writel(I2C_CON_STOP, &regs->ien);
  119. start = get_timer(0);
  120. while (1) {
  121. if (readl(&regs->ipd) & I2C_STOPIPD) {
  122. writel(I2C_STOPIPD, &regs->ipd);
  123. break;
  124. }
  125. if (get_timer(start) > I2C_TIMEOUT_MS) {
  126. debug("I2C Send Start Bit Timeout\n");
  127. rk_i2c_show_regs(regs);
  128. return -ETIMEDOUT;
  129. }
  130. udelay(1);
  131. }
  132. return 0;
  133. }
  134. static inline void rk_i2c_disable(struct rk_i2c *i2c)
  135. {
  136. writel(0, &i2c->regs->con);
  137. }
  138. static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
  139. uchar *buf, uint b_len)
  140. {
  141. struct i2c_regs *regs = i2c->regs;
  142. uchar *pbuf = buf;
  143. uint bytes_remain_len = b_len;
  144. uint bytes_xferred = 0;
  145. uint words_xferred = 0;
  146. ulong start;
  147. uint con = 0;
  148. uint rxdata;
  149. uint i, j;
  150. int err;
  151. bool snd_chunk = false;
  152. debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
  153. chip, reg, r_len, b_len);
  154. err = rk_i2c_send_start_bit(i2c);
  155. if (err)
  156. return err;
  157. writel(I2C_MRXADDR_SET(1, chip << 1 | 1), &regs->mrxaddr);
  158. if (r_len == 0) {
  159. writel(0, &regs->mrxraddr);
  160. } else if (r_len < 4) {
  161. writel(I2C_MRXRADDR_SET(r_len, reg), &regs->mrxraddr);
  162. } else {
  163. debug("I2C Read: addr len %d not supported\n", r_len);
  164. return -EIO;
  165. }
  166. while (bytes_remain_len) {
  167. if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
  168. con = I2C_CON_EN;
  169. bytes_xferred = 32;
  170. } else {
  171. /*
  172. * The hw can read up to 32 bytes at a time. If we need
  173. * more than one chunk, send an ACK after the last byte.
  174. */
  175. con = I2C_CON_EN | I2C_CON_LASTACK;
  176. bytes_xferred = bytes_remain_len;
  177. }
  178. words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
  179. /*
  180. * make sure we are in plain RX mode if we read a second chunk
  181. */
  182. if (snd_chunk)
  183. con |= I2C_CON_MOD(I2C_MODE_RX);
  184. else
  185. con |= I2C_CON_MOD(I2C_MODE_TRX);
  186. writel(con, &regs->con);
  187. writel(bytes_xferred, &regs->mrxcnt);
  188. writel(I2C_MBRFIEN | I2C_NAKRCVIEN, &regs->ien);
  189. start = get_timer(0);
  190. while (1) {
  191. if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
  192. writel(I2C_NAKRCVIPD, &regs->ipd);
  193. err = -EREMOTEIO;
  194. }
  195. if (readl(&regs->ipd) & I2C_MBRFIPD) {
  196. writel(I2C_MBRFIPD, &regs->ipd);
  197. break;
  198. }
  199. if (get_timer(start) > I2C_TIMEOUT_MS) {
  200. debug("I2C Read Data Timeout\n");
  201. err = -ETIMEDOUT;
  202. rk_i2c_show_regs(regs);
  203. goto i2c_exit;
  204. }
  205. udelay(1);
  206. }
  207. for (i = 0; i < words_xferred; i++) {
  208. rxdata = readl(&regs->rxdata[i]);
  209. debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
  210. for (j = 0; j < 4; j++) {
  211. if ((i * 4 + j) == bytes_xferred)
  212. break;
  213. *pbuf++ = (rxdata >> (j * 8)) & 0xff;
  214. }
  215. }
  216. bytes_remain_len -= bytes_xferred;
  217. snd_chunk = true;
  218. debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
  219. }
  220. i2c_exit:
  221. rk_i2c_disable(i2c);
  222. return err;
  223. }
  224. static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
  225. uchar *buf, uint b_len)
  226. {
  227. struct i2c_regs *regs = i2c->regs;
  228. int err;
  229. uchar *pbuf = buf;
  230. uint bytes_remain_len = b_len + r_len + 1;
  231. uint bytes_xferred = 0;
  232. uint words_xferred = 0;
  233. ulong start;
  234. uint txdata;
  235. uint i, j;
  236. debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
  237. chip, reg, r_len, b_len);
  238. err = rk_i2c_send_start_bit(i2c);
  239. if (err)
  240. return err;
  241. while (bytes_remain_len) {
  242. if (bytes_remain_len > RK_I2C_FIFO_SIZE)
  243. bytes_xferred = RK_I2C_FIFO_SIZE;
  244. else
  245. bytes_xferred = bytes_remain_len;
  246. words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
  247. for (i = 0; i < words_xferred; i++) {
  248. txdata = 0;
  249. for (j = 0; j < 4; j++) {
  250. if ((i * 4 + j) == bytes_xferred)
  251. break;
  252. if (i == 0 && j == 0 && pbuf == buf) {
  253. txdata |= (chip << 1);
  254. } else if (i == 0 && j <= r_len && pbuf == buf) {
  255. txdata |= (reg &
  256. (0xff << ((j - 1) * 8))) << 8;
  257. } else {
  258. txdata |= (*pbuf++)<<(j * 8);
  259. }
  260. }
  261. writel(txdata, &regs->txdata[i]);
  262. debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
  263. }
  264. writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), &regs->con);
  265. writel(bytes_xferred, &regs->mtxcnt);
  266. writel(I2C_MBTFIEN | I2C_NAKRCVIEN, &regs->ien);
  267. start = get_timer(0);
  268. while (1) {
  269. if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
  270. writel(I2C_NAKRCVIPD, &regs->ipd);
  271. err = -EREMOTEIO;
  272. }
  273. if (readl(&regs->ipd) & I2C_MBTFIPD) {
  274. writel(I2C_MBTFIPD, &regs->ipd);
  275. break;
  276. }
  277. if (get_timer(start) > I2C_TIMEOUT_MS) {
  278. debug("I2C Write Data Timeout\n");
  279. err = -ETIMEDOUT;
  280. rk_i2c_show_regs(regs);
  281. goto i2c_exit;
  282. }
  283. udelay(1);
  284. }
  285. bytes_remain_len -= bytes_xferred;
  286. debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
  287. }
  288. i2c_exit:
  289. rk_i2c_disable(i2c);
  290. return err;
  291. }
  292. static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  293. int nmsgs)
  294. {
  295. struct rk_i2c *i2c = dev_get_priv(bus);
  296. int ret;
  297. debug("i2c_xfer: %d messages\n", nmsgs);
  298. for (; nmsgs > 0; nmsgs--, msg++) {
  299. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  300. if (msg->flags & I2C_M_RD) {
  301. ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
  302. msg->len);
  303. } else {
  304. ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
  305. msg->len);
  306. }
  307. if (ret) {
  308. debug("i2c_write: error sending\n");
  309. return -EREMOTEIO;
  310. }
  311. }
  312. rk_i2c_send_stop_bit(i2c);
  313. rk_i2c_disable(i2c);
  314. return 0;
  315. }
  316. int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  317. {
  318. struct rk_i2c *i2c = dev_get_priv(bus);
  319. rk_i2c_set_clk(i2c, speed);
  320. return 0;
  321. }
  322. static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
  323. {
  324. struct rk_i2c *priv = dev_get_priv(bus);
  325. int ret;
  326. ret = clk_get_by_index(bus, 0, &priv->clk);
  327. if (ret < 0) {
  328. debug("%s: Could not get clock for %s: %d\n", __func__,
  329. bus->name, ret);
  330. return ret;
  331. }
  332. return 0;
  333. }
  334. static int rockchip_i2c_probe(struct udevice *bus)
  335. {
  336. struct rk_i2c *priv = dev_get_priv(bus);
  337. struct rk_i2c_soc_data *soc_data;
  338. struct udevice *pinctrl;
  339. int bus_nr;
  340. int ret;
  341. priv->regs = dev_read_addr_ptr(bus);
  342. soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus);
  343. if (soc_data->controller_type == RK_I2C_LEGACY) {
  344. ret = dev_read_alias_seq(bus, &bus_nr);
  345. if (ret < 0) {
  346. debug("%s: Could not get alias for %s: %d\n",
  347. __func__, bus->name, ret);
  348. return ret;
  349. }
  350. ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
  351. if (ret) {
  352. debug("%s: Cannot find pinctrl device\n", __func__);
  353. return ret;
  354. }
  355. /* pinctrl will switch I2C to new type */
  356. ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
  357. if (ret) {
  358. debug("%s: Failed to switch I2C to new type %s: %d\n",
  359. __func__, bus->name, ret);
  360. return ret;
  361. }
  362. }
  363. return 0;
  364. }
  365. static const struct dm_i2c_ops rockchip_i2c_ops = {
  366. .xfer = rockchip_i2c_xfer,
  367. .set_bus_speed = rockchip_i2c_set_bus_speed,
  368. };
  369. static const struct rk_i2c_soc_data rk3066_soc_data = {
  370. .controller_type = RK_I2C_LEGACY,
  371. };
  372. static const struct rk_i2c_soc_data rk3188_soc_data = {
  373. .controller_type = RK_I2C_LEGACY,
  374. };
  375. static const struct rk_i2c_soc_data rk3228_soc_data = {
  376. .controller_type = RK_I2C_NEW,
  377. };
  378. static const struct rk_i2c_soc_data rk3288_soc_data = {
  379. .controller_type = RK_I2C_NEW,
  380. };
  381. static const struct rk_i2c_soc_data rk3328_soc_data = {
  382. .controller_type = RK_I2C_NEW,
  383. };
  384. static const struct rk_i2c_soc_data rk3399_soc_data = {
  385. .controller_type = RK_I2C_NEW,
  386. };
  387. static const struct udevice_id rockchip_i2c_ids[] = {
  388. {
  389. .compatible = "rockchip,rk3066-i2c",
  390. .data = (ulong)&rk3066_soc_data,
  391. },
  392. {
  393. .compatible = "rockchip,rk3188-i2c",
  394. .data = (ulong)&rk3188_soc_data,
  395. },
  396. {
  397. .compatible = "rockchip,rk3228-i2c",
  398. .data = (ulong)&rk3228_soc_data,
  399. },
  400. {
  401. .compatible = "rockchip,rk3288-i2c",
  402. .data = (ulong)&rk3288_soc_data,
  403. },
  404. {
  405. .compatible = "rockchip,rk3328-i2c",
  406. .data = (ulong)&rk3328_soc_data,
  407. },
  408. {
  409. .compatible = "rockchip,rk3399-i2c",
  410. .data = (ulong)&rk3399_soc_data,
  411. },
  412. { }
  413. };
  414. U_BOOT_DRIVER(i2c_rockchip) = {
  415. .name = "i2c_rockchip",
  416. .id = UCLASS_I2C,
  417. .of_match = rockchip_i2c_ids,
  418. .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
  419. .probe = rockchip_i2c_probe,
  420. .priv_auto_alloc_size = sizeof(struct rk_i2c),
  421. .ops = &rockchip_i2c_ops,
  422. };