rcar_i2c.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/i2c/rcar_i2c.c
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Clock configuration based on Linux i2c-rcar.c:
  8. * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
  9. * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10. * Copyright (C) 2012-14 Renesas Solutions Corp.
  11. * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12. */
  13. #include <common.h>
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <i2c.h>
  17. #include <asm/io.h>
  18. #include <wait_bit.h>
  19. #include <dm/device_compat.h>
  20. #define RCAR_I2C_ICSCR 0x00 /* slave ctrl */
  21. #define RCAR_I2C_ICMCR 0x04 /* master ctrl */
  22. #define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
  23. #define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
  24. #define RCAR_I2C_ICMCR_FSDA BIT(5) /* override SDA pin */
  25. #define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
  26. #define RCAR_I2C_ICMCR_MIE BIT(3) /* master if enable */
  27. #define RCAR_I2C_ICMCR_TSBE BIT(2)
  28. #define RCAR_I2C_ICMCR_FSB BIT(1) /* force stop bit */
  29. #define RCAR_I2C_ICMCR_ESG BIT(0) /* enable start bit gen */
  30. #define RCAR_I2C_ICSSR 0x08 /* slave status */
  31. #define RCAR_I2C_ICMSR 0x0c /* master status */
  32. #define RCAR_I2C_ICMSR_MASK 0x7f
  33. #define RCAR_I2C_ICMSR_MNR BIT(6) /* Nack */
  34. #define RCAR_I2C_ICMSR_MAL BIT(5) /* Arbitration lost */
  35. #define RCAR_I2C_ICMSR_MST BIT(4) /* Stop */
  36. #define RCAR_I2C_ICMSR_MDE BIT(3)
  37. #define RCAR_I2C_ICMSR_MDT BIT(2)
  38. #define RCAR_I2C_ICMSR_MDR BIT(1)
  39. #define RCAR_I2C_ICMSR_MAT BIT(0)
  40. #define RCAR_I2C_ICSIER 0x10 /* slave irq enable */
  41. #define RCAR_I2C_ICMIER 0x14 /* master irq enable */
  42. #define RCAR_I2C_ICCCR 0x18 /* clock dividers */
  43. #define RCAR_I2C_ICCCR_SCGD_OFF 3
  44. #define RCAR_I2C_ICSAR 0x1c /* slave address */
  45. #define RCAR_I2C_ICMAR 0x20 /* master address */
  46. #define RCAR_I2C_ICRXD_ICTXD 0x24 /* data port */
  47. /*
  48. * First Bit Setup Cycle (Gen3).
  49. * Defines 1st bit delay between SDA and SCL.
  50. */
  51. #define RCAR_I2C_ICFBSCR 0x38
  52. #define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
  53. enum rcar_i2c_type {
  54. RCAR_I2C_TYPE_GEN2,
  55. RCAR_I2C_TYPE_GEN3,
  56. };
  57. struct rcar_i2c_priv {
  58. void __iomem *base;
  59. struct clk clk;
  60. u32 intdelay;
  61. u32 icccr;
  62. enum rcar_i2c_type type;
  63. };
  64. static int rcar_i2c_finish(struct udevice *dev)
  65. {
  66. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  67. int ret;
  68. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  69. true, 10, true);
  70. writel(0, priv->base + RCAR_I2C_ICSSR);
  71. writel(0, priv->base + RCAR_I2C_ICMSR);
  72. writel(0, priv->base + RCAR_I2C_ICMCR);
  73. return ret;
  74. }
  75. static int rcar_i2c_recover(struct udevice *dev)
  76. {
  77. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  78. u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  79. u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  80. int i;
  81. u32 mstat;
  82. /* Send 9 SCL pulses */
  83. for (i = 0; i < 9; i++) {
  84. writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  85. udelay(5);
  86. writel(mcra, priv->base + RCAR_I2C_ICMCR);
  87. udelay(5);
  88. }
  89. /* Send stop condition */
  90. udelay(5);
  91. writel(mcra, priv->base + RCAR_I2C_ICMCR);
  92. udelay(5);
  93. writel(mcr, priv->base + RCAR_I2C_ICMCR);
  94. udelay(5);
  95. writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  96. udelay(5);
  97. writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  98. udelay(5);
  99. mstat = readl(priv->base + RCAR_I2C_ICMSR);
  100. return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
  101. }
  102. static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
  103. {
  104. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  105. u32 mask = RCAR_I2C_ICMSR_MAT |
  106. (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
  107. int ret;
  108. writel(0, priv->base + RCAR_I2C_ICMIER);
  109. writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
  110. writel(0, priv->base + RCAR_I2C_ICMSR);
  111. writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
  112. /* Wait for the bus */
  113. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
  114. RCAR_I2C_ICMCR_FSDA, false, 2, true);
  115. if (ret) {
  116. if (rcar_i2c_recover(dev)) {
  117. dev_err(dev, "Bus busy, aborting\n");
  118. return ret;
  119. }
  120. }
  121. writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
  122. /* Reset */
  123. writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
  124. priv->base + RCAR_I2C_ICMCR);
  125. /* Clear Status */
  126. writel(0, priv->base + RCAR_I2C_ICMSR);
  127. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
  128. true, 100, true);
  129. if (ret)
  130. return ret;
  131. /* Check NAK */
  132. if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
  133. return -EREMOTEIO;
  134. return 0;
  135. }
  136. static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
  137. {
  138. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  139. u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
  140. int i, ret = -EREMOTEIO;
  141. for (i = 0; i < msg->len; i++) {
  142. if (msg->len - 1 == i)
  143. icmcr |= RCAR_I2C_ICMCR_FSB;
  144. writel(icmcr, priv->base + RCAR_I2C_ICMCR);
  145. writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
  146. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
  147. RCAR_I2C_ICMSR_MDR, true, 100, true);
  148. if (ret)
  149. return ret;
  150. msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
  151. }
  152. writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
  153. return rcar_i2c_finish(dev);
  154. }
  155. static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
  156. {
  157. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  158. u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
  159. int i, ret = -EREMOTEIO;
  160. for (i = 0; i < msg->len; i++) {
  161. writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
  162. writel(icmcr, priv->base + RCAR_I2C_ICMCR);
  163. writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
  164. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
  165. RCAR_I2C_ICMSR_MDE, true, 100, true);
  166. if (ret)
  167. return ret;
  168. }
  169. writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
  170. icmcr |= RCAR_I2C_ICMCR_FSB;
  171. writel(icmcr, priv->base + RCAR_I2C_ICMCR);
  172. return rcar_i2c_finish(dev);
  173. }
  174. static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  175. {
  176. int ret;
  177. for (; nmsgs > 0; nmsgs--, msg++) {
  178. ret = rcar_i2c_set_addr(dev, msg->addr, 1);
  179. if (ret)
  180. return ret;
  181. if (msg->flags & I2C_M_RD)
  182. ret = rcar_i2c_read_common(dev, msg);
  183. else
  184. ret = rcar_i2c_write_common(dev, msg);
  185. if (ret)
  186. return ret;
  187. }
  188. return 0;
  189. }
  190. static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
  191. {
  192. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  193. int ret;
  194. /* Ignore address 0, slave address */
  195. if (addr == 0)
  196. return -EINVAL;
  197. ret = rcar_i2c_set_addr(dev, addr, 1);
  198. writel(0, priv->base + RCAR_I2C_ICMSR);
  199. return ret;
  200. }
  201. static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
  202. {
  203. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  204. u32 scgd, cdf, round, ick, sum, scl;
  205. unsigned long rate;
  206. /*
  207. * calculate SCL clock
  208. * see
  209. * ICCCR
  210. *
  211. * ick = clkp / (1 + CDF)
  212. * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
  213. *
  214. * ick : I2C internal clock < 20 MHz
  215. * ticf : I2C SCL falling time
  216. * tr : I2C SCL rising time
  217. * intd : LSI internal delay
  218. * clkp : peripheral_clk
  219. * F[] : integer up-valuation
  220. */
  221. rate = clk_get_rate(&priv->clk);
  222. cdf = rate / 20000000;
  223. if (cdf >= 8) {
  224. dev_err(dev, "Input clock %lu too high\n", rate);
  225. return -EIO;
  226. }
  227. ick = rate / (cdf + 1);
  228. /*
  229. * it is impossible to calculate large scale
  230. * number on u32. separate it
  231. *
  232. * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
  233. * = F[sum * ick / 1000000000]
  234. * = F[(ick / 1000000) * sum / 1000]
  235. */
  236. sum = 35 + 200 + priv->intdelay;
  237. round = (ick + 500000) / 1000000 * sum;
  238. round = (round + 500) / 1000;
  239. /*
  240. * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
  241. *
  242. * Calculation result (= SCL) should be less than
  243. * bus_speed for hardware safety
  244. *
  245. * We could use something along the lines of
  246. * div = ick / (bus_speed + 1) + 1;
  247. * scgd = (div - 20 - round + 7) / 8;
  248. * scl = ick / (20 + (scgd * 8) + round);
  249. * (not fully verified) but that would get pretty involved
  250. */
  251. for (scgd = 0; scgd < 0x40; scgd++) {
  252. scl = ick / (20 + (scgd * 8) + round);
  253. if (scl <= bus_freq_hz)
  254. goto scgd_find;
  255. }
  256. dev_err(dev, "it is impossible to calculate best SCL\n");
  257. return -EIO;
  258. scgd_find:
  259. dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
  260. scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
  261. priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
  262. writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
  263. if (priv->type == RCAR_I2C_TYPE_GEN3) {
  264. /* Set SCL/SDA delay */
  265. writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
  266. }
  267. return 0;
  268. }
  269. static int rcar_i2c_probe(struct udevice *dev)
  270. {
  271. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  272. int ret;
  273. priv->base = dev_read_addr_ptr(dev);
  274. priv->intdelay = dev_read_u32_default(dev,
  275. "i2c-scl-internal-delay-ns", 5);
  276. priv->type = dev_get_driver_data(dev);
  277. ret = clk_get_by_index(dev, 0, &priv->clk);
  278. if (ret)
  279. return ret;
  280. ret = clk_enable(&priv->clk);
  281. if (ret)
  282. return ret;
  283. /* reset slave mode */
  284. writel(0, priv->base + RCAR_I2C_ICSIER);
  285. writel(0, priv->base + RCAR_I2C_ICSAR);
  286. writel(0, priv->base + RCAR_I2C_ICSCR);
  287. writel(0, priv->base + RCAR_I2C_ICSSR);
  288. /* reset master mode */
  289. writel(0, priv->base + RCAR_I2C_ICMIER);
  290. writel(0, priv->base + RCAR_I2C_ICMCR);
  291. writel(0, priv->base + RCAR_I2C_ICMSR);
  292. writel(0, priv->base + RCAR_I2C_ICMAR);
  293. ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
  294. if (ret)
  295. clk_disable(&priv->clk);
  296. return ret;
  297. }
  298. static const struct dm_i2c_ops rcar_i2c_ops = {
  299. .xfer = rcar_i2c_xfer,
  300. .probe_chip = rcar_i2c_probe_chip,
  301. .set_bus_speed = rcar_i2c_set_speed,
  302. };
  303. static const struct udevice_id rcar_i2c_ids[] = {
  304. { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
  305. { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
  306. { }
  307. };
  308. U_BOOT_DRIVER(i2c_rcar) = {
  309. .name = "i2c_rcar",
  310. .id = UCLASS_I2C,
  311. .of_match = rcar_i2c_ids,
  312. .probe = rcar_i2c_probe,
  313. .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
  314. .ops = &rcar_i2c_ops,
  315. };