mv_i2c.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
  5. *
  6. * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * (C) Copyright 2003 Pengutronix e.K.
  10. * Robert Schwebel <r.schwebel@pengutronix.de>
  11. *
  12. * (C) Copyright 2011 Marvell Inc.
  13. * Lei Wen <leiwen@marvell.com>
  14. *
  15. * Back ported to the 8xx platform (from the 8260 platform) by
  16. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <i2c.h>
  21. #include <asm/io.h>
  22. #include "mv_i2c.h"
  23. /* All transfers are described by this data structure */
  24. struct mv_i2c_msg {
  25. u8 condition;
  26. u8 acknack;
  27. u8 direction;
  28. u8 data;
  29. };
  30. #ifdef CONFIG_ARMADA_3700
  31. /* Armada 3700 has no padding between the registers */
  32. struct mv_i2c {
  33. u32 ibmr;
  34. u32 idbr;
  35. u32 icr;
  36. u32 isr;
  37. u32 isar;
  38. };
  39. #else
  40. struct mv_i2c {
  41. u32 ibmr;
  42. u32 pad0;
  43. u32 idbr;
  44. u32 pad1;
  45. u32 icr;
  46. u32 pad2;
  47. u32 isr;
  48. u32 pad3;
  49. u32 isar;
  50. };
  51. #endif
  52. /*
  53. * Dummy implementation that can be overwritten by a board
  54. * specific function
  55. */
  56. __weak void i2c_clk_enable(void)
  57. {
  58. }
  59. /*
  60. * i2c_reset: - reset the host controller
  61. *
  62. */
  63. static void i2c_reset(struct mv_i2c *base)
  64. {
  65. u32 icr_mode;
  66. /* Save bus mode (standard or fast speed) for later use */
  67. icr_mode = readl(&base->icr) & ICR_MODE_MASK;
  68. writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
  69. writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
  70. udelay(100);
  71. writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
  72. i2c_clk_enable();
  73. writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
  74. /* set control reg values */
  75. writel(I2C_ICR_INIT | icr_mode, &base->icr);
  76. writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
  77. writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
  78. udelay(100);
  79. }
  80. /*
  81. * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
  82. * are set and cleared
  83. *
  84. * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
  85. */
  86. static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
  87. unsigned long cleared_mask)
  88. {
  89. int timeout = 1000, isr;
  90. do {
  91. isr = readl(&base->isr);
  92. udelay(10);
  93. if (timeout-- < 0)
  94. return 0;
  95. } while (((isr & set_mask) != set_mask)
  96. || ((isr & cleared_mask) != 0));
  97. return 1;
  98. }
  99. /*
  100. * i2c_transfer: - Transfer one byte over the i2c bus
  101. *
  102. * This function can tranfer a byte over the i2c bus in both directions.
  103. * It is used by the public API functions.
  104. *
  105. * @return: 0: transfer successful
  106. * -1: message is empty
  107. * -2: transmit timeout
  108. * -3: ACK missing
  109. * -4: receive timeout
  110. * -5: illegal parameters
  111. * -6: bus is busy and couldn't be aquired
  112. */
  113. static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
  114. {
  115. int ret;
  116. if (!msg)
  117. goto transfer_error_msg_empty;
  118. switch (msg->direction) {
  119. case I2C_WRITE:
  120. /* check if bus is not busy */
  121. if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
  122. goto transfer_error_bus_busy;
  123. /* start transmission */
  124. writel(readl(&base->icr) & ~ICR_START, &base->icr);
  125. writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
  126. writel(msg->data, &base->idbr);
  127. if (msg->condition == I2C_COND_START)
  128. writel(readl(&base->icr) | ICR_START, &base->icr);
  129. if (msg->condition == I2C_COND_STOP)
  130. writel(readl(&base->icr) | ICR_STOP, &base->icr);
  131. if (msg->acknack == I2C_ACKNAK_SENDNAK)
  132. writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
  133. if (msg->acknack == I2C_ACKNAK_SENDACK)
  134. writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
  135. writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
  136. writel(readl(&base->icr) | ICR_TB, &base->icr);
  137. /* transmit register empty? */
  138. if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
  139. goto transfer_error_transmit_timeout;
  140. /* clear 'transmit empty' state */
  141. writel(readl(&base->isr) | ISR_ITE, &base->isr);
  142. /* wait for ACK from slave */
  143. if (msg->acknack == I2C_ACKNAK_WAITACK)
  144. if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
  145. goto transfer_error_ack_missing;
  146. break;
  147. case I2C_READ:
  148. /* check if bus is not busy */
  149. if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
  150. goto transfer_error_bus_busy;
  151. /* start receive */
  152. writel(readl(&base->icr) & ~ICR_START, &base->icr);
  153. writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
  154. if (msg->condition == I2C_COND_START)
  155. writel(readl(&base->icr) | ICR_START, &base->icr);
  156. if (msg->condition == I2C_COND_STOP)
  157. writel(readl(&base->icr) | ICR_STOP, &base->icr);
  158. if (msg->acknack == I2C_ACKNAK_SENDNAK)
  159. writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
  160. if (msg->acknack == I2C_ACKNAK_SENDACK)
  161. writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
  162. writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
  163. writel(readl(&base->icr) | ICR_TB, &base->icr);
  164. /* receive register full? */
  165. if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
  166. goto transfer_error_receive_timeout;
  167. msg->data = readl(&base->idbr);
  168. /* clear 'receive empty' state */
  169. writel(readl(&base->isr) | ISR_IRF, &base->isr);
  170. break;
  171. default:
  172. goto transfer_error_illegal_param;
  173. }
  174. return 0;
  175. transfer_error_msg_empty:
  176. debug("i2c_transfer: error: 'msg' is empty\n");
  177. ret = -1;
  178. goto i2c_transfer_finish;
  179. transfer_error_transmit_timeout:
  180. debug("i2c_transfer: error: transmit timeout\n");
  181. ret = -2;
  182. goto i2c_transfer_finish;
  183. transfer_error_ack_missing:
  184. debug("i2c_transfer: error: ACK missing\n");
  185. ret = -3;
  186. goto i2c_transfer_finish;
  187. transfer_error_receive_timeout:
  188. debug("i2c_transfer: error: receive timeout\n");
  189. ret = -4;
  190. goto i2c_transfer_finish;
  191. transfer_error_illegal_param:
  192. debug("i2c_transfer: error: illegal parameters\n");
  193. ret = -5;
  194. goto i2c_transfer_finish;
  195. transfer_error_bus_busy:
  196. debug("i2c_transfer: error: bus is busy\n");
  197. ret = -6;
  198. goto i2c_transfer_finish;
  199. i2c_transfer_finish:
  200. debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
  201. i2c_reset(base);
  202. return ret;
  203. }
  204. static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
  205. uchar *buffer, int len)
  206. {
  207. struct mv_i2c_msg msg;
  208. debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
  209. "len=0x%02x)\n", chip, *addr, alen, len);
  210. if (len == 0) {
  211. printf("reading zero byte is invalid\n");
  212. return -EINVAL;
  213. }
  214. i2c_reset(base);
  215. /* dummy chip address write */
  216. debug("i2c_read: dummy chip address write\n");
  217. msg.condition = I2C_COND_START;
  218. msg.acknack = I2C_ACKNAK_WAITACK;
  219. msg.direction = I2C_WRITE;
  220. msg.data = (chip << 1);
  221. msg.data &= 0xFE;
  222. if (i2c_transfer(base, &msg))
  223. return -1;
  224. /*
  225. * send memory address bytes;
  226. * alen defines how much bytes we have to send.
  227. */
  228. while (--alen >= 0) {
  229. debug("i2c_read: send address byte %02x (alen=%d)\n",
  230. *addr, alen);
  231. msg.condition = I2C_COND_NORMAL;
  232. msg.acknack = I2C_ACKNAK_WAITACK;
  233. msg.direction = I2C_WRITE;
  234. msg.data = addr[alen];
  235. if (i2c_transfer(base, &msg))
  236. return -1;
  237. }
  238. /* start read sequence */
  239. debug("i2c_read: start read sequence\n");
  240. msg.condition = I2C_COND_START;
  241. msg.acknack = I2C_ACKNAK_WAITACK;
  242. msg.direction = I2C_WRITE;
  243. msg.data = (chip << 1);
  244. msg.data |= 0x01;
  245. if (i2c_transfer(base, &msg))
  246. return -1;
  247. /* read bytes; send NACK at last byte */
  248. while (len--) {
  249. if (len == 0) {
  250. msg.condition = I2C_COND_STOP;
  251. msg.acknack = I2C_ACKNAK_SENDNAK;
  252. } else {
  253. msg.condition = I2C_COND_NORMAL;
  254. msg.acknack = I2C_ACKNAK_SENDACK;
  255. }
  256. msg.direction = I2C_READ;
  257. msg.data = 0x00;
  258. if (i2c_transfer(base, &msg))
  259. return -1;
  260. *buffer = msg.data;
  261. debug("i2c_read: reading byte (%p)=0x%02x\n",
  262. buffer, *buffer);
  263. buffer++;
  264. }
  265. i2c_reset(base);
  266. return 0;
  267. }
  268. static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
  269. uchar *buffer, int len)
  270. {
  271. struct mv_i2c_msg msg;
  272. debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
  273. "len=0x%02x)\n", chip, *addr, alen, len);
  274. i2c_reset(base);
  275. /* chip address write */
  276. debug("i2c_write: chip address write\n");
  277. msg.condition = I2C_COND_START;
  278. msg.acknack = I2C_ACKNAK_WAITACK;
  279. msg.direction = I2C_WRITE;
  280. msg.data = (chip << 1);
  281. msg.data &= 0xFE;
  282. if (i2c_transfer(base, &msg))
  283. return -1;
  284. /*
  285. * send memory address bytes;
  286. * alen defines how much bytes we have to send.
  287. */
  288. while (--alen >= 0) {
  289. debug("i2c_read: send address byte %02x (alen=%d)\n",
  290. *addr, alen);
  291. msg.condition = I2C_COND_NORMAL;
  292. msg.acknack = I2C_ACKNAK_WAITACK;
  293. msg.direction = I2C_WRITE;
  294. msg.data = addr[alen];
  295. if (i2c_transfer(base, &msg))
  296. return -1;
  297. }
  298. /* write bytes; send NACK at last byte */
  299. while (len--) {
  300. debug("i2c_write: writing byte (%p)=0x%02x\n",
  301. buffer, *buffer);
  302. if (len == 0)
  303. msg.condition = I2C_COND_STOP;
  304. else
  305. msg.condition = I2C_COND_NORMAL;
  306. msg.acknack = I2C_ACKNAK_WAITACK;
  307. msg.direction = I2C_WRITE;
  308. msg.data = *(buffer++);
  309. if (i2c_transfer(base, &msg))
  310. return -1;
  311. }
  312. i2c_reset(base);
  313. return 0;
  314. }
  315. #ifndef CONFIG_DM_I2C
  316. static struct mv_i2c *base_glob;
  317. static void i2c_board_init(struct mv_i2c *base)
  318. {
  319. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  320. u32 icr;
  321. /*
  322. * call board specific i2c bus reset routine before accessing the
  323. * environment, which might be in a chip on that bus. For details
  324. * about this problem see doc/I2C_Edge_Conditions.
  325. *
  326. * disable I2C controller first, otherwhise it thinks we want to
  327. * talk to the slave port...
  328. */
  329. icr = readl(&base->icr);
  330. writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
  331. i2c_init_board();
  332. writel(icr, &base->icr);
  333. #endif
  334. }
  335. #ifdef CONFIG_I2C_MULTI_BUS
  336. static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
  337. static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
  338. static unsigned int current_bus;
  339. int i2c_set_bus_num(unsigned int bus)
  340. {
  341. if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
  342. printf("Bad bus: %d\n", bus);
  343. return -1;
  344. }
  345. base_glob = (struct mv_i2c *)i2c_regs[bus];
  346. current_bus = bus;
  347. if (!bus_initialized[current_bus]) {
  348. i2c_board_init(base_glob);
  349. bus_initialized[current_bus] = 1;
  350. }
  351. return 0;
  352. }
  353. unsigned int i2c_get_bus_num(void)
  354. {
  355. return current_bus;
  356. }
  357. #endif
  358. /* API Functions */
  359. void i2c_init(int speed, int slaveaddr)
  360. {
  361. u32 val;
  362. #ifdef CONFIG_I2C_MULTI_BUS
  363. current_bus = 0;
  364. base_glob = (struct mv_i2c *)i2c_regs[current_bus];
  365. #else
  366. base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
  367. #endif
  368. if (speed > I2C_SPEED_STANDARD_RATE)
  369. val = ICR_FM;
  370. else
  371. val = ICR_SM;
  372. clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
  373. i2c_board_init(base_glob);
  374. }
  375. static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
  376. {
  377. struct mv_i2c_msg msg;
  378. i2c_reset(base);
  379. msg.condition = I2C_COND_START;
  380. msg.acknack = I2C_ACKNAK_WAITACK;
  381. msg.direction = I2C_WRITE;
  382. msg.data = (chip << 1) + 1;
  383. if (i2c_transfer(base, &msg))
  384. return -1;
  385. msg.condition = I2C_COND_STOP;
  386. msg.acknack = I2C_ACKNAK_SENDNAK;
  387. msg.direction = I2C_READ;
  388. msg.data = 0x00;
  389. if (i2c_transfer(base, &msg))
  390. return -1;
  391. return 0;
  392. }
  393. /*
  394. * i2c_probe: - Test if a chip answers for a given i2c address
  395. *
  396. * @chip: address of the chip which is searched for
  397. * @return: 0 if a chip was found, -1 otherwhise
  398. */
  399. int i2c_probe(uchar chip)
  400. {
  401. return __i2c_probe_chip(base_glob, chip);
  402. }
  403. /*
  404. * i2c_read: - Read multiple bytes from an i2c device
  405. *
  406. * The higher level routines take into account that this function is only
  407. * called with len < page length of the device (see configuration file)
  408. *
  409. * @chip: address of the chip which is to be read
  410. * @addr: i2c data address within the chip
  411. * @alen: length of the i2c data address (1..2 bytes)
  412. * @buffer: where to write the data
  413. * @len: how much byte do we want to read
  414. * @return: 0 in case of success
  415. */
  416. int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
  417. {
  418. u8 addr_bytes[4];
  419. addr_bytes[0] = (addr >> 0) & 0xFF;
  420. addr_bytes[1] = (addr >> 8) & 0xFF;
  421. addr_bytes[2] = (addr >> 16) & 0xFF;
  422. addr_bytes[3] = (addr >> 24) & 0xFF;
  423. return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
  424. }
  425. /*
  426. * i2c_write: - Write multiple bytes to an i2c device
  427. *
  428. * The higher level routines take into account that this function is only
  429. * called with len < page length of the device (see configuration file)
  430. *
  431. * @chip: address of the chip which is to be written
  432. * @addr: i2c data address within the chip
  433. * @alen: length of the i2c data address (1..2 bytes)
  434. * @buffer: where to find the data to be written
  435. * @len: how much byte do we want to read
  436. * @return: 0 in case of success
  437. */
  438. int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
  439. {
  440. u8 addr_bytes[4];
  441. addr_bytes[0] = (addr >> 0) & 0xFF;
  442. addr_bytes[1] = (addr >> 8) & 0xFF;
  443. addr_bytes[2] = (addr >> 16) & 0xFF;
  444. addr_bytes[3] = (addr >> 24) & 0xFF;
  445. return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
  446. }
  447. #else /* CONFIG_DM_I2C */
  448. struct mv_i2c_priv {
  449. struct mv_i2c *base;
  450. };
  451. static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  452. {
  453. struct mv_i2c_priv *i2c = dev_get_priv(bus);
  454. struct i2c_msg *dmsg, *omsg, dummy;
  455. memset(&dummy, 0, sizeof(struct i2c_msg));
  456. /*
  457. * We expect either two messages (one with an offset and one with the
  458. * actual data) or one message (just data or offset/data combined)
  459. */
  460. if (nmsgs > 2 || nmsgs == 0) {
  461. debug("%s: Only one or two messages are supported.", __func__);
  462. return -1;
  463. }
  464. omsg = nmsgs == 1 ? &dummy : msg;
  465. dmsg = nmsgs == 1 ? msg : msg + 1;
  466. if (dmsg->flags & I2C_M_RD)
  467. return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
  468. omsg->len, dmsg->buf, dmsg->len);
  469. else
  470. return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
  471. omsg->len, dmsg->buf, dmsg->len);
  472. }
  473. static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  474. {
  475. struct mv_i2c_priv *priv = dev_get_priv(bus);
  476. u32 val;
  477. if (speed > I2C_SPEED_STANDARD_RATE)
  478. val = ICR_FM;
  479. else
  480. val = ICR_SM;
  481. clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
  482. return 0;
  483. }
  484. static int mv_i2c_probe(struct udevice *bus)
  485. {
  486. struct mv_i2c_priv *priv = dev_get_priv(bus);
  487. priv->base = (void *)devfdt_get_addr_ptr(bus);
  488. return 0;
  489. }
  490. static const struct dm_i2c_ops mv_i2c_ops = {
  491. .xfer = mv_i2c_xfer,
  492. .set_bus_speed = mv_i2c_set_bus_speed,
  493. };
  494. static const struct udevice_id mv_i2c_ids[] = {
  495. { .compatible = "marvell,armada-3700-i2c" },
  496. { }
  497. };
  498. U_BOOT_DRIVER(i2c_mv) = {
  499. .name = "i2c_mv",
  500. .id = UCLASS_I2C,
  501. .of_match = mv_i2c_ids,
  502. .probe = mv_i2c_probe,
  503. .priv_auto_alloc_size = sizeof(struct mv_i2c_priv),
  504. .ops = &mv_i2c_ops,
  505. };
  506. #endif /* CONFIG_DM_I2C */