intel_i2c.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. *
  6. * SMBus block read/write support added by Stefan Roese:
  7. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <i2c.h>
  12. #include <pci.h>
  13. #include <asm/io.h>
  14. /* PCI Configuration Space (D31:F3): SMBus */
  15. #define SMB_BASE 0x20
  16. #define HOSTC 0x40
  17. #define HST_EN (1 << 0)
  18. #define SMB_RCV_SLVA 0x09
  19. /* SMBus I/O bits. */
  20. #define SMBHSTSTAT 0x0
  21. #define SMBHSTCTL 0x2
  22. #define SMBHSTCMD 0x3
  23. #define SMBXMITADD 0x4
  24. #define SMBHSTDAT0 0x5
  25. #define SMBHSTDAT1 0x6
  26. #define SMBBLKDAT 0x7
  27. #define SMBTRNSADD 0x9
  28. #define SMBSLVDATA 0xa
  29. #define SMBAUXCTL 0xd
  30. #define SMLINK_PIN_CTL 0xe
  31. #define SMBUS_PIN_CTL 0xf
  32. /* I801 Hosts Status register bits */
  33. #define SMBHSTSTS_BYTE_DONE 0x80
  34. #define SMBHSTSTS_INUSE_STS 0x40
  35. #define SMBHSTSTS_SMBALERT_STS 0x20
  36. #define SMBHSTSTS_FAILED 0x10
  37. #define SMBHSTSTS_BUS_ERR 0x08
  38. #define SMBHSTSTS_DEV_ERR 0x04
  39. #define SMBHSTSTS_INTR 0x02
  40. #define SMBHSTSTS_HOST_BUSY 0x01
  41. /* I801 Host Control register bits */
  42. #define SMBHSTCNT_INTREN 0x01
  43. #define SMBHSTCNT_KILL 0x02
  44. #define SMBHSTCNT_LAST_BYTE 0x20
  45. #define SMBHSTCNT_START 0x40
  46. #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
  47. /* Auxiliary control register bits, ICH4+ only */
  48. #define SMBAUXCTL_CRC 1
  49. #define SMBAUXCTL_E32B 2
  50. #define SMBUS_TIMEOUT 100 /* 100 ms */
  51. struct intel_i2c {
  52. u32 base;
  53. int running;
  54. };
  55. static int smbus_wait_until_ready(u32 base)
  56. {
  57. unsigned long ts;
  58. u8 byte;
  59. ts = get_timer(0);
  60. do {
  61. byte = inb(base + SMBHSTSTAT);
  62. if (!(byte & 1))
  63. return 0;
  64. } while (get_timer(ts) < SMBUS_TIMEOUT);
  65. return -ETIMEDOUT;
  66. }
  67. static int smbus_wait_until_done(u32 base)
  68. {
  69. unsigned long ts;
  70. u8 byte;
  71. ts = get_timer(0);
  72. do {
  73. byte = inb(base + SMBHSTSTAT);
  74. if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0))
  75. return 0;
  76. } while (get_timer(ts) < SMBUS_TIMEOUT);
  77. return -ETIMEDOUT;
  78. }
  79. static int smbus_block_read(u32 base, u8 dev, u8 *buffer,
  80. int offset, int len)
  81. {
  82. u8 buf_temp[32];
  83. int count;
  84. int i;
  85. debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
  86. __func__, __LINE__, dev, offset, len);
  87. if (smbus_wait_until_ready(base) < 0)
  88. return -ETIMEDOUT;
  89. /* Setup transaction */
  90. /* Reset the data buffer index */
  91. inb(base + SMBHSTCTL);
  92. /* Set the device I'm talking too */
  93. outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD);
  94. /* Set the command/address... */
  95. outb(offset & 0xff, base + SMBHSTCMD);
  96. /* Set up for a block read */
  97. outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
  98. (base + SMBHSTCTL));
  99. /* Clear any lingering errors, so the transaction will run */
  100. outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
  101. /* Start the command */
  102. outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
  103. /* Poll for transaction completion */
  104. if (smbus_wait_until_done(base) < 0) {
  105. printf("SMBUS read transaction timeout (dev=0x%x)\n", dev);
  106. return -ETIMEDOUT;
  107. }
  108. count = inb(base + SMBHSTDAT0);
  109. debug("%s (%d): count=%d (len=%d)\n", __func__, __LINE__, count, len);
  110. if (count == 0) {
  111. debug("ERROR: len=0 on read\n");
  112. return -EIO;
  113. }
  114. if (count < len) {
  115. debug("ERROR: too few bytes read\n");
  116. return -EIO;
  117. }
  118. if (count > 32) {
  119. debug("ERROR: count=%d too high\n", count);
  120. return -EIO;
  121. }
  122. /* Read all available bytes from buffer */
  123. for (i = 0; i < count; i++)
  124. buf_temp[i] = inb(base + SMBBLKDAT);
  125. memcpy(buffer, buf_temp, len);
  126. /* Return results of transaction */
  127. if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
  128. return -EIO;
  129. return 0;
  130. }
  131. static int smbus_block_write(u32 base, u8 dev, u8 *buffer,
  132. int offset, int len)
  133. {
  134. int i;
  135. debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
  136. __func__, __LINE__, dev, offset, len);
  137. if (smbus_wait_until_ready(base) < 0)
  138. return -ETIMEDOUT;
  139. /* Setup transaction */
  140. /* Set the device I'm talking too */
  141. outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD);
  142. /* Set the command/address... */
  143. outb(offset, base + SMBHSTCMD);
  144. /* Set up for a block write */
  145. outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
  146. (base + SMBHSTCTL));
  147. /* Clear any lingering errors, so the transaction will run */
  148. outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
  149. /* Write count in DAT0 register */
  150. outb(len, base + SMBHSTDAT0);
  151. /* Write data bytes... */
  152. for (i = 0; i < len; i++)
  153. outb(*buffer++, base + SMBBLKDAT);
  154. /* Start the command */
  155. outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
  156. /* Poll for transaction completion */
  157. if (smbus_wait_until_done(base) < 0) {
  158. printf("SMBUS write transaction timeout (dev=0x%x)\n", dev);
  159. return -ETIMEDOUT;
  160. }
  161. /* Return results of transaction */
  162. if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
  163. return -EIO;
  164. return 0;
  165. }
  166. static int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  167. {
  168. struct intel_i2c *i2c = dev_get_priv(bus);
  169. struct i2c_msg *dmsg, *omsg, dummy;
  170. debug("i2c_xfer: %d messages\n", nmsgs);
  171. memset(&dummy, 0, sizeof(struct i2c_msg));
  172. /*
  173. * We expect either two messages (one with an offset and one with the
  174. * actucal data) or one message (just data)
  175. */
  176. if (nmsgs > 2 || nmsgs == 0) {
  177. debug("%s: Only one or two messages are supported", __func__);
  178. return -EIO;
  179. }
  180. omsg = nmsgs == 1 ? &dummy : msg;
  181. dmsg = nmsgs == 1 ? msg : msg + 1;
  182. if (dmsg->flags & I2C_M_RD)
  183. return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0],
  184. omsg->buf[0], dmsg->len);
  185. else
  186. return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1],
  187. dmsg->buf[0], dmsg->len - 1);
  188. }
  189. static int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  190. uint chip_flags)
  191. {
  192. struct intel_i2c *i2c = dev_get_priv(bus);
  193. u8 buf[4];
  194. return smbus_block_read(i2c->base, chip_addr, buf, 0, 1);
  195. }
  196. static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  197. {
  198. return 0;
  199. }
  200. static int intel_i2c_probe(struct udevice *dev)
  201. {
  202. struct intel_i2c *priv = dev_get_priv(dev);
  203. ulong base;
  204. /* Save base address from PCI BAR */
  205. priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
  206. PCI_REGION_IO);
  207. base = priv->base;
  208. /* Set SMBus enable. */
  209. dm_pci_write_config8(dev, HOSTC, HST_EN);
  210. /* Disable interrupts */
  211. outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL);
  212. /* Set 32-byte data buffer mode */
  213. outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL);
  214. return 0;
  215. }
  216. static int intel_i2c_bind(struct udevice *dev)
  217. {
  218. static int num_cards __attribute__ ((section(".data")));
  219. char name[20];
  220. /* Create a unique device name for PCI type devices */
  221. if (device_is_on_pci_bus(dev)) {
  222. /*
  223. * ToDo:
  224. * Setting req_seq in the driver is probably not recommended.
  225. * But without a DT alias the number is not configured. And
  226. * using this driver is impossible for PCIe I2C devices.
  227. * This can be removed, once a better (correct) way for this
  228. * is found and implemented.
  229. */
  230. dev->req_seq = num_cards;
  231. sprintf(name, "intel_i2c#%u", num_cards++);
  232. device_set_name(dev, name);
  233. }
  234. return 0;
  235. }
  236. static const struct dm_i2c_ops intel_i2c_ops = {
  237. .xfer = intel_i2c_xfer,
  238. .probe_chip = intel_i2c_probe_chip,
  239. .set_bus_speed = intel_i2c_set_bus_speed,
  240. };
  241. static const struct udevice_id intel_i2c_ids[] = {
  242. { .compatible = "intel,ich-i2c" },
  243. { }
  244. };
  245. U_BOOT_DRIVER(intel_i2c) = {
  246. .name = "i2c_intel",
  247. .id = UCLASS_I2C,
  248. .of_match = intel_i2c_ids,
  249. .ops = &intel_i2c_ops,
  250. .priv_auto_alloc_size = sizeof(struct intel_i2c),
  251. .bind = intel_i2c_bind,
  252. .probe = intel_i2c_probe,
  253. };
  254. static struct pci_device_id intel_smbus_pci_supported[] = {
  255. /* Intel BayTrail SMBus on the PCI bus */
  256. { PCI_VDEVICE(INTEL, 0x0f12) },
  257. /* Intel IvyBridge (Panther Point PCH) SMBus on the PCI bus */
  258. { PCI_VDEVICE(INTEL, 0x1e22) },
  259. {},
  260. };
  261. U_BOOT_PCI_DEVICE(intel_i2c, intel_smbus_pci_supported);