imx_lpi2c.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductors, Inc.
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <imx_lpi2c.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <dm.h>
  13. #include <fdtdec.h>
  14. #include <i2c.h>
  15. #include <dm/device_compat.h>
  16. #define LPI2C_FIFO_SIZE 4
  17. #define LPI2C_NACK_TOUT_MS 1
  18. #define LPI2C_TIMEOUT_MS 100
  19. static int bus_i2c_init(struct udevice *bus, int speed);
  20. /* Weak linked function for overridden by some SoC power function */
  21. int __weak init_i2c_power(unsigned i2c_num)
  22. {
  23. return 0;
  24. }
  25. static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
  26. {
  27. lpi2c_status_t result = LPI2C_SUCESS;
  28. u32 status;
  29. status = readl(&regs->msr);
  30. if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
  31. result = LPI2C_BUSY;
  32. return result;
  33. }
  34. static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
  35. {
  36. lpi2c_status_t result = LPI2C_SUCESS;
  37. u32 val, status;
  38. status = readl(&regs->msr);
  39. /* errors to check for */
  40. status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
  41. LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
  42. if (status) {
  43. if (status & LPI2C_MSR_PLTF_MASK)
  44. result = LPI2C_PIN_LOW_TIMEOUT_ERR;
  45. else if (status & LPI2C_MSR_ALF_MASK)
  46. result = LPI2C_ARB_LOST_ERR;
  47. else if (status & LPI2C_MSR_NDF_MASK)
  48. result = LPI2C_NAK_ERR;
  49. else if (status & LPI2C_MSR_FEF_MASK)
  50. result = LPI2C_FIFO_ERR;
  51. /* clear status flags */
  52. writel(0x7f00, &regs->msr);
  53. /* reset fifos */
  54. val = readl(&regs->mcr);
  55. val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  56. writel(val, &regs->mcr);
  57. }
  58. return result;
  59. }
  60. static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
  61. {
  62. lpi2c_status_t result = LPI2C_SUCESS;
  63. u32 txcount = 0;
  64. ulong start_time = get_timer(0);
  65. do {
  66. txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
  67. txcount = LPI2C_FIFO_SIZE - txcount;
  68. result = imx_lpci2c_check_clear_error(regs);
  69. if (result) {
  70. debug("i2c: wait for tx ready: result 0x%x\n", result);
  71. return result;
  72. }
  73. if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  74. debug("i2c: wait for tx ready: timeout\n");
  75. return -1;
  76. }
  77. } while (!txcount);
  78. return result;
  79. }
  80. static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
  81. {
  82. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  83. lpi2c_status_t result = LPI2C_SUCESS;
  84. /* empty tx */
  85. if (!len)
  86. return result;
  87. while (len--) {
  88. result = bus_i2c_wait_for_tx_ready(regs);
  89. if (result) {
  90. debug("i2c: send wait for tx ready: %d\n", result);
  91. return result;
  92. }
  93. writel(*txbuf++, &regs->mtdr);
  94. }
  95. return result;
  96. }
  97. static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
  98. {
  99. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  100. lpi2c_status_t result = LPI2C_SUCESS;
  101. u32 val;
  102. ulong start_time = get_timer(0);
  103. /* empty read */
  104. if (!len)
  105. return result;
  106. result = bus_i2c_wait_for_tx_ready(regs);
  107. if (result) {
  108. debug("i2c: receive wait fot tx ready: %d\n", result);
  109. return result;
  110. }
  111. /* clear all status flags */
  112. writel(0x7f00, &regs->msr);
  113. /* send receive command */
  114. val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
  115. writel(val, &regs->mtdr);
  116. while (len--) {
  117. do {
  118. result = imx_lpci2c_check_clear_error(regs);
  119. if (result) {
  120. debug("i2c: receive check clear error: %d\n",
  121. result);
  122. return result;
  123. }
  124. if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  125. debug("i2c: receive mrdr: timeout\n");
  126. return -1;
  127. }
  128. val = readl(&regs->mrdr);
  129. } while (val & LPI2C_MRDR_RXEMPTY_MASK);
  130. *rxbuf++ = LPI2C_MRDR_DATA(val);
  131. }
  132. return result;
  133. }
  134. static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
  135. {
  136. lpi2c_status_t result;
  137. struct imx_lpi2c_reg *regs =
  138. (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  139. u32 val;
  140. result = imx_lpci2c_check_busy_bus(regs);
  141. if (result) {
  142. debug("i2c: start check busy bus: 0x%x\n", result);
  143. /* Try to init the lpi2c then check the bus busy again */
  144. bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  145. result = imx_lpci2c_check_busy_bus(regs);
  146. if (result) {
  147. printf("i2c: Error check busy bus: 0x%x\n", result);
  148. return result;
  149. }
  150. }
  151. /* clear all status flags */
  152. writel(0x7f00, &regs->msr);
  153. /* turn off auto-stop condition */
  154. val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
  155. writel(val, &regs->mcfgr1);
  156. /* wait tx fifo ready */
  157. result = bus_i2c_wait_for_tx_ready(regs);
  158. if (result) {
  159. debug("i2c: start wait for tx ready: 0x%x\n", result);
  160. return result;
  161. }
  162. /* issue start command */
  163. val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
  164. writel(val, &regs->mtdr);
  165. return result;
  166. }
  167. static int bus_i2c_stop(struct udevice *bus)
  168. {
  169. lpi2c_status_t result;
  170. struct imx_lpi2c_reg *regs =
  171. (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  172. u32 status;
  173. ulong start_time;
  174. result = bus_i2c_wait_for_tx_ready(regs);
  175. if (result) {
  176. debug("i2c: stop wait for tx ready: 0x%x\n", result);
  177. return result;
  178. }
  179. /* send stop command */
  180. writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
  181. start_time = get_timer(0);
  182. while (1) {
  183. status = readl(&regs->msr);
  184. result = imx_lpci2c_check_clear_error(regs);
  185. /* stop detect flag */
  186. if (status & LPI2C_MSR_SDF_MASK) {
  187. /* clear stop flag */
  188. status &= LPI2C_MSR_SDF_MASK;
  189. writel(status, &regs->msr);
  190. break;
  191. }
  192. if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
  193. debug("stop timeout\n");
  194. return -ETIMEDOUT;
  195. }
  196. }
  197. return result;
  198. }
  199. static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
  200. {
  201. lpi2c_status_t result;
  202. result = bus_i2c_start(bus, chip, 1);
  203. if (result)
  204. return result;
  205. result = bus_i2c_receive(bus, buf, len);
  206. if (result)
  207. return result;
  208. return result;
  209. }
  210. static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
  211. {
  212. lpi2c_status_t result;
  213. result = bus_i2c_start(bus, chip, 0);
  214. if (result)
  215. return result;
  216. result = bus_i2c_send(bus, buf, len);
  217. if (result)
  218. return result;
  219. return result;
  220. }
  221. u32 __weak imx_get_i2cclk(u32 i2c_num)
  222. {
  223. return 0;
  224. }
  225. static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
  226. {
  227. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  228. struct imx_lpi2c_reg *regs;
  229. u32 val;
  230. u32 preescale = 0, best_pre = 0, clkhi = 0;
  231. u32 best_clkhi = 0, abs_error = 0, rate;
  232. u32 error = 0xffffffff;
  233. u32 clock_rate;
  234. bool mode;
  235. int i;
  236. regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  237. if (IS_ENABLED(CONFIG_CLK)) {
  238. clock_rate = clk_get_rate(&i2c_bus->per_clk);
  239. if (clock_rate <= 0) {
  240. dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
  241. return clock_rate;
  242. }
  243. } else {
  244. clock_rate = imx_get_i2cclk(bus->seq);
  245. if (!clock_rate)
  246. return -EPERM;
  247. }
  248. mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
  249. /* disable master mode */
  250. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  251. writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
  252. for (preescale = 1; (preescale <= 128) &&
  253. (error != 0); preescale = 2 * preescale) {
  254. for (clkhi = 1; clkhi < 32; clkhi++) {
  255. if (clkhi == 1)
  256. rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
  257. else
  258. rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
  259. abs_error = speed > rate ? speed - rate : rate - speed;
  260. if (abs_error < error) {
  261. best_pre = preescale;
  262. best_clkhi = clkhi;
  263. error = abs_error;
  264. if (abs_error == 0)
  265. break;
  266. }
  267. }
  268. }
  269. /* Standard, fast, fast mode plus and ultra-fast transfers. */
  270. val = LPI2C_MCCR0_CLKHI(best_clkhi);
  271. if (best_clkhi < 2)
  272. val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
  273. else
  274. val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
  275. LPI2C_MCCR0_DATAVD(best_clkhi / 2);
  276. writel(val, &regs->mccr0);
  277. for (i = 0; i < 8; i++) {
  278. if (best_pre == (1 << i)) {
  279. best_pre = i;
  280. break;
  281. }
  282. }
  283. val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
  284. writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
  285. if (mode) {
  286. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  287. writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
  288. }
  289. return 0;
  290. }
  291. static int bus_i2c_init(struct udevice *bus, int speed)
  292. {
  293. struct imx_lpi2c_reg *regs;
  294. u32 val;
  295. int ret;
  296. regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  297. /* reset peripheral */
  298. writel(LPI2C_MCR_RST_MASK, &regs->mcr);
  299. writel(0x0, &regs->mcr);
  300. /* Disable Dozen mode */
  301. writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
  302. /* host request disable, active high, external pin */
  303. val = readl(&regs->mcfgr0);
  304. val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
  305. LPI2C_MCFGR0_HRSEL_MASK));
  306. val |= LPI2C_MCFGR0_HRPOL(0x1);
  307. writel(val, &regs->mcfgr0);
  308. /* pincfg and ignore ack */
  309. val = readl(&regs->mcfgr1);
  310. val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
  311. val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
  312. val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
  313. writel(val, &regs->mcfgr1);
  314. ret = bus_i2c_set_bus_speed(bus, speed);
  315. /* enable lpi2c in master mode */
  316. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  317. writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
  318. debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
  319. return ret;
  320. }
  321. static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
  322. u32 chip_flags)
  323. {
  324. lpi2c_status_t result;
  325. result = bus_i2c_start(bus, chip, 0);
  326. if (result) {
  327. bus_i2c_stop(bus);
  328. bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  329. return result;
  330. }
  331. result = bus_i2c_stop(bus);
  332. if (result)
  333. bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  334. return result;
  335. }
  336. static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  337. {
  338. int ret = 0, ret_stop;
  339. for (; nmsgs > 0; nmsgs--, msg++) {
  340. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  341. if (msg->flags & I2C_M_RD)
  342. ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
  343. else {
  344. ret = bus_i2c_write(bus, msg->addr, msg->buf,
  345. msg->len);
  346. if (ret)
  347. break;
  348. }
  349. }
  350. if (ret)
  351. debug("i2c_write: error sending\n");
  352. ret_stop = bus_i2c_stop(bus);
  353. if (ret_stop)
  354. debug("i2c_xfer: stop bus error\n");
  355. ret |= ret_stop;
  356. return ret;
  357. }
  358. static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  359. {
  360. return bus_i2c_set_bus_speed(bus, speed);
  361. }
  362. __weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  363. {
  364. return 0;
  365. }
  366. static int imx_lpi2c_probe(struct udevice *bus)
  367. {
  368. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  369. fdt_addr_t addr;
  370. int ret;
  371. i2c_bus->driver_data = dev_get_driver_data(bus);
  372. addr = devfdt_get_addr(bus);
  373. if (addr == FDT_ADDR_T_NONE)
  374. return -EINVAL;
  375. i2c_bus->base = addr;
  376. i2c_bus->index = bus->seq;
  377. i2c_bus->bus = bus;
  378. /* power up i2c resource */
  379. ret = init_i2c_power(bus->seq);
  380. if (ret) {
  381. debug("init_i2c_power err = %d\n", ret);
  382. return ret;
  383. }
  384. if (IS_ENABLED(CONFIG_CLK)) {
  385. ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
  386. if (ret) {
  387. dev_err(bus, "Failed to get per clk\n");
  388. return ret;
  389. }
  390. ret = clk_enable(&i2c_bus->per_clk);
  391. if (ret) {
  392. dev_err(bus, "Failed to enable per clk\n");
  393. return ret;
  394. }
  395. ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
  396. if (ret) {
  397. dev_err(bus, "Failed to get ipg clk\n");
  398. return ret;
  399. }
  400. ret = clk_enable(&i2c_bus->ipg_clk);
  401. if (ret) {
  402. dev_err(bus, "Failed to enable ipg clk\n");
  403. return ret;
  404. }
  405. } else {
  406. /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
  407. ret = enable_i2c_clk(1, bus->seq);
  408. if (ret < 0)
  409. return ret;
  410. }
  411. ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  412. if (ret < 0)
  413. return ret;
  414. debug("i2c : controller bus %d at 0x%lx , speed %d: ",
  415. bus->seq, i2c_bus->base,
  416. i2c_bus->speed);
  417. return 0;
  418. }
  419. static const struct dm_i2c_ops imx_lpi2c_ops = {
  420. .xfer = imx_lpi2c_xfer,
  421. .probe_chip = imx_lpi2c_probe_chip,
  422. .set_bus_speed = imx_lpi2c_set_bus_speed,
  423. };
  424. static const struct udevice_id imx_lpi2c_ids[] = {
  425. { .compatible = "fsl,imx7ulp-lpi2c", },
  426. { .compatible = "fsl,imx8qm-lpi2c", },
  427. {}
  428. };
  429. U_BOOT_DRIVER(imx_lpi2c) = {
  430. .name = "imx_lpi2c",
  431. .id = UCLASS_I2C,
  432. .of_match = imx_lpi2c_ids,
  433. .probe = imx_lpi2c_probe,
  434. .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
  435. .ops = &imx_lpi2c_ops,
  436. };